Signal processing method and communication device

Abstract

The present application discloses a signal processing method and a communication device for performing parallel processing of multiple sparse vectors at a receiving end to reduce latency. In the present application, a sparse signal is first acquired, and then element-mapping demodulation is performed on the sparse signal to obtain L sparse vectors, where L is an integer greater than or equal to 2. Then, parallel symbol inverse mapping is performed on at least two of the L sparse vectors to obtain at least two bit sequences. Compared with serial symbol inverse mapping, this method reduces processing time and latency.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a signal processing method and a communication device. Background Art

[0002] Orthogonal sparse recurrent codes (OSRCs) are based on the sparse recurrent code structure and incorporate serial coding techniques. They are primarily targeted at low-bitrate, short-code-length applications. On the transmitter side, the OSR coding scheme is serial coding, which sequentially selects a group of nonzero elements, ensuring that the positions of the nonzero elements in each group do not overlap. On the receiver side, serial erasure decoding is primarily used to decode the OSRs, which can lead to significant latency. Summary of the Invention

[0003] Embodiments of the present application provide a signal processing method and a communication device for performing parallel processing on multiple sparse vectors at a receiving end to reduce latency.

[0004] In a first aspect, the present application proposes a signal processing method, comprising:

[0005] First, a sparse signal is acquired, and then element-mapping demodulation is performed on the sparse signal to obtain L sparse vectors, where L is an integer greater than or equal to 2. Then, parallel sign inverse mapping is performed on at least two of the L sparse vectors to obtain at least two bit sequences. Compared with serial sign inverse mapping, this method reduces processing time and latency.

[0006] In some possible implementations, a wireless signal is received, and OFDM demodulation is performed on the wireless signal to obtain the sparse signal, which can then be used in a multipath fading channel.

[0007] In some possible implementations, parallel symbol inverse mapping is performed on the L sparse vectors to obtain L bit sequences, thereby maximizing the reduction in latency.

[0008] In some possible implementations, the L bit sequences are combined to obtain a target bit sequence, the target bit sequence is deinterleaved to obtain coded information, and the coded information is decoded to restore binary information bits.

[0009] In some possible implementations, the decoding process is an inverse operation of a cyclic redundancy check (CRC) or an inverse operation of a low-density parity check (LDPC) code, thereby verifying the accuracy of the sparse signal.

[0010] The second aspect of the present application provides a signal processing method, comprising:

[0011] Symbol mapping is performed on L bit sequences to obtain L sparse vectors, and element mapping modulation is performed on the L sparse vectors according to L power values ​​to obtain a sparse signal. Since the power difference between any two power values ​​in the L power values ​​is not less than the preset power difference, the size of the power difference can be guaranteed, thereby making it easier for the first communication device as the receiving end to distinguish different sparse vectors.

[0012] In some possible implementations, the lengths of the L sparse vectors are the same, making calculations on them easier.

[0013] In some possible implementations, OFDM modulation is performed on the sparse signal to obtain a wireless signal, and the wireless signal is sent, which can be used in a multipath fading channel.

[0014] In some possible implementations, binary information bits are obtained, the binary information bits are encoded to obtain encoded information, the encoded information is interleaved to obtain the target bit sequence, and the target bit sequence is divided to obtain the L bit sequences.

[0015] In some possible implementations, the encoding process is CRC or LDPC, so as to verify the accuracy of the sparse signal.

[0016] In a third aspect, the present application provides a communication device, which is specifically a first communication device, and the first communication device is used to execute any method described in any one of the first aspects.

[0017] In a fourth aspect, the present application provides a communication device, which is specifically a second communication device, and the first communication device is used to execute any method described in any one of the first aspects.

[0018] In a fifth aspect, the present application provides a communication system, comprising: a first communication device and a second communication device, wherein:

[0019] The first communication device is configured to execute any one of the methods executed by the first communication device in the third aspect;

[0020] The second communication device is used to execute any one of the methods executed by the second communication device in the fourth aspect.

[0021] In a sixth aspect, the present application provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is run on a computer, it enables the computer to execute any one of the methods in the first, second or third aspects above.

[0022] In a seventh aspect, the present application provides a computer program product, which includes computer-executable instructions, which are stored in a computer-readable storage medium; at least one processor of the device can read the computer-executable instructions from the computer-readable storage medium, and at least one processor executes the computer-executable instructions so that the device implements the method provided by the above-mentioned first aspect or any possible implementation of the first aspect.

[0023] In an eighth aspect, the present application provides a communication device, which may include at least one processor, a memory, and a communication interface. The at least one processor is coupled to the memory and the communication interface. The memory is configured to store instructions, the at least one processor is configured to execute the instructions, and the communication interface is configured to communicate with other communication devices under the control of the at least one processor. When executed by the at least one processor, the instructions cause the at least one processor to perform the method of the first aspect or any possible implementation of the first aspect.

[0024] In a ninth aspect, the present application provides a chip system, which includes a processor for supporting a communication device to implement the functions involved in the first aspect or any possible implementation of the first aspect.

[0025] In one possible design, the chip system may further include a memory for storing program instructions and data necessary for the communication device. The chip system may be composed of a chip or may include a chip and other discrete devices.

[0026] Among them, the technical effects brought about by the second to ninth aspects or any possible implementation methods thereof can refer to the technical effects brought about by the first aspect or different possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the architecture of a mobile communication system used in the embodiments of the present application;

[0028] Figure 2 This is a schematic diagram of an embodiment of a signal processing method proposed in this application;

[0029] Figure 3-1 This is a schematic diagram of an embodiment of a signal processing method proposed in this application;

[0030] Figure 3-2 Schematic diagram of an embodiment of an orthogonal sparse recursive code in this application;

[0031] Figure 3-3 This is a schematic diagram of an embodiment of implementing multi-user encoding and decoding in this application;

[0032] Figure 3-4A schematic diagram of an embodiment in which a second communication device generates and transmits a wireless signal based on binary information bits;

[0033] Figure 3-5 A schematic diagram of an embodiment of a first communication device receiving a sparse signal and restoring the signal to a target bit sequence;

[0034] Figure 3-6 The simulation experiment diagrams of orthogonal sparse recursive codes in serial erasure decoding scheme, parallel erasure decoding scheme and polar code in serial erasure decoding scheme are shown;

[0035] Figure 3-7 Another simulation experiment diagram of the serial erasure decoding scheme, the parallel erasure decoding scheme, and the serial erasure decoding scheme of the orthogonal sparse recursive code;

[0036] Figure 3-8 Another simulation experiment diagram of the serial erasure decoding scheme, the parallel erasure decoding scheme, and the serial erasure decoding scheme of the orthogonal sparse recursive code;

[0037] Figure 4 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0038] Figure 5 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0039] Figure 6 A schematic structural diagram of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] Embodiments of the present application provide a signal processing method and a communication device for performing parallel processing on multiple sparse vectors at a receiving end to reduce latency.

[0041] The embodiments of the present application are described below with reference to the accompanying drawings.

[0042] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, and this is merely a way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0043] The technical solutions of the embodiments of the present application can be applied to various communication systems, such as code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal frequency-division multiple access (OFDMA), single carrier frequency division multiple access (SC-FDMA) and other systems. The term "system" and "network" can be used interchangeably. A CDMA system can implement wireless technologies such as universal terrestrial radio access (UTRA) and CDMA2000. UTRA can include wideband CDMA (WCDMA) technology and other CDMA variants. CDMA2000 can cover interim standard (IS) 2000 (IS-2000), IS-95 and IS-856 standards. A TDMA system can implement wireless technologies such as global system for mobile communication (GSM). The OFDMA system can implement wireless technologies such as evolved universal radio terrestrial access (Evolved UTRA, E-UTRA), ultra mobile broadband (UMB), IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE802.20, Flash OFDMA, etc. UTRA and E-UTRA are UMTS and UMTS evolved versions. 3GPP's long term evolution (LTE) and various versions based on LTE evolution are new versions of UMTS using E-UTRA. The technical solutions of the embodiments of the present application can also be applied to the new radio (NR) system in the fifth generation (5G) mobile communication system of the long term evolution (LTE) system and future mobile communication systems.

[0044] The system architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field will know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0045] like Figure 1 , which is a schematic diagram of the architecture of a mobile communication system used in an embodiment of the present application. The mobile communication system 100 includes a first communication device 110 and a second communication device 120. The first communication device 110 or the second communication device 120 may be a core network device, a wireless access network device, or a terminal device. The terminal device is wirelessly connected to the wireless access network device, and the wireless access network device is wirelessly or wiredly connected to the core network device.

[0046] Terminal devices can be called terminals, user equipment (UE), mobile stations (MS), mobile terminals (MT), etc. Terminal devices can be mobile phones, tablet computers, computers with wireless transceiver functions, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc. The embodiments of the present application do not limit the specific technology and specific device form adopted by the terminal devices.

[0047] The wireless access network device is an access device that the terminal device uses to access the mobile communication system wirelessly. It can be a base station NodeB, an evolved NodeB (eNB), a transmission reception point (TRP), a next-generation base station (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system. The embodiments of this application do not limit the specific technology and specific device form used by the wireless access network device.

[0048] The core network equipment and the radio access network equipment can be independent, distinct physical devices, or the functions of the core network equipment and the logical functions of the radio access network equipment can be integrated into the same physical device. Alternatively, a single physical device can integrate some of the functions of the core network equipment and some of the functions of the radio access network equipment. Terminal devices can be fixed or mobile. It should be noted that the core network equipment, radio access network equipment, and terminal devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on aircraft, drones, balloons, and satellites. The embodiments of this application do not limit the application scenarios of network devices and terminal devices. In the embodiments of this application, the terminal device or network device includes a hardware layer, an operating system layer running on the hardware layer, and an application layer running on the operating system layer. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and memory (also known as main memory). The operating system can be any one or more computer operating systems that implement service processing through processes, such as the Linux operating system, the Unix operating system, the Android operating system, the iOS operating system, or the Windows operating system. The application layer includes applications such as browsers, address books, word processing software, and instant messaging software. Furthermore, the embodiments of the present application do not particularly limit the specific structure of the execution subject of the method provided in the embodiments of the present application. As long as it is possible to communicate according to the method provided in the embodiments of the present application by running a program that records the code of the method provided in the embodiments of the present application, for example, the execution subject of the method provided in the embodiments of the present application may be a wireless access network device or a terminal device, or a functional module in the terminal device or access network device that can call and execute a program.

[0049] It should be noted that Figure 1 The communication system may also include other network devices, such as wireless relay devices and wireless backhaul devices. Figure 1The embodiments of the present application do not limit the number of core network devices, wireless access network devices, and terminal devices included in the mobile communication system.

[0050] In addition, various aspects or features of the present application can be implemented as methods, devices or products using standard programming and / or engineering techniques. The term "product" as used in this application covers computer programs that can be accessed from any computer-readable device, carrier or medium. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks or tapes, etc.), optical disks (e.g., compact discs (CDs), digital versatile discs (DVDs), etc.), smart cards and flash memory devices (e.g., erasable programmable read-only memories (EPROMs), cards, sticks or key drives, etc.). In addition, the various storage media described herein may represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing and / or carrying instructions and / or data.

[0051] Currently, when transmitting information over an error-prone channel, when the transmission rate is less than the channel capacity, according to Shannon's channel coding theorem, a coding scheme exists that can achieve error-free transmission. Since Shannon proposed the channel coding theorem, developing low-complexity coding and decoding schemes that approach the Shannon limit has been a major goal in information theory and coding research. Examples include long codes with pseudo-random properties (turbo codes), low-density parity-check codes (LDPC codes), polar codes that approach the Shannon limit, and spatially coupled LDPC codes.

[0052] Among them, sparse recurrent codes are a coding scheme that can achieve Shannon capacity. They use position modulation to map the transmitted information bits into a sparse vector, and then, through compressed sensing, transform the sparse vector through a compression matrix to obtain the transmitted codeword. After passing through a Gaussian additive noise channel, an approximate message passing algorithm can be used to recover the signal at the receiver. Combined with power allocation and spatial coupling, sparse recurrent codes can achieve channel capacity under the conditions of an approximate message passing (AMP) algorithm.

[0053] Orthogonal sparse recurrent codes (OSRCs) are based on the sparse recurrent code structure and incorporate the concept of serial coding, primarily targeting low-bitrate, short-code-length applications. On the transmitter side, the OSR coding scheme is serial coding, which sequentially selects a group of nonzero elements, ensuring that the positions of the nonzero elements in each group do not overlap. On the receiver side, the OSR codes are primarily decoded using a serial erasure decoding scheme. However, this scheme decodes the OSR layer by layer in a serial manner. Layer-by-layer decoding is serial, requiring the decoding of the previous layer to complete and be subtracted from the received signal before decoding the next layer. This decoding scheme can introduce significant latency issues.

[0054] To do this, refer to Figure 2 In the present application, a signal processing method and a communication device are proposed. First, (1) a sparse signal is acquired. Then, (2) element-mapping demodulation is performed on the sparse signal according to L power values ​​to obtain at least two sparse vectors among the L sparse vectors, where L is an integer greater than or equal to 2. Then, (3) parallel symbol inverse mapping is performed on the at least two sparse vectors to obtain at least two bit sequences. Compared with serial symbol inverse mapping, the processing time is reduced and the delay is lowered.

[0055] The above scheme is described in detail below.

[0056] Please refer to Figure 3-1 , is a signal processing method proposed in this application, the method comprising:

[0057] 301. The second communication device encodes binary information bits to obtain encoded information.

[0058] In the embodiment of the present application, the binary information bit d can be a vector whose elements are either 0 or 1, such as a 10-dimensional vector (010001011100). In some feasible implementations, the second communication device can encode d to obtain encoded information c. It should be noted that c can also be a vector whose elements are either 0 or 1, such as (101110010110).

[0059] In some feasible implementations, the coding process may include a cyclic redundancy check (CRC) or a low-density parity check code (LDPC) to protect a portion of the information bits in d so that it has an error-detecting function. The first communication device at the receiving end may use CRC or LDPC to detect whether the potential codeword is correct, thereby helping to successfully decode the code. It should be noted that a binary encoder may be built into the second communication device, and d is encoded by the binary encoder. In an embodiment of the present application, the ability of the coding method to resist fading is enhanced by the design of the outer code cascade, while helping to improve the performance degradation problem of the code rate increase. By improving the performance of the overall coding scheme against errors, it can be used for transmission in a fading channel.

[0060] 302. The second communication device performs interleaving processing on the encoded information to obtain a target bit sequence.

[0061] In the embodiment of the present application, the second communication device can perform interleaving processing (which can be recorded as π) on the coded information c to obtain the target bit sequence u. It should be noted that interleaving is a technology used for data processing in mobile communication systems, which can maximally change the structure of the information (d) without changing the information content. It should be noted that the target bit sequence u∈F2 B , F2 B represents a binary field of length B. For example, if B is 10, then F2 B The elements in F2 are vectors of length 10, the number of elements in the vector is 10, and its elements are either 0 or 1 (binary bits), for example, (0100100101)∈F2 B .

[0062] 303. The second communication device divides the target bit sequence into L blocks to obtain L bit sequences.

[0063] In the embodiment of the present application, the second communication device may have a built-in bit splitter to divide the target bit sequence u into L blocks to obtain L bit sequences ui (i = 1, 2, ..., L), that is, u∈F2 B Divide into L blocks {u1,u2,…,uL}, where ui∈F2 Bi , Bi is the binary field F2 Bi The length of the elements in , for example, the length of ui(i=1,2,…,L) is Bi(i=1,2,…,L). It should be noted that the lengths of ui(i=1,2,…,L) can be different or the same, that is, B1=B2=…=BL, and this is not limited here.

[0064] For example, u=(0100100101), L=4, B1=3, B2=3, B3=2, B4=2, then u1=(010)∈F2 3 , u2=(010)∈F2 3 , u3=(01)∈F2 2 , u4=(01)∈F2 2 For another example, u=(010010010101), L=3, B1=4, B2=4, B3=4, then u1=(0100)∈F2 4 , u2=(1001)∈F2 4 , u3=(0101)∈F2 4 .

[0065] 304. The second communication device performs symbol mapping on the L bit sequences respectively to obtain L sparse vectors.

[0066] In an embodiment of the present application, after the second communication device generates a bit sequence ui (i = 1, 2, ..., L), it can perform symbol mapping on each of the L bit sequences ui (i = 1, 2, ..., L) to obtain L sparse vectors xi (i = 1, 2, ..., L), where ui corresponds to xi. For example, the L sparse vectors xi (i = 1, 2, ..., L) include x1 and x2, where x1 corresponds to u1 and x2 corresponds to u2.

[0067] It should be noted that the symbol mapping is used to map each ui into a sparse vector xi of the same length (e.g., length N), where xi can be an orthogonal sparse recursive code and xi has Ki non-zero elements. For example, the mapping relationship of the symbol mapping is as follows: Figure 3-2 As shown, the Bi binary information bits in ui are divided into two parts. The first part is used to select the position of the non-zero element in xi (denoted as Ii). That is, the binary information bits in the first part are used for index selection through Ki and Ni (i.e., Bi), i.e., position modulation. The second part of the binary information bits is used for modulation mapping, and the constellation used for the modulation symbol is denoted as Ai. In some feasible implementations, Ai = A (i = 1, 2, ..., L), that is, for all xi, the constellation Ai used is the same, and this constellation is used for quadrature phase shift keying (QPSK) modulation.

[0068] In some feasible implementations, after the symbol mapping of ui (i = 1, 2, ..., L-1), the non-zero element positions selected in order to obtain xi (i = 1, 2, ..., L-1) need to be non-conflicting. In some feasible implementations, such as Figure 3-2 As shown, after generating x(i+1), the Ki non-zero element positions Ii in x(i+1) that have been selected by x(i) are removed, resulting in the non-zero element position I(i+1) of x(i+1). Then, when generating x(i+2), the K(i+1) non-zero element positions I(i+1) in x(i+2) that have been selected by x(i+1) are removed, resulting in the non-zero element position I(i+2) of x(i+2). This is done by analogy, ensuring that the non-zero element positions Ki(i=1,2,…,L) selected by any ui(i=1,2,…,L) do not have overlapping non-zero element positions, making {x1,x2,…,xL} orthogonal. For example, remove the K1 non-zero element positions I1 in x2 that have been selected by x1 to obtain the non-zero element position I2 in x2; remove the K2 non-zero element positions I1 in x3 that have been selected by x2 to obtain the non-zero element position I3 in x3. Similarly, the KL non-zero element positions selected in xL have been removed, and I1∪I2∪…∪I(L-1) has been removed, resulting in IL.

[0069] Orthogonal sparse recurrent codes have the characteristics of low rate and short code length. In some feasible implementations of the encoding and decoding method based on orthogonal sparse recurrent codes, ui (i = 1, 2, ..., L) can be regarded as information from multiple different users. For example, Figure 3-3 , let uk be the user k information sequence, obtain the user k information sequence (i = 1, 2, ..., K), generate K sparse vectors ck (i = 1, 2, ..., K) through the orthogonal sparse regression encoder k, and then generate the wireless signal y subsequently, so that the first communication device as the receiving end can be restored to the information sequence k (i = 1, 2, ..., K) through the orthogonal sparse decoder, so as to realize multi-user encoding and decoding or large-scale machine-type communication encoding and decoding, which helps to support low-speed access and short packet data transmission of massive devices.

[0070] 305. The second communication device performs element mapping modulation on the L sparse vectors according to the L power values ​​to obtain a sparse signal.

[0071] In the embodiment of the present application, L sparse vectors xi (i=1, 2, ..., L) can be generated into a sparse signal x through element mapping modulation.

[0072] For example, after setting the power Pi (i = 1, 2, ..., L), the following calculation can be performed to obtain the sparse signal x:

[0073]

[0074] It should be noted that, in order to distinguish between sparse vectors xi (i=1, 2, ..., L) by energy, when allocating power between the sparse vectors xi (i=1, 2, ..., L), the energy difference can be as large as possible. For example, the power difference between the powers Pi (i=1, 2, ..., L) can be set to be no less than a preset power difference, so that the first communication device as the receiving end can more easily detect different sparse vectors xi (i=1, 2, ..., L) when receiving x.

[0075] 306. The second communication device performs OFDM modulation on the sparse signal to obtain a wireless signal.

[0076] In an embodiment of the present application, the second communication device performs OFDM modulation on the sparse signal x to obtain a wireless signal y. In some feasible implementations, a cyclic prefix (CP) may be added after the OFDM modulation, which is not limited here. It should be noted that due to the use of OFDM modulation, the wireless signal y can be transmitted in a multipath fading channel. In an embodiment of the present application, the OFDM scheme based on orthogonal sparse recurrent codes can be applied to multipath fading channels, thereby counteracting the multipath effects in the fading channel.

[0077] 307. The second communication device sends a wireless signal to the first communication device.

[0078] In the embodiment of the present application, the second communication device can send a wireless signal y to the first communication device via an antenna. It should be noted that, due to the use of OFDM demodulation, the wireless signal y can be received in a multipath fading channel.

[0079] The above describes an embodiment in which the second communication device generates a sparse signal from binary information bits and sends the signal through steps 301-307. Figure 3-4 The figure shows the process of the second communication device generating a wireless signal y from binary bit information d and sending it, including steps 301 to 307. The following describes the process of the first communication device acquiring a sparse signal and restoring it to binary information bits through steps 308 to 313.

[0080] 308. The first communication device performs OFDM demodulation on the wireless signal to obtain a sparse signal.

[0081] In this embodiment of the present application, when the first communication device receives a wireless signal y via an antenna, it can remove the CP and then perform OFDM demodulation on the CP-removed y to obtain a sparse signal x. In this embodiment of the present application, the OFDM scheme based on orthogonal sparse recurrent codes can be applied to multipath fading channels, thereby combating the multipath effects in fading channels.

[0082] Among them, such as Figure 3-5 As shown, the process of the first communication device receiving the sparse signal and restoring it to the target bit sequence includes step 309, step 310 and step 311.

[0083] 309. The first communication device performs element mapping demodulation on the sparse signal to obtain L sparse vectors.

[0084] In an embodiment of the present application, the first communication device may perform element-mapping demodulation on the sparse signal x to obtain L sparse vectors xi (i=1, 2, ..., L).

[0085] It should be noted that since the L sparse vectors xi (i = 1, 2, ..., L) are orthogonal, any element in x belongs to any one of xi (i = 1, 2, ..., L). For an element in x, its power can be used to determine which sparse vector xi it belongs to.

[0086] For example, if the first communication device has power Pi (i=1, 2, ..., L), if x* is an element in x, obtain the power of x* and match it with Pi (i=1, 2, ..., L). If the power of x* is the same as P1, since:

[0087]

[0088] Then x* is an element of x1.

[0089] By analogy, the sparse vector described by each element in x can be obtained, thereby obtaining L sparse vectors xi (i=1, 2, ..., L).

[0090] In some feasible implementations, if the first communication device does not have power Pi (i = 1, 2, ..., L), then the first communication device can perform energy detection on each element in x, and divide it according to the size of the energy, and combine elements with equal power into a sparse vector, thereby obtaining L sparse vectors xi (i = 1, 2, ..., L).

[0091] In some feasible implementations, the first communication device may perform element mapping demodulation on the sparse signal to obtain at least 2 sparse vectors among the L sparse vectors, or may obtain all sparse vectors among the L sparse vectors, which is not limited here.

[0092] 310. The first communication device performs parallel symbol inverse mapping on the L sparse vectors to obtain L bit sequences.

[0093] In an embodiment of the present application, after generating at least two sparse vectors in xi (i = 1, 2, ..., L), such as x1 and x2, parallel symbol inverse mapping can be performed to obtain bit sequence u1 and bit sequence u2, where u1 corresponds to x1 and u2 corresponds to x2. In some feasible implementations, after generating all sparse vectors in xi (i = 1, 2, ..., L), parallel symbol inverse mapping can be performed to obtain L bit sequences ui (i = 1, 2, ..., L), where ui corresponds to xi. Compared with serial symbol inverse mapping, the processing time is reduced and the latency is lowered. It should be noted that step 310 is the inverse operation of step 305. In an embodiment of the present application, the first communication device performs parallel symbol inverse mapping on at least two sparse vectors in L bit sequences to obtain L bit sequences, which is called a parallel elimination decoding scheme.

[0094] 311. The first communication device combines L bit sequences to obtain a target bit sequence.

[0095] In the embodiment of the present application, after generating L bit sequences ui (i=1, 2, ..., L), the L bit sequences ui (i=1, 2, ..., L) can be combined to obtain a binary information bit sequence u. It should be noted that step 311 and step 303 are inverse operations.

[0096] For example, L = 4, B1 = 3, B2 = 3, B3 = 2, B4 = 2, u1 = (010) ∈ F2 3 , u2=(010)∈F2 3 , u3=(01)∈F2 2 , u4=(01)∈F2 2 , then, u=(0100100101). For another example, L=3, B1=4, B2=4, B3=4, then u1=(0100)∈F2 4 , u2=(1001)∈F2 4 , u3=(0101)∈F2 4 , then, u=(010010010101). Where Bi is the binary field F2 Bi The length of each block does not need to be exactly the same, that is, Bi and Bj are not necessarily the same. If i and j are not equal, i∈{1,2,…,L} and j∈{1,2,…,L}.

[0097] 312. The first communication device performs deinterleaving processing on the target bit sequence to obtain coded information.

[0098] In the embodiment of the present application, when generating the target bit sequence u∈F2 B, u can be deinterleaved to obtain the coded information c. It should be noted that step 312 is the inverse operation of step 302. It should be noted that a bit splitter can be built into the second communication device to deinterleave u to obtain c. In the embodiment of the present application, bit-level interleaving or symbol-level interleaving can facilitate multi-user non-orthogonal access time-frequency resources for transmission.

[0099] 313. The first communication device decodes the encoded information to obtain binary information bits. The decoding process is an inverse operation of CRC or an inverse operation of LDPC.

[0100] In this embodiment of the present application, the encoded information c can be decoded to obtain binary information bits d. It should be noted that step 313 and step 301 are inverse operations. In some feasible implementations, the binary channel encoder (binary encoder) can also be a binary channel decoder (binary decoder). In this embodiment of the present application, the first communication device can perform an inverse CRC operation on c through a binary channel decoder (binary decoder) to further perform error detection and correction on the decoding.

[0101] For example, please refer to Figure 3-6 、 Figure 3-7 、 Figure 3-8 The frame error rate (FER) performance of orthogonal sparse recursive codes under parallel erasure decoding scheme, serial erasure decoding scheme and polar code under serial erasure decoding are compared under the same code length conditions.

[0102] like Figure 3-6 As shown in Figure 1, the code length of the polar code is (128, 14), the code length of the serial cancellation decoding scheme (Orthogonal-sparse representation-based classifier serial canceller, O-SRC SC) is (129, 14), and the code length of the parallel cancellation decoding scheme (Orthogonal-sparse representation-based classifier parallel canceller, O-SRC PC) is (129, 14). The code length (N, K) indicates that the length before encoding is K and the length after encoding is N. Figure 3-7 As shown in Figure 2, the code length of the polar code is (256, 16), the code length of the serial erasure decoding scheme (O-SRCSC) is (257, 16), and the code length of the parallel erasure decoding scheme (O-SRC PC) is (257, 16). Figure 3-8 As shown in FIG, the code length of the polar code is (512, 18), the code length of the serial erasure decoding scheme (O-SRC SC) is (513, 18), and the code length of the parallel erasure decoding scheme (O-SRC PC) is (513, 18).

[0103] exist Figure 3-6 、 Figure 3-7 、 Figure 3-8 In the three simulation experiment figures, the solid line represents the FER performance of orthogonal sparse recurrent codes under serial cancellation decoding (O-SRC SC), the solid squares represent the FER performance of orthogonal sparse recurrent codes under parallel cancellation decoding (O-SRC PC), and the dashed line represents the frame error rate performance of polar codes under serial cancellation decoding. The horizontal axis is the signal-to-noise ratio (SNR), and the vertical axis is the FRR.

[0104] From above Figure 3-6 、 Figure 3-7 、 Figure 3-8 It can be seen that the parallel erasure decoding scheme proposed in this invention has essentially the same frame error rate performance as the serial erasure decoding scheme. Compared to the original serial erasure decoding, the parallel erasure decoding scheme reduces latency. Furthermore, compared to the FRR of polar codes under serial erasure decoding, the parallel erasure decoding scheme proposed in this application has a certain performance gain.

[0105] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0106] In order to better implement the above-mentioned solutions of the embodiments of the present application, relevant devices for implementing the above-mentioned solutions are also provided below.

[0107] See also Figure 4 As shown, a communication device 400 provided in an embodiment of the present application may include: a transceiver module 401 and a processing module 402, wherein:

[0108] The transceiver module 401 is configured to obtain a sparse signal.

[0109] The processing module 402 is further configured to perform element mapping demodulation on the sparse signal to obtain L sparse vectors, where L is an integer greater than or equal to 2.

[0110] The processing module 402 is further configured to perform parallel sign inverse mapping on at least two sparse vectors among the L sparse vectors to obtain at least two bit sequences.

[0111] In some possible implementations, the transceiver module 401 is configured to receive wireless signals.

[0112] The processing module 402 is further configured to perform OFDM demodulation on the wireless signal to obtain a sparse signal.

[0113] In some possible implementations, the processing module 402 is further configured to perform parallel sign inverse mapping on the L sparse vectors to obtain L bit sequences.

[0114] In some possible implementations, the processing module 402 is further configured to combine L bit sequences to obtain a target bit sequence, perform deinterleaving on the target bit sequence to obtain coded information, and perform decoding on the coded information to obtain binary information bits.

[0115] In some possible implementations, the decoding process is an inverse operation of a cyclic redundancy check (CRC) or an inverse operation of a low-density parity check (LDPC) code.

[0116] See also Figure 5 As shown, a communication device 500 provided in an embodiment of the present application may include: a processing module 501 and a transceiver module 502, wherein:

[0117] The processing module 501 is configured to perform symbol mapping on L bit sequences to obtain L sparse vectors.

[0118] The processing module 501 is further configured to perform element mapping modulation on the L sparse vectors according to the L power values ​​to obtain a sparse signal, wherein the power difference between any two power values ​​in the L power values ​​is not less than a preset power difference.

[0119] In some possible implementations, the lengths of the L sparse vectors are the same.

[0120] In some possible implementations, the processing module 501 is further configured to perform OFDM modulation on the sparse signal to obtain a wireless signal.

[0121] The transceiver module 502 is configured to send wireless signals.

[0122] In some possible implementations, the transceiver module 502 is further configured to obtain binary information bits.

[0123] The processing module 501 is further configured to perform encoding processing on the binary information bits to obtain encoded information, perform interleaving processing on the encoded information to obtain a target bit sequence, and divide the target bit sequence to obtain L bit sequences.

[0124] In some possible implementations, the encoding process is CRC or LDPC.

[0125] It should be noted that the information interaction, execution process, etc. between the modules / units of the above-mentioned device are based on the same concept as the method embodiment of the present application, and the technical effects they bring are the same as those of the method embodiment of the present application. For specific contents, please refer to the description in the method embodiment shown above in the present application, and no further details will be given here.

[0126] An embodiment of the present application further provides a computer storage medium, wherein the computer storage medium stores a program, and the program executes some or all of the steps recorded in the above method embodiment.

[0127] Next, another communication device provided by the embodiment of the present application is introduced. Figure 6 As shown, the communication device 600 includes:

[0128] Receiver 601, transmitter 602, processor 603 and memory 604. In some embodiments of the present application, the receiver 601, transmitter 602, processor 603 and memory 604 may be connected via a bus or other means, wherein: Figure 6 The bus connection is taken as an example.

[0129] The memory 604 may include a read-only memory and a random access memory, and provides instructions and data to the processor 603. A portion of the memory 604 may also include non-volatile random access memory (NVRAM). The memory 604 stores an operating system and operating instructions, executable modules, or data structures, or a subset or an extension thereof. The operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks.

[0130] Processor 603 controls the operation of communication device 600 and may also be referred to as a central processing unit (CPU). In specific applications, the various components of communication device 600 are coupled together via a bus system. In addition to a data bus, the bus system may also include a power bus, a control bus, and a status signal bus. However, for clarity, all bus systems are referred to as a bus system in the figure.

[0131] The methods disclosed in the above embodiments of the present application can be applied to or implemented by processor 603. Processor 603 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits or software instructions in processor 603. The above processor 603 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can be located in storage media such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other well-known storage media in the art. The storage medium is located in the memory 604 , and the processor 603 reads the information in the memory 604 and completes the steps of the above method in combination with its hardware.

[0132] The receiver 601 may be used to receive input digital or character information and generate signal input related to the relevant settings and function control of XXX. The transmitter 602 may include a display device such as a display screen. The transmitter 602 may be used to output digital or character information through an external interface.

[0133] In the embodiment of the present application, the processor 603 is configured to execute the signal processing method executed by the aforementioned first communication device and the second communication device.

[0134] In another possible design, when the communication device 500 or the communication device 600 is a chip, it includes: a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin, or a circuit. The processing unit may execute computer-executable instructions stored in the storage unit to enable the chip in the terminal to execute the method for sending wireless report information of any one of the above-mentioned first aspects. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc. The storage unit may also be a storage unit in the terminal located outside the chip, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0135] The processor mentioned in any of the above may be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the above method.

[0136] It should also be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0137] Through the description of the above embodiments, it is clear to those skilled in the art that the present application can be implemented by means of software plus necessary general-purpose hardware, and of course it can also be implemented by means of dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. In general, all functions performed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be various, such as analog circuits, digital circuits, or dedicated circuits, etc. However, for the present application, software program implementation is a better implementation method in most cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0138] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0139] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, a server, or a data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, a computer, a server, or a data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium can be a magnetic medium, (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid-state drive (SSD)).

Claims

1. A signal processing method, characterized in that: include: Get sparse signals; Performing element mapping demodulation on the sparse signal to obtain L sparse vectors, where L is an integer greater than or equal to 2; Performing parallel sign inverse mapping on at least two of the L sparse vectors to obtain at least two bit sequences.

2. The method according to claim 1, characterized in that The method further comprises: Receive wireless signals; Perform OFDM demodulation on the wireless signal to obtain the sparse signal.

3. The method according to claim 2, characterized in that The performing parallel sign inverse mapping on at least two of the L sparse vectors to obtain at least two bit sequences includes: Performing parallel sign inverse mapping on the L sparse vectors to obtain L bit sequences.

4. The method according to claim 3, characterized in that The method further comprises: Merging the L bit sequences to obtain a target bit sequence; Performing deinterleaving processing on the target bit sequence to obtain coded information; The coded information is decoded to obtain binary information bits.

5. The method according to claim 4, characterized in that: The decoding process is an inverse operation of a cyclic redundancy check CRC or an inverse operation of a low-density parity check code LDPC.

6. A signal processing method, characterized in that: include: Perform symbol mapping on L bit sequences to obtain L sparse vectors, where L is an integer greater than or equal to 2; The L sparse vectors are element-mapped and modulated according to the L power values ​​to obtain a sparse signal, and a power difference between any two power values ​​in the L power values ​​is not less than a preset power difference.

7. The method according to claim 6, characterized in that The lengths of the L sparse vectors are the same.

8. The method according to claim 6 or 7, characterized in that: The method further comprises: Performing OFDM modulation on the sparse signal to obtain a wireless signal; The wireless signal is transmitted.

9. The method according to claim 8, characterized in that The method further comprises: Obtaining binary information bits; performing encoding processing on the binary information bits to obtain encoded information; performing interleaving processing on the coded information to obtain a target bit sequence; The target bit sequence is divided to obtain the L bit sequences.

10. The method according to claim 9, characterized in that: The encoding process is CRC or LDPC.

11. A communication device, characterized in that: include: a transceiver module for acquiring sparse signals; a processing module, configured to perform element-mapping demodulation on the sparse signal to obtain L sparse vectors, where L is an integer greater than or equal to 2; The processing module is further configured to perform parallel sign inverse mapping on at least two of the L sparse vectors to obtain at least two bit sequences.

12. The communication device according to claim 11, characterized in that: The transceiver module is used to receive wireless signals; The processing module is further configured to perform OFDM demodulation on the wireless signal to obtain the sparse signal.

13. The communication device according to claim 12, characterized in that: The processing module is further configured to perform parallel sign inverse mapping on the L sparse vectors to obtain L bit sequences.

14. The communication device according to claim 13, characterized in that: The processing module is further configured to combine the L bit sequences to obtain a target bit sequence, perform deinterleaving on the target bit sequence to obtain coded information, and perform decoding on the coded information to obtain binary information bits.

15. The communication device according to claim 14, characterized in that: The decoding process is an inverse operation of a cyclic redundancy check CRC or an inverse operation of a low-density parity check code LDPC.

16. A communication device, characterized in that: include: a processing module, configured to perform symbol mapping on the L bit sequences to obtain L sparse vectors, where L is an integer greater than or equal to 2; The processing module is further configured to perform element mapping modulation on the L sparse vectors according to the L power values ​​to obtain a sparse signal, wherein the power difference between any two power values ​​among the L power values ​​is not less than a preset power difference.

17. The communication device according to claim 16, characterized in that: The lengths of the L sparse vectors are the same.

18. The communication device according to claim 16 or 17, characterized in that: The processing module is further configured to perform OFDM modulation on the sparse signal to obtain a wireless signal; The transceiver module is used to send the wireless signal.

19. The communication device according to claim 18, characterized in that: The transceiver module is further used to obtain binary information bits; The processing module is further configured to perform encoding processing on the binary information bits to obtain encoded information, perform interleaving processing on the encoded information to obtain a target bit sequence, and divide the target bit sequence to obtain the L bit sequences.

20. The communication device according to claim 19, characterized in that: The encoding process is CRC or LDPC.

21. A communication system, characterized in that: include: A first communication device and a second communication device, wherein The first communication device is configured to execute the method according to any one of claims 1 to 5; The second communication device is configured to execute the method according to any one of claims 6 to 10.

22. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a program, and the program causes a computer device to execute the method according to any one of claims 1 to 10.

23. A computer program product, characterized in that The computer program product includes computer-executable instructions, which are stored in a computer-readable storage medium; at least one processor of a device reads the computer-executable instructions from the computer-readable storage medium, and the at least one processor executes the computer-executable instructions so that the device performs the method according to any one of claims 1 to 10.

24. A communication device, characterized in that: The communication device includes at least one processor, a memory and a communication interface; the at least one processor coupled to the memory and the communication interface; The memory is used to store instructions, the processor is used to execute the instructions, and the communication interface is used to communicate with other communication devices under the control of the at least one processor; When the instructions are executed by the at least one processor, the at least one processor is caused to perform the method according to any one of claims 1 to 10.

25. A chip system, characterized in that: The chip system includes a processor and a memory, the memory and the processor are interconnected via a line, instructions are stored in the memory, and the processor is used to execute the method according to any one of claims 1 to 10.

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