PWM signal conversion circuit, method and LED dimming system

Abstract

The present invention provides a PWM signal conversion circuit, method, and LED dimming system, comprising: a PWM signal detection module that outputs a first voltage corresponding to the low-level time of the PWM signal and a second voltage corresponding to the high-level time; an addition module that sums the first and second voltages to obtain a third voltage; a switching signal generation module that generates a switching signal based on the third voltage; a duty cycle ratio generation module that counts the high-level times of the PWM signal based on the switching signal to obtain a duty cycle ratio; and an output voltage generation module that obtains an output voltage related to the duty cycle of the PWM signal based on the duty cycle ratio. The present invention eliminates the need for large capacitors, simplifies chip peripheral circuitry, and extracts the duty cycle of the PWM signal within a single PWM signal cycle, resulting in rapid and efficient calculations. The frequency of the PWM signal duty cycle count is a fixed multiple of the PWM frequency itself, ensuring that the duty cycle count remains constant regardless of changes in the PWM signal frequency, resulting in high accuracy.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a PWM signal conversion circuit, method and LED dimming system. Background Art

[0002] In LED lighting applications, a low-pass filter is usually used to convert the dimming PWM signal into an analog signal. Figure 1 This is a common RC filter circuit in low-pass filters. Using a low-pass filter to filter the PWM signal into an analog signal requires a large-capacity capacitor C to filter the low-frequency PWM signal into an analog signal with relatively small ripple for internal use in the chip, and it cannot be integrated into the chip. For a given PWM signal, The expected analog signal is Duty*Vref.

[0003] In addition, the values of Ton and Toff can be obtained by digital sampling technology to perform digital operations to obtain the corresponding analog signals, but due to Division is required, so digital circuits are difficult to implement simply.

[0004] Therefore, how to propose an easily implementable PWM signal conversion voltage on the basis of reducing the complexity of peripheral circuits and lowering costs has become one of the urgent problems to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a PWM signal conversion circuit, method and LED dimming system to solve the problems of complex peripheral circuits, high cost and difficulty in implementation of the PWM signal conversion circuit in the prior art.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a PWM signal conversion circuit, which at least includes:

[0007] a PWM signal detection module, receiving a PWM signal, detecting a low-level time and a high-level time of the PWM signal, and outputting a first voltage corresponding to the low-level time and a second voltage corresponding to the high-level time;

[0008] an adding module, connected to the output end of the PWM signal detection module, and summing the first voltage and the second voltage to obtain a third voltage;

[0009] a switching signal generating module, connected to the output terminal of the adding module, and generating a switching signal based on the third voltage, wherein the frequency of the switching signal is greater than the frequency of the PWM signal;

[0010] a duty cycle value generating module, connected to the output end of the switching signal generating module, starting to count the switching signal at the rising edge of the PWM signal and ending the counting at the falling edge of the PWM signal, and obtaining the duty cycle value of the PWM signal;

[0011] The output voltage generating module is connected to the output end of the duty cycle value generating module, and obtains an output voltage related to the duty cycle of the PWM signal based on the duty cycle value of the PWM signal.

[0012] Optionally, the PWM signal detection module includes a detection unit, a first counting unit, a first digital-to-analog conversion unit, and a time-to-voltage conversion unit;

[0013] The detection unit receives the PWM signal and detects a falling edge, a rising edge, a low level, and a high level of the PWM signal;

[0014] The first counting unit is connected to the output end of the detection unit, counts the sum of the falling edges and rising edges of the PWM signal based on the sampling clock signal, and outputs the counting result and the overflow bit;

[0015] The first digital-to-analog conversion unit is connected to the output end of the first counting unit and converts the counting result into an analog signal;

[0016] The time-to-voltage conversion unit is connected to the output ends of the detection unit, the first counting unit, and the first digital-to-analog conversion unit, and generates the first voltage and the second voltage based on the analog signal output by the first digital-to-analog conversion unit, the overflow bit, and the detection signal of the PWM signal.

[0017] More optionally, the first counting unit includes an adder and a counter; the adder is connected to the output end of the detection unit, and sums the rising edge trigger signal and the falling edge trigger signal of the PWM signal; the reset end of the counter is connected to the output end of the adder, the clock end receives the sampling clock signal, the first output end outputs the counting result, and the second output end outputs the overflow bit.

[0018] More optionally, the time-to-voltage conversion unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first diode, a second diode, a first capacitor, a second capacitor, a first voltage output subunit, a second voltage output subunit, a first controller, and a second controller;

[0019] One end of the first switch is connected to the output end of the first digital-to-analog conversion unit, the other end is connected to the input end of the first voltage output subunit, and the control end is connected to the rising edge trigger signal of the PWM signal;

[0020] One end of the second switch is connected to the output end of the first digital-to-analog conversion unit, the other end is connected to the anode of the first diode, and the control end is connected to the low-level detection signal of the PWM signal; the cathode of the first diode is connected to the input end of the first voltage output subunit;

[0021] One end of the third switch is connected to the output end of the first digital-to-analog conversion unit, the other end is connected to the input end of the second voltage output subunit, and the control end is connected to the falling edge trigger signal of the PWM signal;

[0022] One end of the fourth switch is connected to the output end of the first digital-to-analog conversion unit, the other end is connected to the anode of the second diode, and the control end is connected to the high-level detection signal of the PWM signal; the cathode of the second diode is connected to the input end of the second voltage output subunit;

[0023] The upper plate of the first capacitor is connected to the input terminal of the first voltage output subunit, and the lower plate is grounded;

[0024] The upper plate of the second capacitor is connected to the input terminal of the second voltage output subunit, and the lower plate is grounded;

[0025] The first controller is connected to the output end of the detection unit and the first counting unit, and generates a control signal for the fifth switch based on a low-level detection signal of the PWM signal and the overflow bit; the fifth switch is connected in parallel to both ends of the first capacitor, and is turned on when the PWM signal is at a low level and the overflow bit is valid;

[0026] The second controller is connected to the output ends of the detection unit and the first counting unit, and generates a control signal for the sixth switch based on the high-level detection signal of the PWM signal and the overflow bit; the sixth switch is connected in parallel to the two ends of the second capacitor, and the sixth switch is turned on when the PWM signal is high and the overflow bit is valid.

[0027] More optionally, the first controller and the second controller are AND logic gates, and the fifth switch and the sixth switch are NMOS transistors.

[0028] More optionally, the third voltage satisfies the following relationship:

[0029]

[0030] Among them, V o1 is the third voltage; V Toff is the first voltage; V Ton is the second voltage; T PWM is the period of the PWM signal; TH_CLK is the period of the sampling clock signal; is the output voltage accuracy of the first digital-to-analog conversion unit.

[0031] Optionally, the switch signal generating module includes a current source, a third capacitor, a comparison unit and a seventh switch;

[0032] One end of the current source is connected to the power supply voltage, and the other end is connected to the upper plate of the third capacitor; the lower plate of the third capacitor is grounded;

[0033] The input end of the comparison unit is connected to the upper plate of the third capacitor and the output end of the adding module respectively, and the output end is connected to the control end of the seventh switch;

[0034] The seventh switch is connected in parallel to both ends of the third capacitor, and is turned on when the voltage of the upper plate of the third capacitor reaches the third voltage.

[0035] More optionally, the frequency of the switching signal satisfies the following relationship:

[0036]

[0037] Among them, F new is the frequency of the switching signal; K1 is the multiple of the frequency of the switching signal higher than the frequency of the PWM signal, which is set to a fixed value; F PWM is the frequency of the PWM signal; I1 is the current flowing through the current source; C3 is the capacitance of the third capacitor; V o1 is the voltage value of the third voltage.

[0038] Optionally, the duty cycle value generating module includes a second counting unit and a latch;

[0039] The clock terminal of the second counting unit is connected to the output terminal of the switch signal generating module, and the reset terminal is connected to the rising edge trigger signal of the PWM signal;

[0040] The input end of the latch is connected to the output end of the second counting unit, the control end is connected to the falling edge trigger signal of the PWM signal, and outputs the duty cycle value of the PWM signal.

[0041] Optionally, the output voltage generating module includes a second digital-to-analog conversion unit and a voltage divider unit; the second digital-to-analog conversion unit receives the duty cycle value of the PWM signal and converts the duty cycle value of the PWM signal into an analog signal; the voltage divider unit is connected to the output end of the second digital-to-analog conversion unit and divides the analog signal output by the second digital-to-analog conversion unit to obtain the output voltage.

[0042] To achieve the above-mentioned and other related objectives, the present invention further provides a PWM signal conversion method, which at least includes:

[0043] Acquire a PWM signal, detect a low-level time of the PWM signal and obtain a corresponding first voltage, detect a high-level time of the PWM signal and obtain a corresponding second voltage;

[0044] summing the first voltage and the second voltage to obtain a third voltage;

[0045] generating a switching signal based on the third voltage, wherein a frequency of the switching signal is higher than a frequency of the PWM signal by a fixed multiple;

[0046] Counting the high level of the PWM signal based on the switching signal and generating a duty cycle value of the PWM signal;

[0047] An output voltage related to the duty cycle of the PWM signal is obtained based on the duty cycle ratio of the PWM signal.

[0048] Optionally, the PWM signal conversion method includes counting the sum of the rising edges and falling edges of the PWM signal and converting the counting result into an analog signal; generating the first voltage and the second voltage based on the analog signal of the counting result and the rising edge trigger signal, falling edge trigger signal, high level detection signal, and low level detection signal of the PWM signal.

[0049] Optionally, the fixed multiple is set to 100 times.

[0050] To achieve the above-mentioned and other related objectives, the present invention further provides an LED dimming system, which comprises at least:

[0051] The PWM signal conversion circuit is used to convert the dimming PWM signal into an analog output voltage;

[0052] The LED driving circuit is connected to the PWM signal conversion circuit and drives the LED light string to realize dimming control based on the output signal of the PWM signal conversion circuit.

[0053] As described above, the PWM signal conversion circuit, method, and LED dimming system of the present invention have the following beneficial effects:

[0054] 1. The PWM signal conversion circuit, method and LED dimming system of the present invention can extract the duty cycle value of a low-frequency PWM signal without using a large capacitor, and can be integrated inside a chip, simplifying the chip peripheral circuit.

[0055] 2. The PWM signal conversion circuit, method, and LED dimming system of the present invention can extract the duty cycle of the PWM signal only through one PWM signal cycle, so that the output signal can immediately follow the changes of the PWM signal, while the commonly used filtering method requires several PWM signal cycles to achieve stability.

[0056] 3. The frequency of the PWM signal conversion circuit, method and LED dimming system of the present invention for counting the duty cycle of the PWM signal is a fixed multiple of the PWM frequency itself. Therefore, no matter how the PWM signal frequency changes, the duty cycle counting is always fixed and accurate.

[0057] 4. In the PWM signal conversion circuit, method and LED dimming system of the present invention, the fixed frequency is set to K1=100, and the count value output by the duty cycle value generating module can be directly used as the reading of the duty cycle of the PWM signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It shows a schematic structural diagram of an RC low-pass filter circuit in the prior art.

[0059] Figure 2 Shown is a structural schematic diagram of the PWM signal conversion circuit of the present invention.

[0060] Figure 3 Shown is a structural schematic diagram of the PWM signal detection module of the present invention.

[0061] Figure 4 Shown is a flow chart of the PWM signal conversion method of the present invention.

[0062] Figure 5 Shown is a structural schematic diagram of the LED dimming system of the present invention.

[0063] Component number description

[0064] 1 PWM signal conversion circuit

[0065] 11 PWM signal detection module

[0066] 111 Detection Unit

[0067] 111a Falling edge trigger

[0068] 111b rising edge flip-flop

[0069] 111c Low Level Detector

[0070] 111d High Level Detector

[0071] 112 First counting unit

[0072] 112a Adder

[0073] 112b counter

[0074] 113 First digital-to-analog conversion unit

[0075] 114 Time-to-voltage conversion unit

[0076] 114a first voltage output subunit

[0077] 114b second voltage output subunit

[0078] 114c First Controller

[0079] 114d Second Controller

[0080] 12 Addition Module

[0081] 13. Switch signal generation module

[0082] 131 Comparison Unit

[0083] 14 Duty cycle value generation module

[0084] 141 Second counting unit

[0085] 142 latch

[0086] 15. Output voltage generation module

[0087] 151 Second digital-to-analog conversion unit

[0088] 152 voltage divider unit

[0089] 2 LED driver circuit

[0090] Steps S1 to S5 DETAILED DESCRIPTION

[0091] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0092] See also Figures 2 to 5It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0093] Example 1

[0094] like Figure 2 As shown, this embodiment provides a PWM signal conversion circuit, the PWM signal conversion circuit comprising:

[0095] PWM signal detection module 11 , addition module 12 , switch signal generation module 13 , duty cycle value generation module 14 and output voltage generation module 15 .

[0096] like Figure 2 As shown, the PWM signal detection module 11 receives the PWM signal, detects the low level time and high level time of the PWM signal, and outputs a first voltage V corresponding to the low level time. Toff and a second voltage V corresponding to the high level time Ton .

[0097] Specifically, in this embodiment, the PWM signal is input into the PWM signal detection module 11 through the dimming port DIM to implement dimming control. In actual use, any occasion that requires converting a PWM signal into an analog signal is applicable to the present invention, which will not be described in detail here.

[0098] Specifically, if Figure 3 As shown, in this embodiment, the PWM signal detection module 11 includes a detection unit 111, a first counting unit 112, a first digital-to-analog conversion unit 113 and a time-to-voltage conversion unit 114. In actual use, any first voltage V corresponding to the low level time of the PWM signal can be obtained. Toff and a second voltage V corresponding to the high level time of the PWM signal Ton The circuit structures of FIG. 1 and FIG. 2 are all applicable to the present invention and are not limited to this embodiment.

[0099] More specifically, the detection unit 111 receives the PWM signal and detects the falling edge, rising edge, low level, and high level of the PWM signal. For example, the detection unit 111 includes a falling edge trigger 111a, a rising edge trigger 111b, a low level detector 111c, and a high level detector 111d. The falling edge trigger 111a, the rising edge trigger 111b, the low level detector 111c, and the high level detector 111d each receive the PWM signal and perform corresponding detections.

[0100] More specifically, the first counting unit 112 is connected to the output of the detection unit 111 and counts the total number of falling and rising edges of the PWM signal based on a sampling clock signal High CLK, outputting a count result and an overflow bit. The sampling clock signal High CLK has a frequency greater than the frequency of the PWM signal. As an example, the first counting unit 112 includes an adder 112a and a counter 112b. The adder 112a is connected to the output of the detection unit 111 and sums the rising and falling edge trigger signals of the PWM signal. The counter 112b has a reset terminal Reset connected to the output of the adder 112a, a clock terminal CLK receiving the sampling clock signal High CLK, a first output terminal OUT outputting the count result, and a second output terminal OV outputting the overflow bit. It should be noted that both rising and falling edges of the PWM signal trigger counting. If both rising and falling edges can trigger the counter to count, an adder is not required, and this embodiment is not limited thereto.

[0101] More specifically, the first digital-to-analog conversion unit 113 is connected to the output terminal of the first counting unit 112 to convert the counting result into an analog signal. Any circuit structure capable of implementing digital-to-analog conversion is applicable to the present invention and will not be described in detail here.

[0102] More specifically, the time-to-voltage conversion unit 114 is connected to the output terminals of the detection unit 111, the first counting unit 112, and the first digital-to-analog conversion unit 113, and generates the first voltage V based on the analog signal output by the first digital-to-analog conversion unit 113, the overflow bit, and the detection signal of the PWM signal. Toff and the second voltage V TonAs an example, the time-to-voltage conversion unit 114 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch Q1, a sixth switch Q2, a first diode D1, a second diode D2, a first capacitor C1, a second capacitor C2, a first voltage output subunit 114a, a second voltage output subunit 114b, a first controller 114c, and a second controller 114d. One end of the first switch S1 is connected to the output end of the first digital-to-analog conversion unit 113, the other end is connected to the input end of the first voltage output subunit 114a, and the control end is connected to the rising edge trigger signal of the PWM signal; one end of the second switch S2 is connected to the output end of the first digital-to-analog conversion unit 113, the other end is connected to the anode of the first diode D1, and the control end is connected to the low level detection signal of the PWM signal; the cathode of the first diode D1 is connected to the input end of the first voltage output subunit 114a; one end of the third switch S3 is connected to the output end of the first digital-to-analog conversion unit 113, the other end is connected to the input end of the second voltage output subunit 114b, and the control end is connected to the falling edge trigger signal of the PWM signal; one end of the fourth switch S4 is connected to the output end of the first digital-to-analog conversion unit 113, the other end is connected to the anode of the second diode D2, and the control end is connected to the high level detection signal of the PWM signal; the cathode of the second diode D2 is connected to the input end of the second voltage output subunit 1 14b; the upper plate of the first capacitor C1 is connected to the input end of the first voltage output subunit 114a, and the lower plate is grounded; the upper plate of the second capacitor C2 is connected to the input end of the second voltage output subunit 114b, and the lower plate is grounded; the first controller 114c is connected to the output ends of the detection unit 111 and the first counting unit 112, and generates a control signal for the fifth switch Q1 based on the low-level detection signal of the PWM signal and the overflow bit; the fifth switch Q1 is connected in parallel across the first capacitor C1, and is turned on when the PWM signal is at a low level and the overflow bit is valid; the second controller 114d is connected to the output ends of the detection unit 111 and the first counting unit 112, and generates a control signal for the sixth switch Q2 based on the high-level detection signal of the PWM signal and the overflow bit; the sixth switch Q2 is connected in parallel across the second capacitor C2, and is turned on when the PWM signal is at a high level and the overflow bit is valid.Furthermore, in this example, the first controller 114c and the second controller 114d are AND logic gates, and the fifth switch Q1 and the sixth switch Q2 are NMOS transistors. When the first controller 114c outputs a high level, the fifth switch Q1 is turned on, and when the second controller 114d outputs a high level, the sixth switch Q2 is turned on. In actual applications, corresponding devices can be selected according to actual needs as long as they can meet the above logical relationship.

[0103] It should be noted that the types of the first, second, third, fourth, fifth and sixth switches can be set as needed, and the first, second, third and fourth switches can also be implemented using NMOS, which will not be described in detail here.

[0104] like Figure 2 As shown, the adding module 12 is connected to the output end of the PWM signal detecting module 11, and the first voltage V Toff and the second voltage V Ton The sum is calculated to obtain a third voltage Vo1.

[0105] Specifically, in this embodiment, the third voltage Vo1 satisfies the following relationship:

[0106]

[0107] Among them, V o1 is the third voltage; V Toff is the first voltage; V Ton is the second voltage; T PWM is the period of the PWM signal; T H_CLK is the period of the sampling clock signal High CLK; is the output voltage accuracy of the first digital-to-analog conversion unit 113 ; Vref is the highest output reference voltage of the first digital-to-analog conversion unit 113 ; and DAC is the number of bits of the first digital-to-analog conversion unit 113 .

[0108] like Figure 2 As shown, the switching signal generating module 13 is connected to the output end of the adding module 12 and generates a switching signal based on the third voltage Vo1 , wherein the frequency of the switching signal is greater than the frequency of the PWM signal.

[0109] Specifically, if Figure 2As shown, in this embodiment, the switch signal generating module 13 includes a current source I1, a third capacitor C3, a comparison unit 131, and a seventh switch Q3. One end of the current source I1 is connected to the power supply voltage VDD, and the other end is connected to the upper plate of the third capacitor C3. The lower plate of the third capacitor C3 is grounded. The input end of the comparison unit 131 is respectively connected to the upper plate of the third capacitor C3 and the output end of the adding module 12, and the output end is connected to the control end of the seventh switch Q3. The seventh switch Q3 is connected in parallel with both ends of the third capacitor C3 and is turned on when the voltage on the upper plate of the third capacitor C3 reaches the third voltage Vo1. As an example, the non-inverting input terminal of the comparison unit 131 is connected to the upper plate of the third capacitor C3, and the inverting input terminal is connected to the third voltage Vo1; the seventh switch Q3 is implemented using an NMOS; in actual use, the relationship between the polarity of the input terminal of the comparison unit 131 and the corresponding input signal can be interchangeable, and the type of the seventh switch Q3 can be selected according to actual logic requirements and is not limited to this embodiment.

[0110] Specifically, the current source I1 charges the third capacitor C3 to satisfy I1*t new = C3 * Vo1, when the third capacitor C3 is charged to the third voltage Vo1, the comparison unit 131 outputs a high level to turn on the seventh switch Q3, discharging the third capacitor C3 and thus starting a new cycle. Wherein, the cycle of the switching signal satisfies: Among them, t new is the period of the switching signal, C3 is the capacitance of the third capacitor, I1 is the current flowing through the current source; but or That is, the frequency of the switching signal is K1 times higher than the frequency of the PWM signal (where I1, C3, Vref, T H_CLK and 2 DAC Parameters such as φ are fixed internally, so K1 is also a fixed value).

[0111] like Figure 2 As shown, the duty cycle value generating module 14 is connected to the output end of the switching signal generating module 13, starts counting the switching signal at the rising edge of the PWM signal, ends counting at the falling edge of the PWM signal, and obtains the duty cycle value Duty out of the PWM signal.

[0112] Specifically, if Figure 2As shown, in this embodiment, the duty cycle value generating module 14 includes a second counting unit 141 and a latch 142. The clock terminal CLK of the second counting unit 141 is connected to the output terminal of the switching signal generating module 13, and the reset terminal Reset is connected to the rising edge trigger signal rising edge of the PWM signal; the input terminal of the latch 142 is connected to the output terminal of the second counting unit 141, and the control terminal is connected to the falling edge trigger signal falling edge of the PWM signal, and outputs the duty cycle value Duty out of the PWM signal. The duty cycle of the PWM signal satisfies K1 is a multiple of the frequency of the switching signal being higher than the frequency of the PWM signal; and K2 is a result of the switching signal counting the high levels of the PWM signal.

[0113] Specifically, if appropriate parameters (I1, C3, Vref, T H_CLK and 2 DAC , etc.), so that K1=100, then the count number K2 of the second counting unit 141 and the signal Duty out outputted by the latch 142 can be directly used as the reading of the duty cycle.

[0114] like Figure 2 As shown, the output voltage generating module 15 is connected to the output end of the duty cycle value generating module 14 , and obtains the output voltage Out related to the duty cycle of the PWM signal based on the duty cycle value Duty out of the PWM signal.

[0115] Specifically, if Figure 2 As shown, in this embodiment, the output voltage generating module 15 includes a second digital-to-analog conversion unit 151 and a voltage divider unit 152. The second digital-to-analog conversion unit 151 receives the duty cycle value Dutyout of the PWM signal and converts the duty cycle value Dutyout of the PWM signal into an analog signal. The voltage divider unit 152 is connected to the output end of the second digital-to-analog conversion unit 151 and divides the analog signal output by the second digital-to-analog conversion unit 151 to obtain the output voltage Out. It should be noted that the voltage divider unit 152 is used to adjust the proportional relationship between the output voltage and the PWM signal. In actual applications, the voltage divider unit 152 can be omitted, and is not limited to this embodiment.

[0116] Specifically, when the count value of the second counting unit 141 is K1, the voltage value outputted by the second digital-to-analog conversion unit 151 is recorded as the preset value Ref; the output voltage Out is obtained by voltage division. If the setting (For ease of calculation, in this case, K1 = 100, R1 = 0, and the maximum output reference voltage of the first digital-to-analog conversion unit 113 and the second digital-to-analog conversion unit 151 are equal.) Thus, the output voltage Out = Ref * Duty, thereby stably outputting a reference voltage value related to the PWM signal duty cycle. Similarly, when K1 > 100, 100 / K1 = R2 / (R1 + R2), which also yields a reference voltage value related to the PWM signal duty cycle. Details are not detailed here.

[0117] Example 2

[0118] like Figure 4 As shown, this embodiment provides a PWM signal conversion method. As an example, the PWM signal conversion method is implemented using the PWM signal conversion circuit of Example 1. In actual use, any hardware circuit or software code that can implement this method is applicable. The PWM signal conversion method includes:

[0119] S1: Obtain a PWM signal, detect the low level time of the PWM signal and obtain the corresponding first voltage V Toff , detect the high level time of the PWM signal and obtain the corresponding second voltage V Ton .

[0120] Specifically, first, the sum of the rising edges and falling edges of the PWM signal is counted based on the sampling clock signal High CLK (internal high-frequency clock), and the counting result is converted into an analog signal. Then, the first voltage and the second voltage are generated based on the analog signal of the counting result and the rising edge trigger signal, falling edge trigger signal, high level detection signal, and low level detection signal of the PWM signal; Figure 3 As shown, the PWM signal jumps to a low level, the falling edge trigger signal and the low level detection signal are valid, and the rising edge trigger signal and the high level detection signal are invalid. At this time, the second switch S2, the third switch S3 and the fifth switch Q1 are closed, the first switch S1, the fourth switch S4 and the sixth switch Q2 are opened, and the output signal of the first digital-to-analog conversion unit 113 charges the second capacitor C2 and obtains the first voltage V Toff The PWM signal jumps to a high level, the falling edge trigger signal and the low level detection signal are invalid, and the rising edge trigger signal and the high level detection signal are valid. At this time, the second switch S2, the third switch S3 and the fifth switch Q1 are disconnected, the first switch S1, the fourth switch S4 and the sixth switch Q2 are closed, and the output signal of the first digital-to-analog conversion unit 113 charges the first capacitor C1 and obtains the second voltage V Ton The first voltage V ToffThe voltage value can reflect the low level time of the PWM signal, and the second voltage V Ton The voltage value can reflect the high level time of the PWM signal.

[0121] It should be noted that any method capable of detecting the low-level time and the high-level time of the PWM signal is suitable for the present invention, and is not limited to this embodiment.

[0122] S2: The first voltage V Toff With the second voltage V Ton The sum is calculated to obtain a third voltage Vo1.

[0123] S3 : Generate a switching signal based on the third voltage Vo1 , wherein the frequency of the switching signal is higher than the frequency of the PWM signal by a fixed multiple K1 .

[0124] Specifically, if Figure 2 As shown, the current source I1 charges the third capacitor C3. At this time, the comparison unit 131 outputs a low level, and the seventh switch Q3 is turned off. As the charging progresses, the voltage on the third capacitor C3 increases. When the voltage on the third capacitor C3 reaches the third voltage Vo1, the comparison unit 131 jumps to a high level, the seventh switch Q3 is turned on, and the third capacitor C3 starts to discharge. When the voltage on the third capacitor C3 is lower than the third voltage Vo1, the comparison unit 131 jumps to a high level again, and the switching signal is obtained in this cycle.

[0125] Specifically, in this embodiment, Among them, I1, C3, Vref, T H_CLK and 2 DAC Parameters such as K1 are fixed internally, so K1 is also a fixed value and can be set according to actual needs.

[0126] It should be noted that any method capable of obtaining a frequency that is a fixed multiple higher than the PWM signal frequency based on the third voltage Vo1 is applicable to the present invention, and will not be described in detail here.

[0127] S4: Counting the high level of the PWM signal based on the switching signal, and generating a duty ratio value Duty out of the PWM signal.

[0128] Specifically, if Figure 2 As shown, the switching signal is counted at the rising edge of the PWM signal and the counting is ended at the falling edge of the PWM signal, thereby obtaining the count value K2 of the high level of the switching signal to the PWM signal. The total counting length is K1, and the duty cycle of the PWM signal is As an example, if K1 is set to 100, the duty cycle value Duty out of the PWM signal can be directly used as the duty cycle reading.

[0129] S5: Obtaining an output voltage Out related to the duty cycle of the PWM signal based on the duty cycle value Duty out of the PWM signal.

[0130] Specifically, the duty cycle value Duty out of the PWM signal is converted from digital to analog to obtain a voltage related to the duty cycle of the PWM signal; the voltage after analog to digital conversion can be further adjusted by voltage division to obtain a desired output voltage, satisfying Out=Ref*Duty.

[0131] Example 3

[0132] like Figure 5 As shown, this embodiment provides an LED dimming system, the LED dimming system comprising:

[0133] PWM signal conversion circuit 1 and LED driving circuit 2.

[0134] like Figure 5 As shown, the PWM signal conversion circuit 1 converts the dimming PWM signal into an analog output voltage.

[0135] Specifically, the PWM signal is input to the PWM signal conversion circuit 1 through the dimming port DIM, and an output voltage related to the duty cycle of the PWM signal is obtained. The output voltage is provided to the LED driving circuit 2 as a reference signal.

[0136] It should be noted that the structure and working principle of the PWM signal conversion circuit 1 are described in the first embodiment and will not be elaborated here.

[0137] like Figure 5 As shown, the LED driving circuit 2 is connected to the PWM signal conversion circuit, and drives the LED light string based on the output signal of the PWM signal conversion circuit 1 to achieve dimming control.

[0138] Specifically, the LED driving circuit 2 uses the output signal of the PWM signal conversion circuit 1 as a reference signal to adjust the driving signal DIV, thereby achieving dimming control of the LED light string.

[0139] It should be noted that any circuit structure that can implement dimming control based on the output voltage related to the duty cycle of the PWM signal is applicable to the LED driving circuit 2 of the present invention, and the specific structures are not described in detail here.

[0140] The present invention samples and converts the high and low level times of an externally input PWM dimming signal to generate a higher-frequency fixed-rate switching signal to count the PWM signal, thereby obtaining a PWM duty cycle signal and outputting a related reference voltage. The frequency of the PWM signal duty cycle counting is a fixed multiple of the PWM frequency itself, so no matter how the PWM signal frequency changes, the duty cycle count remains fixed. The conversion of the input low-frequency PWM dimming signal to analog dimming does not require the use of large capacitors, the output signal can respond instantly to the input PWM signal, and can be integrated inside the chip to simplify peripheral circuits.

[0141] In summary, the present invention provides a PWM signal conversion circuit, method and LED dimming system, comprising: a PWM signal detection module, which receives a PWM signal, detects a low-level time and a high-level time of the PWM signal, and outputs a first voltage corresponding to the low-level time and a second voltage corresponding to the high-level time; an addition module, which is connected to the output end of the PWM signal detection module, and sums the first voltage and the second voltage to obtain a third voltage; a switching signal generation module, which is connected to the output end of the addition module, and generates a switching signal based on the third voltage, wherein the frequency of the switching signal is greater than the frequency of the PWM signal; a duty cycle value generation module, which is connected to the output end of the switching signal generation module, and starts counting the switching signal at the rising edge of the PWM signal and ends counting at the falling edge of the PWM signal to obtain a duty cycle value of the PWM signal; and an output voltage generation module, which is connected to the output end of the duty cycle value generation module, and obtains an output voltage related to the duty cycle of the PWM signal based on the duty cycle value of the PWM signal. The PWM signal conversion circuit, method, and LED dimming system of the present invention can extract the duty cycle of a low-frequency PWM signal without the use of large capacitors. These circuits can be integrated within a chip, simplifying the chip's peripheral circuitry. Extracting the duty cycle of a PWM signal only requires one PWM signal cycle, allowing the output signal to instantly follow changes in the PWM signal, resulting in rapid and efficient calculations. The frequency at which the PWM signal's duty cycle is counted is a fixed multiple of the PWM frequency itself, ensuring that the duty cycle remains constant regardless of changes in the PWM signal frequency, resulting in high accuracy. Therefore, the present invention effectively overcomes various shortcomings of the prior art and possesses high industrial value.

[0142] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A PWM signal conversion circuit, characterized in that: The PWM signal conversion circuit at least includes: a PWM signal detection module, receiving a PWM signal, detecting a low-level time and a high-level time of the PWM signal, and outputting a first voltage corresponding to the low-level time and a second voltage corresponding to the high-level time; an adding module, connected to the output end of the PWM signal detection module, and summing the first voltage and the second voltage to obtain a third voltage; a switching signal generating module, connected to the output terminal of the adding module, and generating a switching signal based on the third voltage, wherein the frequency of the switching signal is greater than the frequency of the PWM signal; A duty cycle value generating module is connected to the output end of the switch signal generating module, starts counting the switch signal at the rising edge of the PWM signal, ends counting at the falling edge of the PWM signal, and obtains the duty cycle value of the PWM signal; the duty cycle of the PWM signal satisfies , wherein K1 is a multiple of the frequency of the switching signal being higher than the frequency of the PWM signal, and K2 is a result of the switching signal counting the high level of the PWM signal; The output voltage generating module is connected to the output end of the duty cycle value generating module, and obtains an output voltage related to the duty cycle of the PWM signal based on the duty cycle value of the PWM signal.

2. The PWM signal conversion circuit according to claim 1, wherein: The PWM signal detection module includes a detection unit, a first counting unit, a first digital-to-analog conversion unit and a time-to-voltage conversion unit; The detection unit receives the PWM signal and detects a falling edge, a rising edge, a low level, and a high level of the PWM signal; The first counting unit is connected to the output end of the detection unit, counts the sum of the falling edges and rising edges of the PWM signal based on the sampling clock signal, and outputs the counting result and the overflow bit; The first digital-to-analog conversion unit is connected to the output end of the first counting unit and converts the counting result into an analog signal; The time-to-voltage conversion unit is connected to the output end of the detection unit, the first counting unit and the first digital-to-analog conversion unit, and generates the first voltage and the second voltage based on the output signal of the first digital-to-analog conversion unit, the overflow bit and the detection signal of the PWM signal.

3. The PWM signal conversion circuit according to claim 2, wherein: The first counting unit includes an adder and a counter; the adder is connected to the output end of the detection unit and sums the rising edge trigger signal and the falling edge trigger signal of the PWM signal; the reset end of the counter is connected to the output end of the adder, the clock end receives the sampling clock signal, the first output end outputs the counting result, and the second output end outputs the overflow bit.

4. The PWM signal conversion circuit according to claim 2, wherein: The time-to-voltage conversion unit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first diode, a second diode, a first capacitor, a second capacitor, a first voltage output subunit, a second voltage output subunit, a first controller, and a second controller; One end of the first switch is connected to the output end of the first digital-to-analog conversion unit, the other end is connected to the input end of the first voltage output subunit, and the control end is connected to the rising edge trigger signal of the PWM signal; One end of the second switch is connected to the output end of the first digital-to-analog conversion unit, the other end is connected to the anode of the first diode, and the control end is connected to the low-level detection signal of the PWM signal; the cathode of the first diode is connected to the input end of the first voltage output subunit; One end of the third switch is connected to the output end of the first digital-to-analog conversion unit, the other end is connected to the input end of the second voltage output subunit, and the control end is connected to the falling edge trigger signal of the PWM signal; One end of the fourth switch is connected to the output end of the first digital-to-analog conversion unit, the other end is connected to the anode of the second diode, and the control end is connected to the high-level detection signal of the PWM signal; the cathode of the second diode is connected to the input end of the second voltage output subunit; The upper plate of the first capacitor is connected to the input terminal of the first voltage output subunit, and the lower plate is grounded; The upper plate of the second capacitor is connected to the input terminal of the second voltage output subunit, and the lower plate is grounded; The first controller is connected to the output end of the detection unit and the first counting unit, and generates a control signal for the fifth switch based on a low-level detection signal of the PWM signal and the overflow bit; the fifth switch is connected in parallel to both ends of the first capacitor, and is turned on when the PWM signal is at a low level and the overflow bit is valid; The second controller is connected to the output ends of the detection unit and the first counting unit, and generates a control signal for the sixth switch based on the high-level detection signal of the PWM signal and the overflow bit; the sixth switch is connected in parallel to the two ends of the second capacitor, and the sixth switch is turned on when the PWM signal is high and the overflow bit is valid.

5. The PWM signal conversion circuit according to claim 4, wherein: The first controller and the second controller are AND logic gates, and the fifth switch and the sixth switch are NMOS transistors.

6. The PWM signal conversion circuit according to any one of claims 2 to 5, wherein: The third voltage satisfies the following relationship: ； in, is the third voltage; is the first voltage; is the second voltage; is the period of the PWM signal; is the period of the sampling clock signal; is the output voltage accuracy of the first digital-to-analog conversion unit, Vref is the highest output reference voltage of the first digital-to-analog conversion unit, and DAC is the number of bits of the first digital-to-analog conversion unit.

7. The PWM signal conversion circuit according to claim 1, wherein: The switch signal generating module includes a current source, a third capacitor, a comparison unit and a seventh switch; One end of the current source is connected to the power supply voltage, and the other end is connected to the upper plate of the third capacitor; the lower plate of the third capacitor is grounded; The input end of the comparison unit is connected to the upper plate of the third capacitor and the output end of the adding module respectively, and the output end is connected to the control end of the seventh switch; The seventh switch is connected in parallel to both ends of the third capacitor, and is turned on when the voltage of the upper plate of the third capacitor reaches the third voltage.

8. The PWM signal conversion circuit according to claim 7, wherein: The frequency of the switching signal satisfies the following relationship: ； in, is the frequency of the switching signal; K1 is the multiple of the frequency of the switching signal higher than the frequency of the PWM signal, which is set to a fixed value; is the frequency of the PWM signal; I1 is the current flowing through the current source; C3 is the capacitance of the third capacitor; is the voltage value of the third voltage.

9. The PWM signal conversion circuit according to claim 1, wherein: The duty cycle value generating module includes a second counting unit and a latch; The clock terminal of the second counting unit is connected to the output terminal of the switch signal generating module, and the reset terminal is connected to the rising edge trigger signal of the PWM signal; The input end of the latch is connected to the output end of the second counting unit, the control end is connected to the falling edge trigger signal of the PWM signal, and outputs the duty cycle value of the PWM signal.

10. The PWM signal conversion circuit according to claim 1, wherein: The output voltage generating module includes a second digital-to-analog conversion unit and a voltage divider unit; the second digital-to-analog conversion unit receives the duty cycle value of the PWM signal and converts the duty cycle value of the PWM signal into an analog signal; the voltage divider unit is connected to the output end of the second digital-to-analog conversion unit and divides the output signal of the second digital-to-analog conversion unit to obtain the output voltage.

11. A PWM signal conversion method, characterized in that: The PWM signal conversion method at least includes: Acquire a PWM signal, detect a low-level time of the PWM signal and obtain a corresponding first voltage, detect a high-level time of the PWM signal and obtain a corresponding second voltage; summing the first voltage and the second voltage to obtain a third voltage; generating a switching signal based on the third voltage, wherein a frequency of the switching signal is higher than a frequency of the PWM signal by a fixed multiple; The high level of the PWM signal is counted based on the switching signal, and the duty cycle value of the PWM signal is generated; the duty cycle of the PWM signal satisfies , wherein K1 is a multiple of the frequency of the switching signal being higher than the frequency of the PWM signal, and K2 is a result of the switching signal counting the high level of the PWM signal; An output voltage related to the duty cycle of the PWM signal is obtained based on the duty cycle ratio of the PWM signal.

12. The PWM signal conversion method according to claim 11, wherein: The PWM signal conversion method includes counting the sum of the rising edges and falling edges of the PWM signal and converting the counting result into an analog signal; generating the first voltage and the second voltage based on the analog signal of the counting result and the rising edge trigger signal, falling edge trigger signal, high level detection signal, and low level detection signal of the PWM signal.

13. An LED dimming system, characterized in that: The LED dimming system at least includes: The PWM signal conversion circuit according to any one of claims 1 to 10, configured to convert a dimming PWM signal into an analog output voltage; The LED driving circuit is connected to the PWM signal conversion circuit and drives the LED light string to realize dimming control based on the output signal of the PWM signal conversion circuit.

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