Method of manufacturing a semiconductor structure

Abstract

This disclosure provides a method for fabricating a semiconductor structure, belonging to the field of semiconductor technology. The method includes: providing a semiconductor substrate having an active region; the active region comprising a first active region and a second active region isolated from each other; forming a bit line contact trench on the semiconductor substrate, the bit line contact trench exposing the first active region; forming an etch stop layer covering the sidewalls of the bit line contact trench; the etch stop layer exposing a portion of the first active region at the bottom of the bit line contact trench; using the etch stop layer as a mask, etching the semiconductor substrate to form a pit at the bottom of the bit line contact trench; the pit being at least partially located in the first active region; removing the etch stop layer; forming a bit line structure, the bit line leads of the bit line structure filling the pit; and forming a conductive plug electrically connected to the second active region. This method for fabricating a semiconductor structure can improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for fabricating a semiconductor structure. Background Technology

[0002] The development of dynamic random access memory (DRAM) aims for high speed, high integration density, and low power consumption. However, with the miniaturization of semiconductor device structures, especially for DRAM with a critical dimension of less than 17nm, the drive current (the current between the recessed transistor and the bit line structure) is relatively small, which directly limits the electrical performance and storage efficiency of DRAM.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a method for fabricating a semiconductor structure to improve the performance of the semiconductor structure.

[0005] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0006] A semiconductor substrate is provided, the semiconductor substrate having an active region; the active region includes a first active region and a second active region that are isolated from each other;

[0007] A bit line contact groove is formed on the semiconductor substrate, the bit line contact groove exposing the first active region;

[0008] An etching barrier layer is formed to cover the sidewalls of the bit line contact groove; the etching barrier layer exposes a portion of the first active region at the bottom of the bit line contact groove.

[0009] Using the etching barrier layer as a mask, the semiconductor substrate is etched to form a pit at the bottom of the bit line contact trench; the pit is at least partially located in the first active region;

[0010] Remove the etching barrier layer;

[0011] A bitline structure is formed, wherein the bitline leads of the bitline structure fill the recess;

[0012] A conductive plug is formed, and the conductive plug is electrically connected to the second active region.

[0013] According to one embodiment of the present disclosure, forming a bit line contact groove on the semiconductor substrate includes:

[0014] A first mask layer is formed on the semiconductor substrate; the first mask layer covers the second active region and exposes the first active region;

[0015] The semiconductor substrate is patterned using the first mask layer as a mask to form bit line contact grooves that expose the first active region.

[0016] According to one embodiment of this disclosure, forming an etching barrier layer covering the sidewall of the bit line contact groove includes:

[0017] An etching barrier material layer is formed covering the surface of the first mask layer, the sidewalls of the bit line contact groove, and the bottom of the bit line contact groove; the etching barrier material layer at least partially overlaps with the first active region at the bottom of the bit line contact groove.

[0018] The etching barrier material layer is patterned to remove the portion of the etching barrier material layer located at the bottom of the bit line contact groove, thereby forming an etching barrier layer covering the sidewall of the bit line contact groove.

[0019] According to one embodiment of this disclosure, the material of the etching barrier layer is titanium nitride.

[0020] According to one embodiment of this disclosure, the etching barrier material layer is formed by atomic layer deposition.

[0021] According to one embodiment of this disclosure, the etching barrier material layer is patterned by dry etching.

[0022] According to one embodiment of this disclosure, etching the first active region using the etch barrier layer as a mask includes:

[0023] The exposed semiconductor substrate is etched using a first etching condition; under the first etching condition, the etching rate of the first active region is more than 10 times the etching rate of the etch barrier layer.

[0024] According to one embodiment of this disclosure, the first etching condition is to etch the first active region using a gas containing hydrogen bromide.

[0025] According to one embodiment of this disclosure, the semiconductor substrate is filled with a word line structure; the dimension of the bit line lead along the extension direction of the word line structure is a first dimension; and the depth of the pit is a second dimension.

[0026] The second dimension is 0.5 to 2 times the first dimension.

[0027] According to one embodiment of this disclosure, removing the etch barrier layer includes:

[0028] The etching barrier layer is etched under the second etching conditions; under the second etching conditions, the etching rate of the etching barrier layer is more than 30 times that of the etching rate of the first active region.

[0029] According to one embodiment of this disclosure, the second etching condition is to etch the etching barrier layer using an acidic etching solution containing an oxidant.

[0030] According to one embodiment of the present disclosure, when a bit line contact groove is formed on the semiconductor substrate, the surface area of ​​the first active region exposed by the bit line contact groove is a first area.

[0031] After the etch barrier layer is removed, the surface area of ​​the first active region exposed by the bit line contact groove and the pit is the second area;

[0032] The second area is 2 to 4 times the first area.

[0033] According to one embodiment of this disclosure, forming a bitline structure includes:

[0034] A polycrystalline silicon filling material layer is formed, which fills the bit line contact groove and the pit;

[0035] A bit-line conductive material layer and a bit-line insulating top cover material layer are sequentially formed to cover the polycrystalline silicon filling material layer;

[0036] The polysilicon filling material layer, the bit line conductive material layer, and the bit line insulating cap material layer are patterned to form bit line leads; the bit line leads fill the pits.

[0037] An insulating filler layer is formed to fill the bit line contact groove and a bit line insulating layer is formed to cover the bit line lead.

[0038] According to one embodiment of this disclosure, forming a conductive plug includes:

[0039] Forming an embolization hole that exposes the second active region;

[0040] The plug hole is filled with polycrystalline silicon to form the conductive plug.

[0041] According to one embodiment of this disclosure, the method for fabricating the semiconductor structure further includes:

[0042] A transfer electrode layer is formed on the side of the conductive plug away from the semiconductor substrate, the transfer electrode layer including a plurality of transfer electrodes electrically connected to each conductive plug.

[0043] A device layer is formed on the side of the transition electrode layer away from the semiconductor substrate, and the device layer includes a plurality of functional devices electrically connected to each of the transition electrodes in a one-to-one correspondence.

[0044] According to the semiconductor structure fabrication method provided in this disclosure, after forming the bit line contact trench, a pit is also formed at the bottom of the bit line contact trench. When forming the bit line lead, the bit line lead can fill the pit to increase the contact area between the bit line lead and the first active region, improve the charge transfer speed between the bit line lead and the first active region, avoid the limitation of charge transfer speed on the semiconductor structure, and improve the performance of the semiconductor device.

[0045] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0047] Figure 1 This is a top view schematic diagram of an isolation shallow trench on a semiconductor substrate in one embodiment of the present disclosure.

[0048] Figure 2 This is a top view schematic diagram of a shallow trench isolation structure and a word line structure on a semiconductor substrate in one embodiment of the present disclosure.

[0049] Figure 3 for Figure 1 A cross-sectional view of the structure at location PQ.

[0050] Figure 4 for Figure 2 A cross-sectional view of the structure at location PQ.

[0051] Figure 5 This is a schematic diagram of a structure in which a first mask material layer is formed on a semiconductor substrate in one embodiment of the present disclosure.

[0052] Figure 6 This is a top view schematic diagram showing the position of the first mask layer on the semiconductor substrate in one embodiment of the present disclosure.

[0053] Figure 7 This is a schematic diagram of a structure in which a first mask layer is formed on a semiconductor substrate in one embodiment of the present disclosure.

[0054] Figure 8This is a schematic diagram of a structure forming a bit line contact groove in one embodiment of the present disclosure.

[0055] Figure 9 This is a schematic diagram of the structure in one embodiment of the present disclosure, showing the formation of an etching barrier material layer.

[0056] Figure 10 This is a schematic diagram of the structure in one embodiment of the present disclosure, showing the formation of an etching barrier layer.

[0057] Figure 11 This is a schematic diagram of the structure forming the pit in one embodiment of the present disclosure.

[0058] Figure 12 This is a schematic diagram of the structure for removing the etching barrier layer in one embodiment of the present disclosure.

[0059] Figure 13 This is a schematic diagram of the structure in one embodiment of the present disclosure, showing the formation of a polycrystalline silicon filling material layer.

[0060] Figure 14 This is a schematic diagram of the structure of the polycrystalline silicon filling material layer being etched back in one embodiment of the present disclosure.

[0061] Figure 15 This is a schematic diagram of the structure for removing the first mask layer in one embodiment of the present disclosure.

[0062] Figure 16 This is a schematic diagram of the structure of forming a bit line conductive material layer and a bit line insulating top cover material layer in one embodiment of the present disclosure.

[0063] Figure 17 This is a schematic diagram of the structure forming a bit line insulating top cover layer and a bit line second conductive layer in one embodiment of the present disclosure.

[0064] Figure 18 This is a schematic diagram of the structure in one embodiment of the present disclosure, showing the formation of a first conductive layer for bit lines and a polysilicon filling layer.

[0065] Figure 19 This is a schematic diagram of the structure forming an insulating filler material layer in one embodiment of the present disclosure.

[0066] Figure 20 This is a schematic diagram of the structure forming an insulating filler layer in one embodiment of the present disclosure.

[0067] Figure 21 This is a schematic diagram of the structure in one embodiment of the present disclosure, showing the formation of the first insulating material layer of the bit line.

[0068] Figure 22 This is a schematic diagram of the structure forming the first insulating layer of the bit line in one embodiment of the present disclosure.

[0069] Figure 23 This is a schematic diagram of the structure forming the second insulating layer of the bit line in one embodiment of the present disclosure.

[0070] Figure 24 This is a schematic diagram of the structure forming the plug hole in one embodiment of the present disclosure.

[0071] Figure 25 This is a schematic diagram of the structure forming a conductive plug in one embodiment of the present disclosure.

[0072] Figure 26 This is a schematic diagram of the structure in one embodiment of the present disclosure, showing the formation of an electrode material layer.

[0073] Figure 27 This is a schematic diagram of the structure forming the transfer electrode in one embodiment of the present disclosure.

[0074] Figure 28 This is a schematic diagram of the structure forming an isolation material layer in one embodiment of the present disclosure.

[0075] Figure 29 This is a schematic flowchart of a method for fabricating a semiconductor structure in one embodiment of the present disclosure.

[0076] in, Figures 7 to 28 The cutting position is Figure 6 The position indicated by the PQ section line.

[0077] Explanation of reference numerals in the attached figures:

[0078] BP, Semiconductor substrate; STI, Shallow isolation trench; STI0, Shallow trench isolation structure; Act0, Active region; Act1, First active region; Act2, Second active region; WL, Word line structure; BPSIN, Substrate insulating layer; BPSI, Substrate etching positioning layer; MASK1, First mask layer; MASK2, Second mask layer; MASK3, Third mask layer; ESL, Etch barrier layer; BL, Bit line structure; BLL, Bit line lead; BLL1, Polysilicon filling layer; BLL2, Bit line conductive layer; B LL21, First conductive layer of bit line; BLL22, Second conductive layer of bit line; BLL3, Insulating top cover layer of bit line; BLF, Insulating filler layer; BLF1, First insulating filler layer; BLF2, Second insulating filler layer; BLD, Insulating layer of bit line; BLD1, First insulating layer of bit line; BLD2, Second insulating layer of bit line; PLUG, Conductive plug; PAD, Adapter electrode; PAD0, Electrode material layer; PAD1, Isolating material layer; BLGR, Bit line contact groove; BLPIT, Recess; HOLE0, Plug hole. Detailed Implementation

[0079] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0080] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0081] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0082] This disclosure provides a semiconductor structure and its fabrication method, see [link to relevant documentation]. Figure 29 The method for fabricating the semiconductor structure provided in this disclosure includes:

[0083] Step S110, see Figure 2 A semiconductor substrate BP is provided, the semiconductor substrate BP having an active region Act0; the active region Act0 includes a first active region Act1 and a second active region Act2 that are isolated from each other;

[0084] Step S120, see Figure 8 Bit line contact groove BLGR is formed on semiconductor substrate BP, and bit line contact groove BLGR exposes first active region Act1;

[0085] Step S130, see Figure 10 An etch barrier layer (ESL) is formed to cover the sidewall of the bit line contact groove BLGR; the etch barrier layer (ESL) exposes a portion of the first active region Act1 at the bottom of the bit line contact groove BLGR.

[0086] Step S140, see Figure 11 Using the etch barrier layer ESL as a mask, the semiconductor substrate BP is etched to form a pit BLPIT at the bottom of the on-line contact trench BLGR; the pit BLPIT is at least partially located in the first active region Act1.

[0087] Step S150, see Figure 12 Remove the etch barrier layer (ESL);

[0088] Step S160, see Figure 23 This forms a bitline structure BL, and the bitline leads BLL of the bitline structure BL fill the pits BLPIT.

[0089] Step S170, see Figure 25 This forms a conductive plug PLUG, which is electrically connected to the second active region Act2.

[0090] According to the semiconductor structure fabrication method provided in this disclosure, after forming the bit line contact trench BLGR, a pit BLPIT is also formed at the bottom of the bit line contact trench BLGR. When forming the bit line lead BLL, the bit line lead BLL can fill the pit BLPIT to increase the contact area between the bit line lead BLL and the first active region Act1, improve the charge transfer speed between the bit line lead BLL and the first active region Act1, avoid the limitation of charge transfer speed on the semiconductor structure, and improve the performance of the semiconductor device. According to the semiconductor structure fabrication method provided in this disclosure, the formed semiconductor structure has a semiconductor substrate BP, a bit line structure BL, and a conductive plug PLUG. Among them, the semiconductor substrate BP has an active region Act0; the active region Act0 includes a first active region Act1 and a second active region Act2 that are isolated from each other. A bit line contact trench BLGR overlapping with the first active region Act1 is provided on the semiconductor substrate BP, and the bottom of the bit line contact trench BLGR has a pit BLPIT located at least partially in the first active region Act1. The bit line structure BL includes a bit line lead BLL for conduction, the bit line lead BLL filling a pit BLPIT and electrically connected to a first active region Act1 within a bit line contact groove BLGR. A conductive plug PLUG is electrically connected to a second active region Act2. The semiconductor structure of this disclosure can be fabricated using the above-described method, and therefore has the same or similar technical effects, which will not be elaborated further here.

[0091] The principles, details, and effects of the semiconductor structure fabrication method provided in this disclosure will be further explained and illustrated below with reference to the accompanying drawings.

[0092] In step S110, a semiconductor substrate BP can be provided, see [link to relevant documentation]. Figure 2The semiconductor substrate BP is filled with a recessed transistor and a word line structure WL, wherein the word line structure WL can be connected to the gate of the recessed transistor or partially reused as the gate of the recessed transistor.

[0093] The semiconductor substrate BP can be made of materials selected from Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. In some embodiments, it also includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). The semiconductor substrate BP can also be doped, for example, locally lightly doped to form the channel of the recessed transistor, and locally heavily doped to enable the source and drain of the recessed transistor to be electrically connected to the bit line structure BL and the conductive plug PLUG.

[0094] See Figure 1 and Figure 3 The semiconductor substrate BP has shallow isolation trenches (STIs) to allow the semiconductor substrate BP to form multiple independent active regions (Act0). See also Figure 2 and Figure 4 The shallow trench can be filled with an insulating medium to form a shallow trench isolation structure (STI0). For example, it can be filled with a dielectric such as silicon oxide as the insulating medium. See also Figure 1 In one embodiment of this disclosure, each active region Act0 is arranged into multiple active region columns that extend along a first direction C and are parallel to each other. Any active region column may include multiple active regions Act0 and the extension direction of the active regions Act0 is the first direction C.

[0095] Optionally, the semiconductor substrate BP is further provided with word line trenches extending along a second direction D, the angle between the second direction D and the first direction C being less than 90°; the word line structure WL is buried in the word line trenches. See also... Figure 2The word line trench sequentially penetrates the shallow trench isolation structure STI0 and the active region Act0 along the second direction D, exposing the semiconductor substrate BP in the active region Act0. The active region Act0 can be divided by the word line trench into a first active region Act1 and a second active region Act2, which are mutually isolated. The first active region Act1 is used for electrical connection with the bit line lead BLL, and the second active region Act2 is used for electrical connection with the conductive plug PLUG. In some embodiments, the doping dose on the surface of the semiconductor substrate BP exposed by the word line trench can be adjusted, for example, by increasing the doping dose at the bottom of the word line trench or implanting ions of the opposite type, thereby adjusting the threshold voltage of the recessed transistor. Within the word line trench, there can be a gate dielectric layer covering the sidewalls of the word line trench, and a word line inside the gate dielectric layer. The gate dielectric layer in the active region Act0 can serve as the gate insulating layer of the recessed transistor, and the word line can be partially reused as the gate of the recessed transistor. It is understood that the gate dielectric layer can be a single insulating material, a composite of multiple insulating materials, or an air gap can be encapsulated within the multiple insulating materials; this disclosure does not limit this. In the active region Act0, the portion of the semiconductor substrate BP corresponding to the word line can be the channel of a recessed transistor, and the portion of the semiconductor substrate BP connected to the channel can serve as the source and drain of the recessed transistor. The word line trench can also be filled with insulating material to form a dielectric cap; this dielectric cap covers the word line, thus embedding the word line in the semiconductor substrate BP. Optionally, an insulating material can also be disposed on the surface of the semiconductor substrate BP to form a protective layer, which covers the semiconductor substrate BP and protects the active region Act0. In one embodiment of this disclosure, the material of the protective layer can be silicon nitride or silicon oxide.

[0096] Optionally, the surface of the semiconductor substrate BP can be heavily doped to ensure that the source and drain of the recessed transistor have good conductivity, thereby ensuring that the bit line structure BL and the conductive plug PLUG can be electrically connected to the source and drain of the recessed transistor.

[0097] In one embodiment of this disclosure, three columns of active regions are periodically arranged along the second direction D, forming a cycle; columns of active regions Act0 are periodically arranged along a third direction E, perpendicular to the second direction D and within the semiconductor substrate BP. In other words, within the same column of active regions, the sum of the length of the active region Act0 and the distance between two adjacent active regions Act0 within the same column is a predetermined dimension. In two adjacent columns of active regions, after translating the pattern of one column along the second direction D to the adjacent column, the pattern of the translated active region Act0 column can be translated by 1 / 3 of a predetermined dimension along a specific direction in the first direction C, thus coinciding with the active region Act0 pattern of the adjacent column. Similarly, after translating the pattern of one column along the third direction E to the adjacent column, the pattern of the translated active region column coincides with the active region Act0 pattern of the adjacent column.

[0098] Optionally, in one embodiment of this disclosure, any active region Act0 passes through two word line grooves, such that two word line structures WL pass through the active region Act0. Thus, from a top view, the active region Act0 is divided into a first contact area and a second contact area by the two word line structures WL; wherein the first contact area is located between the two word line structures WL passing through the active region Act0, and there are two second contact areas, each located on either side of the first contact area. In a further embodiment, the portion of the active region Act0 located in the first contact area can be designated as the first active region Act1; the portion of the active region Act0 located in the second contact area can be designated as the second active region Act2.

[0099] Alternatively, the semiconductor substrate BP can be prepared by the following method:

[0100] Step S210: Provide a semiconductor substrate BP, which can be a P-type lightly doped single-crystal silicon substrate or an N-type lightly doped single-crystal silicon substrate.

[0101] In step S220, a shallow isolation trench STI is formed on the semiconductor substrate BP to isolate multiple independent active regions Act0 on the surface of the semiconductor substrate BP. Any one of the active regions Act0 extends along the first direction C.

[0102] Step S230: Fill the shallow trench STI with a dielectric to form a shallow trench isolation structure STI0, wherein the dielectric may be silicon oxide.

[0103] In step S240, word line trenches extending along the second direction D are etched on the semiconductor substrate BP. The word line trenches sequentially penetrate the shallow trench isolation structure STI0 and the active region Act0.

[0104] Step S250: A gate dielectric layer is formed covering the sidewalls of the word line trench, and a conductive structure is filled inside the gate dielectric layer to form a word line.

[0105] Step S260: Fill the word line groove with a dielectric to form a dielectric cap covering the word line, thereby obtaining the word line structure WL.

[0106] Thus, in the active region Act0, the word line can be partially reused as the gate of the recessed transistor, the gate dielectric layer can be partially reused as the gate insulating layer of the recessed transistor, and the portion of the semiconductor substrate BP adjacent to the word line can serve as the channel of the recessed transistor. The recessed transistor and the word line are buried in the semiconductor substrate BP.

[0107] It is understood that in the semiconductor fabrication method of this disclosure, as each fabrication process proceeds, corresponding intermediate products can be obtained after each process. These intermediate products are all gradually formed based on the semiconductor substrate BP of this disclosure. In this disclosure, these intermediate products are defined as the substrate. It is understood that all operations on the substrate are performed on the side of the substrate away from the semiconductor substrate BP.

[0108] In step S120, a bit line contact groove BLGR can be formed on the semiconductor substrate BP, and the bit line contact groove BLGR exposes the first active region Act1.

[0109] Alternatively, step S120 can be implemented using the following method:

[0110] Step S210, see Figure 6 and Figure 7 A first mask layer MASK1 is formed on the semiconductor substrate BP. Figure 6 (Represented by a gray circular shadow in the middle); the first mask layer MASK1 covers the second active region Act2 and exposes the first active region Act1;

[0111] Step S220, see Figure 8 The semiconductor substrate BP is patterned using the first mask layer MASK1 as a mask to form a bit line contact groove BLGR that exposes the first active region Act1.

[0112] Optionally, in step S210, a first mask material layer MASK10 and a second mask layer MASK2 can be sequentially formed on the surface of the substrate. Then, using the second mask layer MASK2 as a mask, the first mask material layer MASK10 is patterned to form the first mask layer MASK1. It is understood that after forming the first mask layer MASK1, the remaining second mask layer MASK2 can be removed, or it can be used together with the first mask layer MASK1 as a mask for the semiconductor substrate BP to form the bit line contact trench BLGR.

[0113] In some implementations, the material of the first mask layer MASK1 can be silicon oxide.

[0114] In some implementations, see Figure 5 Before forming the first mask material layer MASK10, a substrate insulating material layer BPSIN0 can be covered on the surface of the substrate to ensure that the recessed transistor and word line structure WL are buried in the semiconductor substrate BP.

[0115] The substrate insulating material layer BPSIN0 can be a single inorganic insulating material or a multilayer stacked inorganic insulating material. For example, in one embodiment of this disclosure, a silicon oxide layer and a silicon nitride layer can be sequentially formed on the surface of the semiconductor substrate BP (the side for which the bit line structure BL is formed), and the stacked silicon oxide layer and silicon nitride layer can serve as the substrate insulating material layer BPSIN0 in this embodiment. In another embodiment of this disclosure, a silicon nitride layer can be formed on the surface of the semiconductor substrate BP (the side for which the bit line structure BL is formed), and this silicon nitride layer can serve as the substrate insulating material layer BPSIN0 in this embodiment. It is understood that in other embodiments of this disclosure, other inorganic insulating materials or other stacking methods can also be used to form the desired substrate insulating material layer BPSIN0.

[0116] In some embodiments of this disclosure, see Figure 5 Before forming the first mask material layer MASK10, a substrate etching positioning material layer BPSI0 can also be formed on the upper surface of the substrate insulating material layer BPSIN0 (away from the surface of the recessed transistor) to facilitate the patterning operation of the first mask material layer MASK10 and avoid damage to the substrate insulating material layer BPSIN0 and the semiconductor substrate BP during the patterning operation of the first mask material layer MASK10.

[0117] In one embodiment of this disclosure, the material of the substrate etching positioning material layer BPSI0 is different from the material of the first mask material layer MASK10, so as to act as an etching barrier during the patterning process of the first mask material layer MASK10. In one embodiment of this disclosure, the material of the substrate etching positioning material layer BPSI0 can be silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon.

[0118] In step S220, see Figure 8The semiconductor substrate BP can be patterned using the first mask layer MASK1 as a mask to form bit line contact trenches BLGR that expose the first active region Act1. Specifically, the semiconductor substrate BP can be etched using the first mask layer MASK1 as a mask to form bit line contact trenches BLGR in locations not covered by the first mask layer MASK1. Correspondingly, the locations of the semiconductor substrate BP covered by the first mask layer MASK1 remain covered by the first mask layer MASK1, thereby ensuring that the second active region Act2 is not exposed.

[0119] See Figure 6 Based on the position of the first mask layer MASK1, after the first active region Act1 is exposed, adjacent first active regions Act1 are isolated by shallow trench isolation structure STI0 or word line structure WL, so that each first active region Act1 remains isolated.

[0120] Optionally, see Figure 8 If a substrate insulating material layer BPSIN0 and a substrate etching positioning material layer BPSI0 are disposed between the semiconductor substrate BP and the first mask layer MASK1, in step S220, the bit line contact trench BLGR penetrates the substrate insulating material layer BPSIN0 and the substrate etching positioning material layer BPSI0 and extends into the semiconductor substrate BP to expose the first active region Act1. Thus, the substrate insulating layer BPSIN0 and the substrate etching positioning material layer BPSI0 are patterned into the substrate insulating layer BPSIN and the substrate etching positioning layer BPSI0, respectively, in step S220. In some embodiments, step S130 can be implemented using the method shown in steps S310 to S320 below.

[0121] Step S310, see Figure 9 An etch barrier material layer ESL0 is formed covering the surface of the first mask layer MASK1, the sidewalls of the bit line contact groove BLGR, and the bottom of the bit line contact groove BLGR; the etch barrier material layer ESL0 at the bottom of the bit line contact groove BLGR at least partially overlaps with the first active region Act1.

[0122] Step S320, see Figure 10 The etching barrier material layer ESL0 is patterned to remove the portion of the etching barrier material layer ESL0 located at the bottom of the bit line contact groove BLGR, thereby forming an etching barrier layer ESL covering the sidewall of the bit line contact groove BLGR.

[0123] In step S310, the material of the etch barrier layer ESL0 is different from the material of the first active region Act1, so as to enable selective etching of the etch barrier layer ESL0 and the first active region Act1 under different etching conditions. In one embodiment of this disclosure, the material of the etch barrier layer ESL0 can be titanium nitride. Further, titanium nitride is deposited by atomic layer deposition to form the etch barrier layer ESL0.

[0124] Of course, in other embodiments of this disclosure, the material of the etch barrier layer ESL0 can also be other materials, such as metals. Accordingly, other deposition methods can also be used when forming the etch barrier layer ESL0, such as CVD (chemical vapor deposition), as long as the etch barrier layer ESL0 covers the sidewalls of the bit line contact trench BLGR.

[0125] In step S320, see Figure 10 The etch stop material layer ESL0 can be etched to pattern it into an etch stop layer ESL. During the etching process, the portion of the etch stop material layer ESL0 located at the bottom of the bit line contact trench BLGR can be removed to form an etch stop layer ESL covering the sidewalls of the bit line contact trench BLGR. Thus, at least a portion of the first active region Act1 located at the bottom of the bit line contact trench BLGR is exposed by the etch stop layer ESL. Therefore, in step S140, the first active region Act1 exposed by the etch stop layer ESL can be selectively etched to form a pit BLPIT at the bottom of the bit line contact trench BLGR.

[0126] See Figure 10 In some embodiments, during the patterning operation of the etch barrier material layer ESL0, the portion of the etch barrier material layer ESL0 located on the surface of the first mask layer MASK1 can also be removed.

[0127] In one embodiment of this disclosure, the etch stop material layer ESL0 can be patterned using dry etching. This effectively etches the portion of the etch stop material layer ESL0 located on the surface of the first mask layer MASK1 and the portion located at the bottom of the bit line contact groove BLGR, without causing significant damage or etching to the portion of the etch stop material layer ESL0 located on the sidewall of the bit line contact groove BLGR. Thus, the remaining portion of the etch stop material layer ESL0 covers the sidewall of the bit line contact groove BLGR, serving as the etch stop layer ESL of this disclosure.

[0128] In step S140, see Figure 11The first active region Act1 can be etched using the etch stop layer (ESL) as a mask to form a pit (BLPIT) at the bottom of the bit line contact trench (BLGR). In other words, the semiconductor substrate BP exposed by the etch stop layer (ESL) can be selectively etched within the bit line contact trench (BLGR) to form a pit (BLPIT) in the portion not protected by the etch stop layer (ESL). See also Figure 11 The recessed transistor (BLPIT) is at least partially located in the first active region Act1. The BLPIT increases the surface area of ​​the first active region Act1, thereby increasing the contact area between Act1 and the bit line lead BLL, and increasing the charge exchange rate between them. This improves the charge transport rate between the recessed transistor and the bit line structure BL, increasing the data write or read speed of the semiconductor structure, and ultimately improving the performance of the semiconductor structure.

[0129] In some embodiments of this disclosure, the depth of the bit line contact groove BLGR is 3 to 4 times the depth of the pit BLPIT. In this way, the surface area of ​​the first active region Act1 can be maximized to improve the performance of the semiconductor structure, while avoiding the pit BLPIT from collapsing due to excessive depth.

[0130] In this disclosure, the dimension of the bit line lead BLL along the extension direction of the word line structure WL is a first dimension, and the depth of the pit BLPIT is a second dimension. In some embodiments, the second dimension is 0.5 to 2 times the first dimension, for example, the second dimension is equal to the first dimension. Exemplarily, in one embodiment of this disclosure, both the first dimension and the second dimension are 10 nm.

[0131] In this disclosure, the surface area of ​​the first active region Act1 exposed by the bit line contact trench BLGR is a first area when the pit BLPIT is not formed, and a second area after the pit BLPIT is formed. In other words, when the bit line contact trench BLGR is formed on the semiconductor substrate BP, the surface area of ​​the first active region Act1 exposed by the bit line contact trench BLGR is the first area; after the etch stop layer ESL is removed, the surface area of ​​the first active region Act1 exposed by the bit line contact trench BLGR and the pit BLPIT is the second area.

[0132] In some implementations, the second area is 2 to 4 times the first area. This significantly increases the contact area between the bit line lead BLL and the first active region Act1, thereby significantly improving the performance of the semiconductor structure.

[0133] In some embodiments of this disclosure, in step S140, a first etching condition may be used to selectively etch the exposed first active region Act1. Further, under the first etching condition, the etching rate of the first active region Act1 is more than 10 times the etching rate of the etch barrier layer ESL. Further, the etching rate of the first active region Act1 is more than 10 to 20 times the etching rate of the etch barrier layer ESL.

[0134] In one embodiment of this disclosure, the first etching condition is to selectively etch the exposed first active region Act1 using dry etching. During the dry etching process, the etch barrier layer ESL is located on the sidewall of the bit line contact trench BLGR and has a very low etching rate, thereby creating a high etch selectivity ratio between the first active region Act1 and the etch barrier layer ESL.

[0135] In one embodiment of this disclosure, the first etching condition is to etch the first active region Act1 using a gas containing hydrogen bromide.

[0136] In step S150, see Figure 12 The etch barrier layer (ESL) can be removed. This allows for the complete re-exposing of the bit line contact trench (BLGR) to form the bit line structure (BL). Optionally, a second etching condition can be used to selectively etch the etch barrier layer (ESL). Further, under the second etching condition, the etching rate of the etch barrier layer (ESL) is more than 30 times that of the first active region (Act1). Further, the etching rate of the etch barrier layer (ESL) is 30 to 50 times that of the first active region (Act1).

[0137] In one embodiment of this disclosure, the second etching condition involves etching the etch barrier layer ESL using an acidic etching solution containing an oxidant. Exemplarily, in one embodiment, the etching solution may contain sulfuric acid and hydrogen peroxide.

[0138] In step S160, a bit line structure BL can be formed, and the bit line leads BLL of the bit line structure BL fill the pits BLPIT. This increases the contact area between the bit line leads BLL and the recessed transistors, improves the data writing or reading speed, and thus improves the performance of the semiconductor structure.

[0139] In some implementations, the method for forming the bit line structure BL may include steps S410 to S440.

[0140] Step S410, as follows Figure 15 As shown, a polycrystalline silicon filling material layer BLL10 is formed, which fills the full-line contact groove BLGR and the pit BLPIT.

[0141] Step S420, as follows Figure 16 As shown, a bit-line conductive material layer BLL20 and a bit-line insulating top cover material layer BLL30 are sequentially formed covering a polycrystalline silicon filling material layer BLL10.

[0142] Step S430, as Figure 18 As shown, the polysilicon filling material layer BLL10, the bit line conductive material layer BLL20, and the bit line insulating cap material layer BLL30 are patterned to form the bit line lead BLL; the bit line lead BLL fills the pit BLPIT.

[0143] Step S440, as follows Figure 23 As shown, an insulating filler layer BLF forms the filling bit line contact groove BLGR and a bit line insulating layer BLD covers the bit line lead BLL.

[0144] In some implementations, in step S410, such as Figure 13 As shown, polysilicon can first be deposited on the surface of the substrate to form an initial polysilicon filling material layer BLL10. This initial polysilicon filling material layer BLL10 fills the full-line contact trench BLGR and the pit BLPIT, and covers it with a first mask layer MASK1. It is understood that after deposition, the initial polysilicon filling material layer BLL10 can be planarized using a planarization process such as CMP (chemical mechanical polishing). See [link to documentation]. Figure 14 Then, the initial polysilicon filling material layer BLL10 is etched back to expose the first mask layer MASK1. Since the etching rates of polysilicon and the first mask layer MASK1 are different, the initial polysilicon filling material layer BLL10 can be etched back to be substantially flush with the substrate etching positioning layer BPSI to form the desired polysilicon filling material layer BLL10. Then, see... Figure 15 The first mask layer MASK1 can be removed to reduce the thickness of the semiconductor structure. Thus, the polysilicon filling material layer BLL10 and the substrate etching positioning layer BPSI are substantially flush and interlocked. In one embodiment of this disclosure, both the polysilicon filling material layer BLL10 and the substrate etching positioning layer BPSI are made of polysilicon, allowing them to interlock and form a film of the same material.

[0145] Optionally, in step S410, the polycrystalline silicon filling material layer BLL10 may also be crystallized to eliminate defects in the polycrystalline silicon filling material layer BLL10 and improve its electrical stability and conductivity. It is understood that during the crystallization process of the polycrystalline silicon filling material layer BLL10, the substrate etching positioning layer BPSI, which uses polycrystalline silicon as the material, can also be crystallized.

[0146] In step S420, see Figure 16 A bit-line conductive material layer BLL20 and a bit-line insulating top cover material layer BLL30 can be sequentially formed on the substrate; the bit-line conductive material layer BLL20 and the bit-line insulating top cover material layer BLL30 cover a polycrystalline silicon filling material layer BLL10.

[0147] See Figure 16 The bit line conductive material layer BLL20 and the bit line insulating capping material layer BLL30 can be formed by deposition. Both the bit line conductive material layer BLL20 and the bit line insulating capping material layer BLL30 are full-surface material layers to completely cover the polysilicon filling material layer BLL10 and the area between the polysilicon filling material layer BLL10. In one embodiment of this disclosure, the bit line conductive material layer BLL20 covers the polysilicon filling layer BLL10 and the substrate etching positioning layer BPSI; the bit line insulating capping material layer BLL30 covers the bit line conductive material layer BLL20.

[0148] In this disclosure, the bit line conductive material layer BLL20 may include a single conductive material layer or multiple stacked conductive material layers. For example, in one embodiment of this disclosure, the bit line conductive material layer BLL20 includes a first bit line conductive material layer BLL210 and a second bit line conductive material layer BLL220 located on the side of the first bit line conductive material layer BLL210 away from the semiconductor substrate BP. The materials of the first bit line conductive material layer BLL210 and the second bit line conductive material layer BLL220 may be different. Further, the material of the first bit line conductive material layer BLL210 may be titanium nitride, and the material of the second bit line conductive material layer BLL220 may be tungsten.

[0149] In this disclosure, the bit-line insulating top cover material layer BLL30 may include a single inorganic insulating material layer or multiple stacked inorganic insulating material layers. For example, in one embodiment of this disclosure, the bit-line insulating top cover material layer BLL30 may be a silicon nitride layer.

[0150] In step S430, the polysilicon filling material layer BLL10, the bit line conductive material layer BLL20, and the bit line insulating top cover material layer BLL30 can be patterned to form bit line leads BLL; wherein, the bit line leads BLL are filled with pits BLPIT.

[0151] In one embodiment of this disclosure, step S430 may include the following process. See [link to previous document]. Figure 16 A third mask layer MASK3 is formed on the bit line insulation top cover material layer BLL30; such as Figure 17 and Figure 18As shown, using the third mask layer MASK3 as a mask, patterning operations are performed on the polysilicon filling material layer BLL10, the bit line conductive material layer BLL20, and the bit line insulating cap material layer BLL30.

[0152] Furthermore, the bit line insulating cap material layer BLL30 and the bit line second conductive material layer BLL220 can be patterned first to form the bit line insulating cap layer BLL3 and the bit line second conductive layer BLL22, respectively; then, using the bit line second conductive layer BLL22 and the bit line insulating cap layer BLL3 as masks, the bit line first conductive material layer BLL210 and the polysilicon filling material layer BLL10 can be patterned to form the bit line first conductive layer BLL21 and the polysilicon filling layer BLL1, respectively.

[0153] Optionally, see Figure 18 When both the polysilicon filling material layer BLL10 and the substrate etching positioning layer BPSI are made of polysilicon, the substrate etching positioning layer BPSI can also be patterned. Thus, in the portion overlapping with the bit line contact trench BLGR, the bit line lead BLL can include a polysilicon filling layer BLL1, a bit line conductive layer BLL2, and a bit line insulating capping layer BLL3, which are sequentially stacked and patterned. In the portion not overlapping with the bit line contact trench BLGR, the bit line lead BLL can include a substrate etching positioning layer BPSI, a bit line conductive layer BLL2, and a bit line insulating capping layer BLL3, which are sequentially stacked and patterned.

[0154] In step S440, as Figure 20 and Figure 23 As shown, an insulating filler layer BLF that fills the bit line contact groove BLGR can be formed first, and then a bit line insulating layer BLD that covers the bit line lead BLL can be formed.

[0155] In some implementations, the insulating filler layer BLF of the filler bit contact groove BLGR can be formed by the following method: such as Figure 19 As shown, an insulating filler material is deposited on the surface of the substrate to form an insulating filler material layer BLF0 covering the entire substrate; as Figure 20 As shown, the insulating filler material layer BLF0 is patterned to form the insulating filler layer BLF, and the insulating filler layer BLF can fill only the bit line contact groove BLGR. Of course, in other embodiments of this disclosure, a portion of the residual film layer after the insulating filler material layer BLF0 is patterned can also be located outside the bit line contact groove BLGR as other functional film layers besides the insulating filler layer BLF.

[0156] Optionally, the insulating filler layer BLF0 may include one filler material or multiple different filler materials. For example, in one embodiment of this disclosure, the insulating filler layer BLF0 may include a first insulating filler layer BLF10 and a second insulating filler layer BLF20 disposed sequentially; the second insulating filler layer BLF20 is located on the side of the first insulating filler layer BLF10 away from the semiconductor substrate BP. After patterning, the first insulating filler layer BLF10 and the second insulating filler layer BLF20 respectively form the first insulating filler layer BLF1 and the second insulating filler layer BLF2. The first insulating filler layer BLF1 may be in close contact with the sidewall of the bit line contact groove BLGR and the sidewall of the polysilicon filler layer BLL1. Within a bit line contact groove BLGR, the second insulating filler layer BLF2 fills the gap between the first insulating filler layers BLF1. Further, the material of the first insulating filler layer BLF10 is silicon oxide; the material of the second insulating filler layer BLF20 is silicon nitride.

[0157] For example, in another embodiment of this disclosure, the insulating filler layer BLF0 may include silicon nitride layers sequentially stacked on the substrate. Figure 19 (Not shown in the diagram) An insulating first filler layer BLF10 and an insulating second filler layer BLF20; a silicon nitride layer covers the surface of the substrate, including but not limited to the surface of the bit line lead BL and the surface of the bit line contact groove. When patterning the insulating filler layer BLF0, the insulating first filler layer BLF10 and the insulating second filler layer BLF20 can be patterned, while the silicon nitride layer is not patterned. In this way, in the formed insulating filler layer BLF, the silicon nitride layer can maintain coverage and protection for the sidewalls and top surface of the bit line lead.

[0158] In some implementations, the bit line insulation layer BLD covering the bit line lead BLL can be formed by the following methods: such as Figure 21 As shown, a first insulating material layer BLD10 is formed on the surface of the substrate, and the first insulating material layer BLD10 covers the bit line lead BLL. Figure 22 As shown, the first insulating material layer BLD10 of the bit line is patterned to form the first insulating layer BLD1 of the bit line, such that the first insulating layer BLD1 of the bit line only covers the sidewall of the bit line lead BLL. Figure 23 As shown, a second bit-line insulating layer BLD2 is formed on the surface of the substrate. Thus, the second bit-line insulating layer BLD2 and the first bit-line insulating layer BLD1 constitute the bit-line insulating layer BLD disclosed herein. The sidewalls of the bit-line lead BLL are sequentially protected by the first bit-line insulating layer BLD1 and the second bit-line insulating layer BLD2, and the top of the bit-line lead BLL is protected by the second bit-line insulating layer BLD2. See also... Figure 23A bit line insulating layer (BLD) may also be provided between adjacent bit line structures (BL). For example, a second bit line insulating layer (BLD2) may also cover the space between adjacent bit line structures (BL).

[0159] In one embodiment of this disclosure, the material protected by the second insulating layer BLD2 of the bit line can be the same as the material of the top insulating layer BLL3 of the bit line, so that the top insulating layer BLL3 of the bit line and the second insulating layer BLD2 of the bit line have a good bond, thereby improving the insulation effect of the bit line structure BL. Further, both the second insulating layer BLD2 and the top insulating layer BLL3 of the bit line are made of silicon nitride.

[0160] In one embodiment of this disclosure, the first insulating layer BLD1 of the bit line is made of silicon oxide. The second insulating layer BLD2 of the bit line is made of silicon nitride.

[0161] It is understood that the bit line insulation layer BLD can also be made of other inorganic insulating materials or have other film layer structures, and this disclosure does not impose any special limitations.

[0162] In step S170, the conductive plug PLUG can be formed by the following method:

[0163] Step S510, as follows Figure 24 As shown, a plug hole HOLE0 is formed to expose the second active region Act2;

[0164] Step S520, as follows Figure 25 As shown, polysilicon is filled into the plug hole HOLE0 to form a conductive plug PLUG.

[0165] In step S510, see Figure 24 The substrate can be patterned to form a plug hole HOLE0 that exposes the second active region Act2. The plug hole HOLE0 does not overlap with the first active region Act1 or the bit line structure BL.

[0166] In step S520, polysilicon can be deposited into the plug hole HOLE0 to form a conductive plug PLUG. Thus, the conductive plug PLUG can serve as a conductive terminal electrically connected to the second active region Act2, enabling electrical connection to other devices in the semiconductor structure. Further, see... Figure 25 The conductive plug PLUG is completely located within the plug hole HOLE0, but it does not completely fill the plug hole HOLE0. In other words, the top surface of the conductive plug PLUG is lower than the top surface of the bit line structure BL.

[0167] In one embodiment of this disclosure, conductive plugs (PLUGs) are used for electrical connection with transition electrodes, which can be used for electrical connection with other functional devices. When the conductive plugs (PLUGs) are electrically connected to a capacitor or other functional device via the transition electrodes, the semiconductor structure can be a storage device. For example, after forming the conductive plugs (PLUGs), the method for fabricating the semiconductor structure of this disclosure further includes: forming a transition electrode layer on the side of the conductive plugs (PLUGs) away from the semiconductor substrate (BP), the transition electrode layer including a plurality of transition electrodes electrically connected to each conductive plug (PLUG); and forming a device layer on the side of the transition electrode layer away from the semiconductor substrate (BP), the device layer including a plurality of functional devices electrically connected to each transition electrode.

[0168] In one embodiment of this disclosure, the transfer electrode layer can be formed by the following method. See [link to previous document]. Figure 26 An electrode material layer PAD0 can be formed on the substrate; the electrode material layer PAD0 fills the plug hole HOLE0 and is electrically connected to the conductive plug PLUG, and covers the bit line structure BL. See also Figure 27 The electrode material layer PAD0 can be patterned to form an array of distributed transfer electrodes PADs. Each transfer electrode PAD is electrically connected to a conductive plug PLUG. See also... Figure 28 An insulating material can be filled into the gap between the transfer electrodes PAD to form an insulating material layer PAD1. Furthermore, the material of the insulating material layer PAD1 can be silicon nitride.

[0169] It should be noted that although the steps of the semiconductor structure fabrication method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0170] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having an active region and a shallow trench isolation structure, wherein adjacent active regions are isolated by the shallow trench isolation structure; The active region includes a first active region and a second active region that are isolated from each other; A first mask layer is formed on the semiconductor substrate; The first mask layer covers the second active region and exposes the first active region; Using the first mask layer as a mask, a patterning operation is performed on the semiconductor substrate to remove part of the first active region and part of the shallow trench isolation structure, so as to form a bit line contact trench that exposes the first active region and the shallow trench isolation structure. An etching barrier layer is formed covering the sidewalls of the bit line contact groove; The etching barrier layer exposes a portion of the first active region at the bottom of the bit line contact groove; Using the etching barrier layer as a mask, the semiconductor substrate is etched to form a pit at the bottom of the bit line contact trench; The pit is at least partially located in the first active region; Remove the etching barrier layer; A bitline structure is formed, wherein the bitline leads of the bitline structure fill the recess; A conductive plug is formed, and the conductive plug is electrically connected to the second active region; The semiconductor substrate is filled with word line structures; the dimension of the bit line lead along the extension direction of the word line structure is a first dimension; the depth of the pit is a second dimension; Wherein, the second dimension is 0.5 to 2 times the first dimension; When the bit line contact groove is formed on the semiconductor substrate, the surface area of ​​the first active region exposed by the bit line contact groove is the first area. After the etch barrier layer is removed, the surface area of ​​the first active region exposed by the bit line contact groove and the pit is the second area; The second area is 2 to 4 times the first area.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etching barrier layer forming the sidewalls of the bit line contact groove includes: An etching barrier material layer is formed covering the surface of the first mask layer, the sidewalls of the bit line contact groove, and the bottom of the bit line contact groove; the etching barrier material layer at least partially overlaps with the first active region at the bottom of the bit line contact groove. The etching barrier material layer is patterned to remove the portion of the etching barrier material layer located at the bottom of the bit line contact groove, thereby forming an etching barrier layer covering the sidewall of the bit line contact groove.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The material of the etching barrier layer is titanium nitride.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The etching barrier material layer is formed by atomic layer deposition.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that, The etching barrier material layer is patterned by dry etching.

6. The method for preparing a semiconductor structure according to claim 2, characterized in that, Using the etching barrier layer as a mask, etching the first active region includes: The exposed semiconductor substrate is etched using a first etching condition; under the first etching condition, the etching rate of the first active region is more than 10 times the etching rate of the etch barrier layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The first etching condition is to use a gas containing hydrogen bromide to etch the first active region.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that, Removing the etching barrier layer includes: The etching barrier layer is etched under the second etching conditions; under the second etching conditions, the etching rate of the etching barrier layer is more than 30 times that of the etching rate of the first active region.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The second etching condition is to etch the etching barrier layer using an acidic etching solution containing an oxidant.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of bitline structures includes: A polycrystalline silicon filling material layer is formed, which fills the bit line contact groove and the pit; A bit-line conductive material layer and a bit-line insulating top cover material layer are sequentially formed to cover the polycrystalline silicon filling material layer; The polysilicon filling material layer, the bit line conductive material layer, and the bit line insulating cap material layer are patterned to form bit line leads; the bit line leads fill the pits. An insulating filler layer is formed to fill the bit line contact groove and a bit line insulating layer is formed to cover the bit line lead.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of conductive plugs includes: Forming an embolization hole that exposes the second active region; The plug hole is filled with polycrystalline silicon to form the conductive plug.

12. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method for preparing the semiconductor structure further includes: A transfer electrode layer is formed on the side of the conductive plug away from the semiconductor substrate, the transfer electrode layer including a plurality of transfer electrodes electrically connected to each conductive plug. A device layer is formed on the side of the transition electrode layer away from the semiconductor substrate, and the device layer includes a plurality of functional devices electrically connected to each of the transition electrodes in a one-to-one correspondence.

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