A memory

Abstract

Embodiments of the present application provide a memory, relating to the field of storage, which can reduce the area and power consumption of the memory while ensuring the flexibility of writing. The memory comprises a plurality of storage units distributed in an array, wherein the storage units comprise a spin-orbit moment providing line; a free layer of a first MTJ is connected to the spin-orbit moment providing line, and a free layer of a second MTJ is connected to the spin-orbit moment providing line; a first bit line, a second bit line and a third bit line are further connected to the spin-orbit moment providing line, the connection ends of the first bit line and the second bit line on the spin-orbit moment providing line are located on the two sides of the first MTJ and the second MTJ, and the connection end of the third bit line on the spin-orbit moment providing line is between the first MTJ and the second MTJ.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, in particular to a memory. BACKGROUND

[0002] Magnetic random access memory (MRAM) has the advantages of non-volatility, high density, high read-write speed, radiation resistance, etc. The core storage unit of the magnetic random access memory is a sandwich film structure formed by stacking a reference layer, a tunneling layer and a free layer in sequence, wherein the reference layer and the free layer are usually made of magnetic material, for example, cobalt-iron-boron CoFeB; the tunneling layer is made of non-magnetic insulating material, for example, magnesium oxide MgO. Generally, the magnetization state of the magnetic material on the upper and lower interfaces of the tunneling layer is in a parallel state, and the resistance of the storage unit is in a low resistance state, recorded as "0"; in an anti-parallel state, the resistance of the storage unit is in a high resistance state, recorded as "1". The memory reading circuit determines the information of the memory as "0" or "1" by judging the size of the output current by applying a small amplitude reading voltage to the storage unit.

[0003] At present, the basic write principle adopted by the large-capacity magnetic random access memory products on the market is: based on the current-induced magnetization switching effect, also known as spin transfer torque (STT), the driving current generated by the transistor flows through the storage unit in the forward or reverse direction, changes the magnetization state of the free layer, realizes the different magnetization states (parallel or anti-parallel) of the magnetic material on the upper and lower interfaces of the tunneling layer, and realizes the writing of data "0" and "1". The current spin transfer torque STT-MRAM has a large write current, and the size of the transistor used to generate the driving current cannot be continuously reduced with the core storage unit, thereby limiting the further miniaturization of the STT-MRAM storage area.

[0004] And the SOT-MRAM based on spin orbit torque (SOT) writing is very excellent in writing power consumption, writing speed and erasing resistance. The basic structure of the storage unit of the SOT-MRAM is a reference layer, a tunneling layer, a free layer and a spin orbit torque providing line (the thickness is generally several nanometers), by passing a driving current in the forward or reverse direction in the spin orbit torque providing line, the magnetization direction of the free layer is reversed, thereby recording data "0" and "1". The biggest bottleneck of this SOT-MRAM is that one storage unit needs to be connected with two driving transistors, resulting in a too large storage unit area, and a single storage unit usually records one bit, i.e. two states "0" or "1". Therefore, how to reduce the power consumption and the storage area while ensuring the flexibility of writing becomes an important target for performance optimization. SUMMARY

[0005] The application provides a memory which can reduce the area and power consumption of the memory while ensuring the flexibility of writing.

[0006] In a first aspect, a memory is provided. The memory comprises a plurality of memory cells arranged in an array, each memory cell comprising a spin-orbit torque (SOT) current supply line, a first magnetic tunnel junction (MTJ) and a second MTJ, wherein a free layer of the first MTJ is connected to the SOT current supply line, and a free layer of the second MTJ is connected to the SOT current supply line; and a first bit line, a second bit line and a third bit line are further connected to the SOT current supply line, connection ends of the first bit line and the second bit line on the SOT current supply line are located on two sides of the first MTJ and the second MTJ, respectively, and a connection end of the third bit line on the SOT current supply line is between the first MTJ and the second MTJ. The SOT current supply line is also referred to as a spin-orbit torque current supply line, and is a nanometer-thick heavy metal or metal alloy film, for example, platinum, tantalum, tungsten, tantalum-tungsten alloy, etc. The first MTJ comprises a sandwich film layer structure formed by stacking a reference layer, a tunneling layer and a free layer on the SOT current supply line, and the second MTJ comprises a sandwich film layer structure formed by stacking a reference layer, a tunneling layer and a free layer on the SOT current supply line, wherein the reference layer and the free layer are usually magnetic layers formed by using a magnetic material, for example, cobalt-iron-boron (CoFeB), and the tunneling layer comprises a non-magnetic insulating material, for example, magnesium oxide (MgO). The memory provided by the above scheme comprises a plurality of memory cells arranged in an array, each memory cell comprising a SOT current supply line, a first MTJ and a second MTJ, wherein a free layer of the first MTJ is connected to the SOT current supply line, and a free layer of the second MTJ is connected to the SOT current supply line; and a first bit line and a second bit line are further connected to the SOT current supply line, connection ends of the first bit line and the second bit line on the SOT current supply line are located on two sides of the first MTJ and the second MTJ, respectively, and a connection end of a third bit line on the SOT current supply line is between the first MTJ and the second MTJ. In this way, in a writing state, signals provided by the first bit line, the second bit line and the third bit line are used to change the resistance value of the first MTJ and / or the second MTJ; in a reading state, the total resistance value of the first MTJ and the second MTJ read from the reference layers of the first MTJ and the second MTJ is used to indicate the data stored in the memory cell, and under the control of the first bit line, the second bit line and the third bit line, the total resistance of the two MTJs in one memory cell has three or four different resistance value states, so that three or four writing states of data can be represented; therefore, the storage and reading of three or four data states can be realized, and compared with the prior art, one memory cell can only store one bit of two states, so that the area and power consumption of the memory can be reduced while ensuring the flexibility of writing.

[0007] In a possible implementation, the reference layer of the first MTJ is provided with a first electrode, and the reference layer of the second MTJ is provided with a second electrode; the second electrode is configured to receive a read voltage; and the first electrode is configured to output a read current.

[0008] In a possible implementation, the second electrode and the first electrode are connected to a current detection circuit; the current detection circuit is configured to input the read voltage to the second electrode and detect the read current of the first electrode, and the read current corresponds to the total resistance value of the first MTJ and the second MTJ, and indicates the data stored in the storage unit. In this way, according to the read voltage applied to the second electrode by the current detection circuit and the read current detected at the first electrode, the total resistance value of the first MTJ and the second MTJ of the storage unit can be calculated.

[0009] In a possible implementation, the first MTJ and the second MTJ have the same size or different sizes. When the first MTJ and the second MTJ have the same size, the resistance value of the first MTJ is the same as that of the second MTJ when the free layer and the reference layer of the first MTJ are in a parallel state and the free layer and the reference layer of the second MTJ are in the parallel state; and the resistance value of the first MTJ is the same as that of the second MTJ when the free layer and the reference layer of the first MTJ are in an anti-parallel state and the free layer and the reference layer of the second MTJ are in the anti-parallel state. When the first MTJ and the second MTJ have different sizes, the resistance value of the first MTJ is different from that of the second MTJ when the free layer and the reference layer of the first MTJ are in the parallel state and the free layer and the reference layer of the second MTJ are in the parallel state; and the resistance value of the first MTJ is different from that of the second MTJ when the free layer and the reference layer of the first MTJ are in the anti-parallel state and the free layer and the reference layer of the second MTJ are in the anti-parallel state.

[0010] In a possible implementation, the reference layer of the first MTJ is connected to a source line, and the reference layer of the second MTJ is connected to a read word line through a gating switch; and when the gating switch is gated by the read word line, the total resistance value of the first MTJ and the second MTJ is read from the source line and the read word line.

[0011] In a possible implementation, a track moment providing line is connected to a first bit line through a first switch, and a control end of the first switch is connected to a write word line; and the track moment providing line is connected to a second bit line through a second switch, and a control end of the second switch is connected to the write word line; in a write state, the write word line controls the first switch and the second switch to be turned on.

[0012] In a second aspect, a memory is provided, comprising a plurality of memory cells arranged in an array, each memory cell comprising n tunnel junctions connected in series, n being an integer greater than or equal to 2, a first end of the ith tunnel junction being connected to the ith bit line, a second end of the ith tunnel junction being connected to the (i+1)th bit line. Exemplary tunnel junctions include MTJs or ferroelectric tunnel junctions (FTJs). The memory provided by the above-mentioned solution comprises a plurality of memory cells arranged in an array, each memory cell comprising n tunnel junctions connected in series, n being an integer greater than or equal to 2, a first end of the ith tunnel junction being connected to the ith bit line, a second end of the ith tunnel junction being connected to the (i+1)th bit line. In this way, in a write state, the bit lines are used to change the resistance of the tunnel junctions, and in a read state, the total resistance of the n tunnel junctions connected in series read at the 1st bit line and the (n+1)th bit line is used to indicate the data stored in the memory cell. Under the control of the bit lines, the total resistance of the n tunnel junctions connected in series in one memory cell has a plurality of different resistance states, which can represent a plurality of write states of data. Therefore, the storage and reading of a plurality of data states can be realized, and compared with the prior art, in which one memory cell can only store one bit of two states, the area and power consumption of the memory can be reduced while ensuring the flexibility of writing.

[0013] In a possible implementation, a first end of the 1st tunnel junction is connected to a current detection circuit through the 1st bit line, a second end of the ith tunnel junction is connected to the current detection circuit through the (i+1)th bit line, the current detection circuit is used to input a read voltage at the 1st bit line and detect a read current at the (i+1)th bit line, and the total resistance of the n tunnel junctions connected in series corresponding to the read current indicates the data stored in the memory cell. In this way, according to the read voltage applied to the first end of the 1st tunnel junction by the current detection circuit and the read current detected at the second end of the ith tunnel junction, the total resistance of the n tunnel junctions of the memory cell can be calculated.

[0014] In a possible implementation, the tunnel junctions have the same size or different sizes.

[0015] In a possible implementation, the MTJ comprises a reference layer, a tunneling layer and a free layer, wherein the MTJ has a first resistance when the reference layer and the free layer have the same magnetization direction, and the MTJ has a second resistance when the reference layer and the free layer have different magnetization directions.

[0016] In a possible implementation, the FTJ comprises a first electrode, a ferroelectric layer and a second electrode, wherein the FTJ has a first resistance when the ferroelectric layer has a first polarization direction, and the FTJ has a second resistance when the ferroelectric layer has a second polarization direction.

[0017] In a possible implementation, a first end of the first tunnel junction is connected to a first bit line through a first switch, and a second end of the nth tunnel junction is connected to an (n+1)th bit line through a second switch; a control end of the first switch and a control end of the second switch are connected to a word line; in a write state or a read state, the word line controls the first switch and the second switch to be turned on.

[0018] In a third aspect, an electronic device is provided, which includes a circuit board and a memory connected to the circuit board, and the memory is the memory as described above. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 A structural schematic diagram of a storage system provided by an embodiment of the present application is shown in FIG. 1;

[0020] Figure 2 A structural schematic diagram of a storage system provided by another embodiment of the present application is shown in FIG. 2;

[0021] Figure 3 A structural schematic diagram of a storage system provided by still another embodiment of the present application is shown in FIG. 3;

[0022] Figure 4 A structural schematic diagram of a memory provided by an embodiment of the present application is shown in FIG. 4;

[0023] Figure 5 A structural schematic diagram of a memory provided by another embodiment of the present application is shown in FIG. 5;

[0024] Figure 6 A structural schematic diagram of a memory provided by still another embodiment of the present application is shown in FIG. 6;

[0025] Figure 7 A structural schematic diagram of a memory provided by still another embodiment of the present application is shown in FIG. 7;

[0026] Figure 8 A structural schematic diagram of a memory provided by another embodiment of the present application is shown in FIG. 8;

[0027] Figure 9 A structural schematic diagram of a memory provided by still another embodiment of the present application is shown in FIG. 9;

[0028] Figure 10 A structural schematic diagram of an MTJ provided by an embodiment of the present application is shown in FIG. 10;

[0029] Figure 11 A structural schematic diagram of an FTJ provided by an embodiment of the present application is shown in FIG. 11;

[0030] Figure 12 A band structure schematic diagram of an FTJ provided by an embodiment of the present application is shown in FIG. 12;

[0031] Figure 13 A structural diagram of a memory is provided for another embodiment of the present application;

[0032] Figure 14 A structural diagram of a memory is provided for another embodiment of the present application;

[0033] Figure 15 A structural diagram of a memory is provided for another embodiment of the present application;

[0034] Figure 16 A structural diagram of a memory is provided for another embodiment of the present application. DETAILED DESCRIPTION

[0035] The making and using of various embodiments will now be described in detail. It should be appreciated that numerous specific implementation details, relationships, and methods are set forth in order to provide a thorough understanding of the embodiments. One skilled in the relevant art, however, will readily recognize that the techniques described herein can be practiced without one or more of the details or with other elements. In other instances, well-known structures and functions have not been described in order to avoid obscuring aspects of the embodiments.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0037] Circuits or other components can be described as or said to be "configured to" perform a task or tasks, in instances of this sort, "configured to" is used to mean that the circuit / component includes structure (e.g., circuitry) for performing the task or tasks during operation. In such descriptions, "configured to" is used in the same sense as "structured to" and "arranged to", and is used to indicate that the circuit / component is structured, arranged, or built in such a manner that it operates to perform an indicated task or tasks.

[0038] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship of the associated objects is described by "and / or", which means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can represent a, b, c, a and b, a and c, b and c, or a, b and c, where a, b and c can be singular or plural. In addition, in the embodiments of the present application, "first", "second", and the like do not limit the quantity and order.

[0039] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0040] The technical solution of this application can be applied to various storage systems that employ random access memory. For example, the technical solution of this application can be applied to a computer, or to a storage system that includes memory, or includes a processor and memory. The processor can be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor, or a neural network processor, etc.

[0041] Figure 1 This is a schematic diagram of a storage system provided in an embodiment of the present application. The storage system may include a storage device, which may be a random access memory (RAM). Optionally, the storage system may also include a CPU, a cache, and a controller.

[0042] In one embodiment, such as Figure 1 As shown, the storage system can be an embedded memory, which includes an integrated CPU, cache, and storage device. In another embodiment, as... Figure 2 As shown, the storage system can be a standalone memory, comprising an integrated CPU, cache, controller, and storage device, the storage device being coupled to the cache and CPU via the controller. In another embodiment, as... Figure 3 As shown, the storage system includes a storage device, as well as an integrated CPU, cache, controller, and dynamic random access memory (DRAM). The storage device can be coupled to the DRAM as an external storage device. The DRAM is coupled to the cache and the CPU through the controller. Figure 1 , Figure 2 Right now Figure 3 The CPU in the various memory types shown can also be replaced with a CPU core.

[0043] Embodiments of this application provide a structure for a memory 40, with reference to... Figure 4 , Figure 5As shown, it includes: storage cells 41 arranged in an array, such as... Figure 4 As shown, memory 40 includes memory cells arranged in an x*y array, containing multiple BLs (BL0-BL2m+1) and multiple WLs (WL0-WL2j+1). Each memory cell is connected to one or more bit lines (BL) and one or more word lines (WL). For example, memory cell 41 is connected to bit lines BL0-BLm and word lines WL0-WLj. Read and write operations of a memory cell can be controlled by controlling BLs and WLs.

[0044] Specifically, such as Figure 5 As shown, the storage unit 41 includes a track point providing line 413, a first magnetic tunnel junction (MTJ) 411, and a second MTJ 412. The first MTJ 411 and the second MTJ 412 may be located on the same side of the track point providing line 413, or on opposite sides of the track point providing line 413. A first bit line BL1, a second bit line BL2, and a third bit line BL3 are also connected to the track point providing line 413. The connection ends of the first bit line BL1 and the second bit line BL2 on the track point providing line 413 are located on opposite sides of the first MTJ 411 and the second MTJ 412, respectively. The connection end of the third bit line BL3 on the track point providing line 413 is between the first MTJ 411 and the second MTJ 412.

[0045] Among them, the orbital moment providing line 413 is also called the spin orbital moment providing line (described as the spin orbital moment providing line in the following scheme). The spin orbital moment providing line is a nanometer-thick heavy metal or metal alloy thin film, such as: platinum, tantalum, tungsten, tantalum-tungsten alloy, etc. In addition, combined with Figure 5As shown, the first MTJ 411 includes a sandwich film structure of a reference layer 4111, a tunneling layer 4112 and a free layer 4113 stacked on the track moment providing line 413, and the second MTJ 412 includes a sandwich film structure of a reference layer 4121, a tunneling layer 4122 and a free layer 4123 stacked on the track moment providing line 413, wherein the reference layer and the free layer are usually magnetic layers formed of a magnetic material, for example, cobalt iron boron CoFeB; the tunneling layer includes a non-magnetic insulating material, for example, magnesium oxide MgO. The current flowing through the track moment providing line 413 can generate a spin current acting on the magnetic layer, and the generated spin orbit torque causes the magnetization of the free layer 4113 / 4123 to flip; by passing a forward or reverse current in the track moment providing line 413, electrons with different spin directions act on the magnetic layer, thereby realizing the writing of the high resistance state and the low resistance state. When the magnetization directions of the reference layer and the free layer are the same (in the following scheme, it is called that the reference layer and the free layer are in parallel state), the MTJ is in a low resistance state, and the MTJ is a first resistance Rp; when the magnetization directions of the reference layer and the free layer are different (in the following scheme, it is called that the reference layer and the free layer are in anti-parallel state), the MTJ is in a high resistance state, and the MTJ is a second resistance Rap.

[0046] Based on the above principle, in the writing state, the signals provided by the first bit line BL1, the second bit line BL2 and the third bit line BL3 are used to change the resistance values of the first MTJ 411 and / or the second MTJ 412; in the reading state, the total resistance values of the first MTJ and the second MTJ read from the reference layer 4111 of the first MTJ 411 and the reference layer 4121 of the second MTJ 412 are used to indicate the data stored in the storage unit.

[0047] In the embodiments of the present application, the sizes of the first MTJ 411 and the second MTJ 412 are not limited, i.e., the sizes of the first MTJ 411 and the second MTJ 412 are the same or different.

[0048] When the free layer 4113 and the reference layer 4111 of the first MTJ 411 are in parallel state, and the free layer 4123 and the reference layer 4121 of the second MTJ 412 are in parallel state, the resistance values of the first MTJ 411 and the second MTJ 412 are the same low resistance state; when the free layer 4113 and the reference layer 4111 of the first MTJ 411 are in anti-parallel state, and the free layer 4123 and the reference layer 4121 of the second MTJ 412 are in anti-parallel state, the resistance values of the first MTJ 411 and the second MTJ 412 are the same high resistance state; when the sizes of the first MTJ 411 and the second MTJ 412 are the same, the resistance values of the first MTJ 411 and the second MTJ 412 are the same.

[0049] Combination Figure 5 As shown in FIG. 4, taking the example that the size of the first MTJ 411 is the same as the size of the second MTJ 412. Referring to Table 1, the voltage of the signals provided by the first bit line BL1, the second bit line BL2 and the third bit line BL3, and the corresponding relationship between the write state of the storage unit and the resistance value of the MTJ at the corresponding voltage are provided.

[0050]

[0051] Table 1

[0052] In the write state, the size of the Vw1, Vw2, Vw1', Vw2' voltage needs to be able to change the magnetization state of the free layer of the MTJ, and the floating pointer BL3 is empty, that is, BL3 is not connected to any signal. Specifically, for example, in state 1, the voltage of BL1 is Vw1, the voltage of BL2 is 0, and BL3 is floating. At this time, there is a current direction in the spin orbit torque providing line, which is Figure 5 the direction of the solid arrow in FIG. 4 (from BL1 to BL2), and the magnetization states of the free layer and the reference layer of the two MTJs are both parallel (for reference Figure 5 In FIG. 4, the magnetization direction of the reference layer 4111 (the direction of the solid arrow in the reference layer 4111) and the magnetization direction of the free layer 4113 (the direction of the solid arrow in the free layer 4113), the resistance value of the first MTJ is Rp1, the resistance value of the second MTJ is Rp2, and the total resistance value of the first MTJ and the second MTJ is Rp1+Rp2, which is equivalent to writing the first data in the storage unit, for example, represented in binary as "00"; in state 2, the voltage of BL1 is 0, the voltage of BL2 is Vw2, and BL3 is floating. At this time, the current direction of the spin orbit torque providing line is reversed to Figure 5 the direction of the dotted arrow in FIG. 4 (from BL2 to BL1), and the free layer 4113 / 4123 undergoes magnetization flipping (for reference Figure 5In state 1, the voltage of BL1 is Vw1, the voltage of BL2 is Vw2, and the voltage of BL3 is 0, at this time, there are two current directions in the spin-orbit torque supply line, the first current direction is from BL1 to BL3, and the second current direction is from BL2 to BL3, then the magnetization state of the free layer and the reference layer of the first MTJ is antiparallel state, and the magnetization state of the free layer and the reference layer of the second MTJ is antiparallel state, the resistance value of the first MTJ is Rap1, and the resistance value of the second MTJ is Rap2, and the total resistance value of the first MTJ and the second MTJ is Rap1+Rap2, which is equivalent to writing the second data into the storage unit, for example, the binary representation is recorded as "11"; in state 3, the voltage of BL1 is Vw1', the voltage of BL2 is Vw2', and the voltage of BL3 is 0, at this time, there are two current directions in the spin-orbit torque supply line, the first current direction is from BL1 to BL3, and the second current direction is from BL2 to BL3, then the magnetization state of the free layer and the reference layer of the first MTJ is parallel state, and the magnetization state of the free layer and the reference layer of the second MTJ is antiparallel state, the resistance value of the first MTJ is Rp1, and the resistance value of the second MTJ is Rap2, and the total resistance value of the first MTJ and the second MTJ is Rp1+Rap2, which is equivalent to writing the third data into the storage unit, for example, the binary representation is recorded as "01"; when reading, since the total resistance values corresponding to the above three writing states are all different, when a certain voltage value is input between the reference layers of the two MTJs, the total resistance value of the two MTJs can be determined according to the current between the reference layers of the two MTJs, so as to be mapped to the corresponding data in each state. Of course, in state 3, the voltage of BL1 can be 0, the voltage of BL2 can be 0, and the voltage of BL3 can be Vw', where Vw'>0, at this time, there are two current directions in the spin-orbit torque supply line, the first current direction is from BL3 to BL1, and the second current direction is from BL3 to BL2, then the magnetization state of the free layer and the reference layer of the first MTJ is antiparallel state, and the magnetization state of the free layer and the reference layer of the second MTJ is parallel state, the resistance value of the first MTJ is Rap1, and the resistance value of the second MTJ is Rp2, and the total resistance value of the first MTJ and the second MTJ is Rap1+Rp2, which is equivalent to writing the third data into the storage unit, for example, the binary representation is recorded as "10"; since the size of the first MTJ 411 and the second MTJ 412 is the same, Rap1+Rp2=Rp1+Rap2, therefore in state 3, only one data can be mapped, that is, the total resistance value in state 3 can only be mapped to any one of "10" or "01".Of course, in some examples, the specific values of Vw1, Vw2, Vw1', Vw2', Vw' are not limited, since the spin-orbit torque provides the current direction in the line, which determines the magnetization direction of the free layer, thus, in state 1, when the voltage Vw1>0, the current direction is from BL1 to BL2, in state 2, when the voltage Vw2>0, the current direction is from BL2 to BL1; in state 3, Vw1'>0, Vw2'>0, the current direction is from BL1 to BL3, and from BL2 to BL3; or, in state 3, Vw'>0, the current direction is from BL2 to BL1, and from BL3 to BL2; the values of Vw1, Vw2, Vw1', Vw2', Vw' can be large enough to ensure that the current is large enough to change the magnetization direction of the free layer.

[0053] When the free layer 4113 of the first MTJ 411 and the reference layer 4111 are in a parallel state, and the free layer 4123 of the second MTJ 412 and the reference layer 4121 are in a parallel state, the resistance values of the first MTJ 411 and the second MTJ 412 are both in a low resistance state, and the sizes of the first MTJ 411 and the second MTJ 412 are different, the resistance values of the first MTJ 411 and the second MTJ 412 are different; when the free layer 4113 of the first MTJ 411 and the reference layer 4111 are in an anti-parallel state, and the free layer 4123 of the second MTJ 412 and the reference layer 4121 are in an anti-parallel state, the resistance values of the first MTJ 411 and the second MTJ 412 are both in a high resistance state, and the sizes of the first MTJ 411 and the second MTJ 412 are different, the resistance values of the first MTJ 411 and the second MTJ 412 are different.

[0054] In combination Figure 6 As shown in the figure, taking the example that the sizes of the first MTJ 411 and the second MTJ 412 are different. Referring to Table 2, the voltages of the signals provided by the first bit line BL1, the second bit line BL2, and the third bit line BL3 are provided, and the corresponding relationship between the write state of the storage unit and the resistance value of the MTJ under the corresponding voltage is provided.

[0055]

[0056] Table 2

[0057] In the write state, the sizes of the Vw1 and Vw2 voltages need to be able to change the magnetization state of the free layer of the MTJ, and the suspended finger BL3 is empty, that is, BL3 is not connected to any signal. Taking Figure 6Taking the scheme shown as an example, assume that the resistance value of the first MTJ high-resistance state is greater than the resistance value of the second MTJ high-resistance state, and the resistance value of the first MTJ low-resistance state is greater than the resistance value of the second MTJ low-resistance state. Specifically, for example, in state 1, the voltage of BL1 is Vw1, the voltage of BL2 is 0, and BL3 is suspended. At this time, there is a current direction in the spin orbital moment supply line, and this current direction is... Figure 6 In the solid arrow direction (from BL1 to BL2), the magnetization states of the free and reference layers of both MTJs are parallel. The resistance value of the first MTJ is Rp1, and the resistance value of the second MTJ is Rp2. The total resistance value of the first and second MTJs is Rp1 + Rp2, which is equivalent to writing the first data in the storage cell, for example, represented as "00" in binary. In state 2, the voltage of BL1 is 0, the voltage of BL2 is Vw2, and BL3 is suspended. At this time, the direction of the line current provided by the spin orbital moment is reversed. Figure 6In the state 3, the voltage of BL1 is Vw1', the voltage of BL2 is Vw2', and the voltage of BL3 is 0. At this time, there are two current directions in the spin orbit torque supply line, the first current direction is from BL1 to BL3, and the second current direction is from BL2 to BL3. The magnetization state of the free layer and the reference layer of the first MTJ is parallel state, and the magnetization state of the free layer and the reference layer of the second MTJ is anti-parallel state. The resistance value of the first MTJ is Rp1, the resistance value of the second MTJ is Rap2, and the total resistance value of the first MTJ and the second MTJ is Rp1+Rap2. It is equivalent to write the third data in the storage unit, for example, the binary representation is "01". In the state 4, the voltage of BL1 is 0, the voltage of BL2 is 0, and the voltage of BL3 is Vw. At this time, there are two current directions in the spin orbit torque supply line, the first current direction is from BL3 to BL1, and the second current direction is from BL3 to BL2. The magnetization state of the free layer and the reference layer of the first MTJ is anti-parallel state, and the magnetization state of the free layer and the reference layer of the second MTJ is parallel state. The resistance value of the first MTJ is Rap1, the resistance value of the second MTJ is Rp2, and the total resistance value of the first MTJ and the second MTJ is Rap1+Rp2. It is equivalent to write the fourth data in the storage unit, for example, the binary representation is "10". When reading, since the total resistance values corresponding to the above four write states are all different, when a certain voltage value is input between the reference layers of the two MTJs, the total resistance value of the two MTJs can be determined according to the current between the reference layers of the two MTJs, so as to map to the corresponding data in each state.Of course, in some examples, the specific values ​​of Vw1, Vw2, Vw1', Vw2', and Vw are not limited. Since the spin orbital moment provides the direction of the current in the line and determines the magnetization direction of the free layer, in state 1, when the voltage Vw1 > 0, the current direction is from BL1 to BL2; in state 2, when the voltage Vw2 > 0, the current direction is from BL2 to BL1; in state 3, Vw1' > 0, Vw2' > 0, the current direction is from BL1 to BL3 and from BL2 to BL3; in state 4, Vw > 0, the current direction is from BL3 to BL1 and from BL3 to BL2. The values ​​of Vw1, Vw2, Vw1', Vw2', and Vw are sufficient to ensure that the current is large enough to change the magnetization direction of the free layer.

[0058] Reference Figure 7 As shown, the reference layer 4111 of the first MTJ411 is connected to the source line SL, and the reference layer 4121 of the second MTJ412 is connected to the read word line RWL (read WL) via a strobe switch S. This RWL can be the one described above. Figure 7 In the process of reading word line RWL (one of the WL lines), when the selector switch S is activated by the read word line RWL, the total resistance value of the first MTJ411 and the second MTJ412 is read from the source line SL and the read word line RWL. The selector switch SL can be a Schottky barrier diode. For example, RWL is connected to the negative terminal of the Schottky barrier diode, and the positive terminal of the Schottky barrier diode is connected to the reference layer 4121 of the second MTJ412. Thus, when the signal input to RWL activates the Schottky barrier diode, the signal input to SL can enter RWL through both the first and second MTJs. The total resistance value of the two MTJs is determined by detecting the signals flowing through the first and second MTJs. Figure 7 The diagram shows the current direction I of the signal flowing through the first MTJ and the second MTJ.

[0059] Reference Figure 7 As shown, the track moment supply line 413 is connected to the first bit line BL1 via the first switch T1, wherein the control terminal of the first switch T1 is connected to the write word line WWL (write WL, which can be the aforementioned Figure 7 One of the WL lines); the track moment supply line 413 is connected to the second bit line BL2 through the second switch T2, wherein the control terminal of the second switch T2 is connected to the write word line WWL; in the write state, the write word line WWL controls the first switch T1 and the second switch T2 to be turned on.

[0060] Reference Figure 7As shown, the first MTJ 411 is provided with a first electrode 413 on the reference layer, and the second MTJ 412 is provided with a second electrode 414 on the reference layer; wherein the second electrode 414 is used to receive a read voltage; and the first electrode 413 is used to output a read current. Specifically, as shown Figure 7 As shown, the second electrode 414 and the first electrode 413 are connected to a current detection circuit 42; the detection circuit 42 is used to input a read voltage to the second electrode 414, and detect the read current of the first electrode 413; the read current corresponds to the total resistance value of the first MTJ and the second MTJ, and indicates the data stored in the storage unit. Wherein, as shown Figure 7 As shown, the first electrode 413 is connected to the current detection circuit 42 through a source line SL, and the second electrode 414 is connected to the current detection circuit 42 through a RWL. In this way, according to the read voltage applied to the second electrode by the current detection circuit 42, and the read current detected at the first electrode, the total resistance value of the first MTJ and the second MTJ of the storage unit can be calculated.

[0061] The above-mentioned scheme provides a memory including an array of storage units, each of which includes a track current supply line, a first magnetic tunnel junction (MTJ) and a second MTJ; wherein the free layer of the first MTJ is connected to the track current supply line, and the free layer of the second MTJ is connected to the track current supply line; the connection end of the first bit line and the second bit line on the track current supply line is located on the two sides of the first MTJ and the second MTJ, and the connection end of the third bit line on the track current supply line is between the first MTJ and the second MTJ. In this way, in the write state, the signals provided by the first bit line, the second bit line and the third bit line are used to change the resistance value of the first MTJ and / or the second MTJ; in the read state, the total resistance value of the first MTJ and the second MTJ read from the reference layer of the first MTJ and the reference layer of the second MTJ is used to indicate the data stored in the storage unit; under the control of the first bit line, the second bit line and the third bit line, the total resistance of the two MTJs in one storage unit has three or four different resistance value states, so as to represent the write state of three or four data; therefore, the storage and reading of three or four data states can be realized; compared with the prior art in which one storage unit can only store one bit of two states, the application reduces the area and power consumption of the memory while ensuring the flexibility of writing.

[0062] Embodiments of the present application provide a structure of a memory 70, as shown in Figure 8 Figure 9 As shown, it includes an array of storage units 71, as shown Figure 8 ​As shown, it includes memory cells arranged in an x*y array, which contains a plurality of BLs (BL0-BL2n+2) and a plurality of WLs (WL0-W2j+1). Each memory cell is connected to one or more bit lines (BLs) and one or more word lines (WLs). For example, memory cell 71 is connected to BL0-BLn+1 and WL0-WLj. By controlling the BLs and WLs, the read / write operation of a memory cell can be controlled.

[0063] Specific reference Figure 9 As shown, memory cell 71 includes n tunnel junctions (711-71n) connected in series, where n is an integer greater than or equal to 2; the first end of the ith tunnel junction is connected to the ith bit line, and the second end of the ith tunnel junction is connected to the (i+1)th bit line; for example Figure 9 As shown in the middle, the first end of the first tunnel junction 711 is connected to the first bit line BL1, and the second end is connected to the second bit line BL2; the first end of the second tunnel junction 712 is connected to the second bit line BL2, and the second end is connected to the third bit line BL3; the first end of the nth tunnel junction 71n is connected to the nth bit line BLn, and the second end is connected to the (n+1)th bit line BLn+1. Among them, the tunnel junction includes the MTJ or ferroelectric tunnel junction (FTJ) described above.

[0064] Reference Figure 10 As shown, the MTJ includes a sandwich film layer structure formed by stacking a reference layer 81, a tunneling layer 82, and a free layer 83, where the reference layer and the free layer are usually magnetic layers formed by using magnetic materials, for example: cobalt-iron-boron CoFeB; the tunneling layer includes non-magnetic insulating materials, for example: magnesium oxide MgO. Among them, the reference layer 81 is the first end of the tunnel junction, and the free layer 83 is the second end of the tunnel junction; or the reference layer 81 is the second end of the tunnel junction, and the free layer 83 is the first end of the tunnel junction; when the magnetization directions of the reference layer 81 and the free layer 83 are the same, the reference layer 81 and the free layer 83 are in a parallel state, the MTJ is in a low resistance state, the MTJ is in a first resistance Rp, and when the magnetization directions of the reference layer 81 and the free layer 83 are different, the reference layer 81 and the free layer 83 are in an anti-parallel state, the MTJ is in a high resistance state, and the MTJ is in a second resistance Rap. The working principle of the MTJ is that the current flowing through the MTJ can cause the magnetization state of the free layer to flip.

[0065] Reference Figure 11As shown, the FTJ includes: a first electrode 91, a ferroelectric layer 92 and a second electrode 93 stacked together; wherein the first electrode 91 and the second electrode 93 are usually made of a conductive material. Exemplarily, the conductive material includes a metal material. For example, tungsten (W), nickel (Ni), platinum (Pt), ruthenium (Ru), iridium (Ir), cobalt (Co), aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN) and the like. The ferroelectric layer 92 can include at least one of the following materials: lead zirconium titanate (PbZrTiO3), strontium bismuth tantalate (SrBi2Ta2O9), hafnium dioxide (HfO2) (note: HfO2may be doped with zirconium (Zr), aluminum (Al), silicon (Si), lanthanum (La) and the like), and the like. Wherein the first electrode 91 is the first end of the tunnel junction, and the second electrode 93 is the second end of the tunnel junction; or the first electrode 91 is the second end of the tunnel junction, and the second electrode 93 is the first end of the tunnel junction; usually the ferroelectric layer is only a few atomic layers thick. Wherein when the ferroelectric layer 92 is in a first polarization direction, the FTJ is in a first resistance, and when the ferroelectric layer 92 is in a second polarization direction, the FTJ is in a second resistance. For details, refer to Figure 12 As shown, the resistance change mechanism of the FTJ is to adjust the polarization state of the ferroelectric layer by an external electric field, change the height of the potential barrier, thereby causing the resistance change in the tunnel junction, and further adjusting the size of the tunneling current. In the initial state, as shown in (a) of Figure 12 , the potential barrier of the ferroelectric layer is φ0, and when the polarization direction of the ferroelectric layer is adjusted to be P polarized to the right (as shown in (b) of Figure 12 from left to right) by an external electric field, the potential barrier of the ferroelectric layer is φ - , the FTJ is in a low resistance state, and the FTJ is in a first resistance Rr; and when the polarization direction of the ferroelectric layer is adjusted to be P polarized to the left (as shown in (c) of Figure 12 from right to left) by an external electric field, the potential barrier of the ferroelectric layer is φ + , the FTJ is in a high resistance state, and the FTJ is in a second resistance Rl; therefore, there are two resistance states of high and low in the ferroelectric tunnel junction, which can be used to represent two logic states of "1" and "0", thereby realizing the storage of data.

[0066] Based on the above principle, wherein in the write state, the signal provided by the bit line BL (BL1-BLn+1) is used to change the resistance of the tunnel junction (711-71n); in the read state, the total resistance value of the n tunnel junctions (711-71n) in series read by the first bit line BL1 and the n+1 bit line BLn+1 is used to indicate the data stored in the storage unit.

[0067] In the embodiments of the present application, the size of the tunnel junction is not limited, i.e. the size of the tunnel junction can be the same or different.

[0068] Exemplarily, refer to Figure 13As shown, the storage unit includes two tunnel junctions (711, 712) in series. If the tunnel junctions are MTJs, when tunnel junction 711 is in the parallel state and tunnel junction 712 is in the parallel state, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are in the low resistance state, and when the sizes of tunnel junction 711 and tunnel junction 712 are the same, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are the same; when tunnel junction 711 is in the anti-parallel state and tunnel junction 712 is in the anti-parallel state, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are in the high resistance state, and when the sizes of tunnel junction 711 and tunnel junction 712 are the same, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are the same. If the tunnel junctions are FTJs, when the polarization directions of tunnel junction 711 and tunnel junction 712 are the same, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are the same.

[0069] In combination Figure 13 As shown, the storage unit includes two tunnel junctions (711, 712) in series. If the tunnel junctions are MTJs, when tunnel junction 711 is in the parallel state and tunnel junction 712 is in the parallel state, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are in the low resistance state, and when the sizes of tunnel junction 711 and tunnel junction 712 are the same, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are the same; when tunnel junction 711 is in the anti-parallel state and tunnel junction 712 is in the anti-parallel state, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are in the high resistance state, and when the sizes of tunnel junction 711 and tunnel junction 712 are the same, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are the same. If the tunnel junctions are FTJs, when the polarization directions of tunnel junction 711 and tunnel junction 712 are the same, the resistance of tunnel junction 711 and the resistance of tunnel junction 712 are the same.

[0070]

[0071] Table 3

[0072] In the write state, the magnitude of the Vw1, Vw2, Vw1', Vw2' voltages needs to be able to change the magnetization state of the free layer of the MTJ, and the floating finger BL2 is empty, i.e., BL2 is not connected to any signal. Specifically, for example, in state 1, the voltage of BL1 is Vw1, the voltage of BL3 is 0, and BL2 is floating. At this time, there is a current direction in the storage unit (the current direction is from BL1 to BL3), and the magnetization state of the free layer and the reference layer of the two MTJs is in the parallel state. The resistance value of MTJ1 is Rp1, the resistance value of MTJ2 is Rp2, and the total resistance value of MTJ1 and MTJ2 is Rp1+Rp2. This is equivalent to writing the first data in the storage unit, for example, the binary representation is recorded as "00". In state 2, the voltage of BL1 is 0, the voltage of BL3 is Vw2, and BL2 is floating. At this time, the current direction in the storage unit is reversed (the current direction is from BL3 to BL1), and the magnetization state of the free layer and the reference layer of the two MTJs is in the anti-parallel state. The resistance value of MTJ1 is Rap1, the resistance value of MTJ2 is Rap2, and the total resistance value of MTJ1 and MTJ2 is Rap1+Rap2. This is equivalent to writing the second data in the storage unit, for example, the binary representation is recorded as "11". In state 3, the voltage of BL1 is Vw1', the voltage of BL2 is 0, and the voltage of BL3 is Vw2'. At this time, there are two current directions in the storage unit, the current direction one is from BL1 to BL2, and the current direction two is from BL3 to BL2. The magnetization state of the free layer and the reference layer of MTJ1 is in the parallel state, and the magnetization state of the free layer and the reference layer of MTJ2 is in the anti-parallel state. The resistance value of MTJ1 is Rp1, the resistance value of MTJ2 is Rap2, and the total resistance value of MTJ1 and MTJ2 is Rp1+Rap2. This is equivalent to writing the third data in the storage unit, for example, the binary representation is recorded as "01". When reading, since the total resistance values corresponding to the above three write states are all different, when a certain voltage value is input to BL1 and BL3, the total resistance value of the two MTJs can be determined according to the current flowing through the two MTJs, thereby mapping to the corresponding data in each state.Of course, in state 3, the voltage of BL1 is 0, the voltage of BL2 is Vw', and the voltage of BL3 is 0, where Vw'>0, at this time, there are two current directions in the storage unit, the first current direction is from BL2 to BL1, and the second current direction is from BL2 to BL3, the magnetization state of the free layer and the reference layer of MTJ1 is anti-parallel state, the magnetization state of the free layer and the reference layer of MTJ2 is parallel state, the resistance value of MTJ1 is Rap1, the resistance value of MTJ2 is Rp2, and the total resistance value of MTJ1 and MTJ2 is Rap1+Rp2, which is equivalent to writing the third data into the storage unit, for example, the binary representation is recorded as "10"; since the sizes of MTJ1 and MTJ2 are the same, Rap1+Rp2=Rp1+Rap2, therefore, in state 3, only one data can be mapped, that is, the total resistance value in state 3 can only map any one of "10" or "01". Of course, in some examples, the specific values of Vw1, Vw2, Vw1', Vw2', and Vw' are not limited, since the current direction in the storage unit determines the magnetization direction of the free layer, therefore, in state 1, when the voltage Vw1>0, the current direction is from BL1 to BL3, in state 2, when the voltage Vw2>0, the current direction is from BL3 to BL1; in state 3, Vw1'>0 and Vw2'>0, the current direction is from BL1 to BL2 and from BL3 to BL2; or, in state 3, Vw'>0, the current direction is from BL2 to BL1 and from BL2 to BL3; the values of Vw1, Vw2, Vw1', Vw2', and Vw' can be ensured to be large enough to change the magnetization direction of the free layer.

[0073] In combination Figure 13 As shown in FIG. 7, taking the FTJ (tunnel junction 711 is FTJ1 and tunnel junction 712 is FTJ2) with the same size as an example for description. Referring to Table 4, the voltages of the signals provided by the first bit line BL1, the second bit line BL2, and the third bit line BL3 are provided, and the corresponding relationship between the write state of the storage unit and the resistance value of the FTJ under the corresponding voltage is provided.

[0074]

[0075] Table 4

[0076] In the write state, the magnitude of the Vw1, Vw2, Vw1' (Vw1' < Vw1), Vw2' (Vw2' < Vw2) voltages needs to be able to change the polarization state of the FTJ, and the floating finger BL2 is empty, i.e., BL2 is not connected to any signal. Specifically, for example, in state 1, the voltage of BL1 is Vw1, the voltage of BL3 is 0, and BL2 is floating. At this time, there is a current direction (the current direction is from BL1 to BL3) in the storage unit, the polarization directions of the two FTJs are the same and are the first polarization direction, for example: both are right polarization, the resistance value of FTJ1 is Rr1, the resistance value of FTJ2 is Rr2, and the total resistance value of FTJ1 and FTJ2 is Rr1+Rr2. Therefore, it is equivalent to writing the first data in the storage unit, for example, the binary representation is recorded as "00"; in state 2, the voltage of BL1 is 0, the voltage of BL3 is Vw2, and BL2 is floating. At this time, there is a current direction (the current direction is from BL3 to BL1) in the storage unit, the polarization directions of the two FTJs are the same and are the second polarization direction, for example: both are left polarization, the resistance value of FTJ1 is Rl1, the resistance value of FTJ2 is Rl2, and the total resistance value of FTJ1 and FTJ2 is Rl1+Rl2. Therefore, it is equivalent to writing the second data in the storage unit, for example, the binary representation is recorded as "11"; in state 3, the voltage of BL1 is Vw1', the voltage of BL2 is 0, and the voltage of BL3 is Vw2'. At this time, there are two current directions in the storage unit, the first current direction is from BL1 to BL2, and the second current direction is from BL3 to BL2. Therefore, the polarization direction of FTJ1 is the first polarization direction, for example: right polarization, the polarization direction of FTJ2 is the second polarization direction, for example: left polarization, the resistance value of FTJ1 is Rr1, the resistance value of FTJ2 is Rl2, and the total resistance value of FTJ1 and FTJ2 is Rr1+Rl2. Therefore, it is equivalent to writing the third data in the storage unit, for example, the binary representation is recorded as "01"; when reading, since the total resistance values corresponding to the above three write states are all different, when a certain voltage value is input to BL1 and BL3, the total resistance value of the two FTJs can be determined according to the current flowing through the two FTJs, thereby mapping to the corresponding data in each state.Of course, state 3 can also be replaced by BL1 voltage being 0, BL2 voltage being Vw', and BL3 voltage being 0, where Vw' > 0. In this case, there are two current directions in the storage cell: one is from BL2 to BL1, and the other is from BL2 to BL3. Then, the polarization direction of FTJ1 is the second polarization direction, for example, left polarization. The polarization direction of FTJ2 is the first polarization direction, for example, right polarization. The resistance value of FTJ1 is Rl1, and the resistance value of FTJ2 is Rr2. The total resistance value of FTJ1 and FTJ2 is Rl1 + Rr2, which is equivalent to writing a third data record in the storage cell, for example, "10" in binary. Since FTJ1 and FTJ2 have the same size, Rl1 + Rr2 = Rr1 + Rl2. Therefore, in state 3, it can only be mapped to one data, that is, the total resistance value in state 3 can only be mapped to either "10" or "01". Of course, in some examples, the specific values ​​of Vw1, Vw2, Vw1', Vw2', and Vw' are not limited. Since the direction of the current in the storage cell determines the polarization direction of the FTJ, in state 1, when voltage Vw1 > 0, the current direction is from BL1 to BL3; in state 2, when voltage Vw2 > 0, the current direction is from BL3 to BL1; in state 3, Vw1' > 0, Vw2' > 0, and the current direction is from BL1 to BL2 and from BL3 to BL2; or, in state 3, Vw' > 0, and the current direction is from BL2 to BL1 and from BL2 to BL3. The values ​​of Vw1, Vw2, Vw1', Vw2', and Vw' are sufficient to ensure that the current is large enough to change the polarization direction of the FTJ.

[0077] For example, refer to Figure 14 As shown, the example is a memory cell containing two series-connected tunnel junctions (711, 712). If the tunnel junction uses an MTJ (Medium-to-Jack) configuration, when tunnel junction 711 and 712 are in a parallel state, their resistances are both low. The resistances of tunnel junctions 711 and 712 are different when their dimensions are different. Similarly, when tunnel junction 711 and 712 are in an anti-parallel state, their resistances are both high. Again, the resistances are different when their dimensions are different. If the tunnel junction uses an FTJ (Flat-to-Fack) configuration, when the polarization directions of tunnel junctions 711 and 712 are the same, their resistances are different when their dimensions are different.

[0078] Combination Figure 14The case of the MTJs (tunnel junction 711 is MTJ1 and tunnel junction 712 is MTJ2) of the same size as the tunnel junction 711 and the tunnel junction 712 is illustrated. The voltages of the signals provided by the first bit line BL1, the second bit line BL2, and the third bit line BL3, and the correspondence between the write state of the storage unit and the resistance value of the MTJ at the respective voltages are provided with reference to Table 5.

[0079]

[0080] Table 5

[0081] In the write state, the Vw1, Vw2, Vw1', Vw2', Vw voltage needs to be able to change the magnetization state of the free layer of the MTJ, the suspended finger BL2 is empty, that is, BL2 is not connected to any signal. Specifically, for example, in state 1, the voltage of BL1 is Vw1, the voltage of BL3 is 0, and BL2 is suspended. At this time, there is a current direction in the storage unit, which is from BL1 to BL3, and the magnetization states of the free layer and the reference layer of the two MTJs are both parallel states. The resistance value of MTJ1 is Rp1, the resistance value of MTJ2 is Rp2, and the total resistance value of MTJ1 and MTJ2 is Rp1+Rp2. It is equivalent to writing the first data in the storage unit, for example, the binary representation is recorded as "00"; in state 2, the voltage of BL1 is 0, the voltage of BL3 is Vw2, and BL2 is suspended. At this time, the current direction in the storage unit is reversed, which is from BL3 to BL1, the free layer is magnetized and reversed, and the magnetization states of the free layer and the reference layer of the two MTJs are both anti-parallel states. The resistance value of MTJ1 is Rap1, the resistance value of MTJ2 is Rap2, and the total resistance value of MTJ1 and MTJ2 is Rap1+Rap2. It is equivalent to writing the second data in the storage unit, for example, the binary representation is recorded as "11"; since the sizes of MTJ1 and MTJ2 are different, Rp1≠Rp2, Rap1≠Rap2; therefore, the total resistance of the two MTJs when MTJ1 is in the parallel state and MTJ2 is in the anti-parallel state is different from the total resistance of the two MTJs when MTJ1 is in the anti-parallel state and MTJ2 is in the parallel state, so two write states can be recorded. In state 3, the voltage of BL1 is Vw1', the voltage of BL3 is Vw2', and the voltage of BL2 is 0. At this time, there are two current directions in the storage unit, the current direction one is BL1 to BL2, and the current direction two is BL3 to BL2. The magnetization state of the free layer and the reference layer of MTJ1 is parallel state, the magnetization state of the free layer and the reference layer of MTJ2 is anti-parallel state, the resistance value of MTJ1 is Rp1, the resistance value of MTJ2 is Rap2, and the total resistance value of MTJ1 and MTJ2 is Rp1+Rap2. It is equivalent to writing the third data in the storage unit, for example, the binary representation is recorded as "01"; in state 4, the voltage of BL1 is 0, the voltage of BL3 is 0, and the voltage of BL2 is Vw. At this time, there are two current directions in the storage unit, the current direction one is BL2 to BL1, and the current direction two is BL2 to BL3. The magnetization state of the free layer and the reference layer of MTJ1 is anti-parallel state, the magnetization state of the free layer and the reference layer of the second MTJ is parallel state, the resistance value of MTJ1 is Rap1, the resistance value of MTJ2 is Rp2, and the total resistance value of MTJ1 and MTJ2 is Rap1+Rp2. It is equivalent to writing the fourth data in the storage unit, for example, the binary representation is recorded as "10".When reading, since the total resistance values corresponding to the above four writing states are all different, when a certain voltage value is input between BL1 and BL3, the total resistance values of the two MTJs can be determined according to the current flowing through the two MTJs, so as to map the corresponding data in each state. Of course, in some examples, the specific values of Vw1, Vw2, Vw1', Vw2', and Vw are not limited. Since the current direction in the storage unit determines the magnetization direction of the free layer, in state 1, when the voltage Vw1>0, the current direction is from BL1 to BL3; in state 2, when the voltage Vw2>0, the current direction is from BL3 to BL1; in state 3, Vw1'>0 and Vw2'>0, the current direction is from BL1 to BL2 and from BL3 to BL2; in state 4, Vw>0, the current direction is from BL2 to BL1 and from BL2 to BL3; the values of Vw1, Vw2, Vw1', Vw2', and Vw can be large enough to ensure that the current is large enough to change the magnetization direction of the free layer.

[0082] In combination Figure 14 As shown in FIG. 7, taking the example of the FTJs with different sizes of tunnel junction 711 and tunnel junction 712 (tunnel junction 711 is FTJ1 and tunnel junction 712 is FTJ2) for illustration. Referring to Table 4, the voltages of the signals provided by the first bit line BL1, the second bit line BL2, and the third bit line BL3 are provided, and the corresponding relationship between the writing state of the storage unit and the resistance value of the FTJ under the corresponding voltage is provided.

[0083]

[0084] Table 6

[0085] In the write state, the magnitude of the Vw1, Vw2, Vw1', Vw2', Vw voltage needs to be able to change the polarization state of the FTJ, and the floating finger BL2 is empty, i.e., BL2 is not connected to any signal. Specifically, for example, in state 1, the voltage of BL1 is Vw1, the voltage of BL3 is 0, and BL2 is floating. At this time, there is a current direction in the storage unit (the current direction is from BL1 to BL3), and the polarization directions of the two FTJs are the same and are the first polarization direction, for example: both are right polarization. The resistance value of FTJ1 is Rr1, the resistance value of FTJ2 is Rr2, and the total resistance value of FTJ1 and FTJ2 is Rr1+Rr2. This is equivalent to writing the first data in the storage unit, for example, the binary representation is recorded as "00". In state 2, the voltage of BL1 is 0, the voltage of BL3 is Vw2, and BL2 is floating. At this time, the current direction in the storage unit is reversed (the current direction is from BL3 to BL1), and the polarization directions of the two FTJs are the same and are the second polarization direction, for example: both are left polarization. The resistance value of FTJ1 is Rl1, the resistance value of FTJ2 is Rl2, and the total resistance value of FTJ1 and FTJ2 is Rl1+Rl2. This is equivalent to writing the second data in the storage unit, for example, the binary representation is recorded as "11". Since the sizes of FTJ1 and FTJ2 are different, Rr1≠Rr2 and Rl1≠Rl2. Therefore, the total resistance of the two FTJs when FTJ1 is in the first polarization direction and FTJ2 is in the second polarization direction is different from the total resistance of the two FTJs when FTJ1 is in the second polarization direction and FTJ2 is in the first polarization direction. Therefore, two write states can be recorded.In state 3, the voltage of BL1 is Vw1', the voltage of BL3 is Vw2', and the voltage of BL2 is 0. At this time, there are two current directions in the storage unit, the first current direction is from BL1 to BL2, and the second current direction is from BL3 to BL2. The polarization direction of FTJ1 is the first polarization direction, for example, right polarization, the polarization direction of FTJ2 is the second polarization direction, for example, left polarization. The resistance value of FTJ1 is Rr1, the resistance value of FTJ2 is Rl2, and the total resistance value of FTJ1 and FTJ2 is Rr1+Rl2. It is equivalent to writing the third data in the storage unit, for example, the binary representation is recorded as "01". In state 4, the voltage of BL1 is 0, the voltage of BL3 is 0, and the voltage of BL2 is Vw. At this time, there are two current directions in the storage unit, the first current direction is from BL2 to BL1, and the second current direction is from BL2 to BL3. The polarization direction of FTJ1 is the second polarization direction, for example, left polarization, the polarization direction of FTJ2 is the first polarization direction, for example, right polarization. The resistance value of FTJ1 is Rl1, the resistance value of FTJ2 is Rr2, and the total resistance value of FTJ1 and FTJ2 is Rl1+Rr2. It is equivalent to writing the fourth data in the storage unit, for example, the binary representation is recorded as "10". When reading, since the total resistance values corresponding to the above four writing states are all different, when a certain voltage value is input to BL1 and BL3, the total resistance value of the two FTJs can be determined according to the current flowing through the two FTJs, so as to be mapped to the corresponding data in each state. Of course, in some examples, the specific values of Vw1, Vw2, Vw1', Vw2', and Vw are not limited. Since the current direction in the storage unit determines the polarization direction of the FTJ, in state 1, when the voltage Vw1>0, the current direction is from BL1 to BL3; in state 2, when the voltage Vw2>0, the current direction is from BL3 to BL1; in state 3, Vw1'>0 and Vw2'>0, the current directions are from BL1 to BL2 and from BL3 to BL2; and in state 4, Vw>0, the current directions are from BL2 to BL1 and from BL2 to BL3. The values of Vw1, Vw2, Vw1', Vw2', and Vw can be large enough to ensure that the size of the current is sufficient to change the polarization direction of the FTJ.

[0086] In combination Figure 15As shown, the storage unit is exemplified by including two series of three tunnel junctions (711, 712, 713). The tunnel junction 711, the tunnel junction 712, and the tunnel junction 713 are exemplified by being the same size FTJs (the tunnel junction 711 is FTJ1, the tunnel junction 712 is FTJ2, and the tunnel junction 713 is FTJ3). The voltages of the signals provided by the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4 are provided with reference to Table 7, and the correspondence between the write state of the storage unit and the resistance value of the FTJ at the respective voltages is provided.

[0087]

[0088] Table 7

[0089] wherein, in the write state, the magnitude of the voltages Vw1, Vw2, Vw1' (Vw1' < Vw1), Vw2' (Vw2' < Vw2), Vw1" (Vw1' < Vw1" < Vw1), and Vw2" (Vw2" < Vw2' < Vw2) needs to be able to change the polarization state of the FTJs, and the floating BL2 / BL3 is open, i.e., BL2 / BL3 is not connected to any signal. Specifically, for example, in state 1, the voltage of BL1 is Vw1, BL2 is floating, BL3 is floating, and the voltage of BL4 is 0, at this time, there is one current direction in the storage unit (the current direction is from BL1 to BL4), the polarization directions of the three FTJs are the same and are all the first polarization direction, for example: all are right polarization r, the resistance values of FTJ1, FTJ2, and FTJ3 are Rr, and the total resistance value of FTJ1, FTJ2, and FTJ3 is 3Rr, which is equivalent to writing the first data in the storage unit, for example, the binary representation is recorded as "00"; in state 2, the voltage of BL1 is 0, BL2 is floating, BL3 is floating, and the voltage of BL4 is Vw2, at this time, there is one current direction in the storage unit (the current direction is from BL4 to BL1), the polarization directions of the three FTJs are the same and are all the second polarization direction, for example: all are left polarization, the resistance values of FTJ1, FTJ2, and FTJ3 are Rl, and the total resistance value of FTJ1, FTJ2, and FTJ3 is 3Rl, which is equivalent to writing the second data in the storage unit, for example, the binary representation is recorded as "11"; in state 3, the voltage of BL1 is Vw1', the voltage of BL2 is 0, BL3 is floating, and the voltage of BL4 is Vw2', at this time, there are two current directions in the storage unit, the first current direction is from BL1 to BL2, and the second current direction is from BL4 to BL2, then the polarization direction of FTJ1 is the first polarization direction, for example: right polarization, the polarization directions of FTJ2 and FTJ3 are the second polarization direction, for example: left polarization, the resistance value of FTJ1 is Rr, the resistance values of FTJ2 and FTJ3 are Rl, and the total resistance value of FTJ1, FTJ2, and FTJ3 is Rr+2Rl, which is equivalent to writing the third data in the storage unit, for example, the binary representation is recorded as "10"; in state 4, the voltage of BL1 is Vw1", the voltage of BL2 is floating, the voltage of BL3 is 0', and the voltage of BL4 is Vw2", at this time, there are two current directions in the storage unit, the first current direction is from BL1 to BL3, and the second current direction is from BL4 to BL3, then the polarization directions of FTJ1 and FTJ2 are the first polarization direction, for example: right polarization, the polarization direction of FTJ3 is the second polarization direction, for example: left polarization, the resistance value of FTJ1 and FTJ2 is Rr, the resistance value of FTJ3 is Rl, and the total resistance value of FTJ1, FTJ2, and FTJ3 is 2Rr+Rl, which is equivalent to writing the third data in the storage unit, for example, the binary representation is recorded as "01".In reading, because the total resistance values corresponding to the above four write states are all different, when BL1 and BL3 input a certain voltage value, the total resistance values of the two FTJs can be determined according to the current flowing through the two FTJs, thereby mapping to the corresponding data in each state. Of course, in some examples, the specific values of Vw1, Vw2, Vw1', Vw2', Vw1'', Vw2'' are not limited, because the current direction in the storage unit determines the polarization direction of the FTJ, therefore, in state 1, when the voltage Vw1>0, the current direction is from BL1 to BL4, in state 2, when the voltage Vw2>0, the current direction is from BL4 to BL1; in state 3, Vw1'>0, Vw2'>0, the current direction is from BL1 to BL2, and from BL4 to BL2; in state 4, Vw1''>0, Vw2''>0, the current direction is from BL1 to BL3, and from BL4 to BL3; the values of Vw1, Vw2, Vw1', Vw2', Vw1'', Vw2'' can only guarantee that the current is large enough to change the polarization direction of the FTJ.

[0090] As shown in Figure 16 the first end of the first tunnel junction 711 is connected to the first bit line BL1 through the first switch T1, and the second end of the nth tunnel junction 71n is connected to the (n+1)th bit line BLn+1 through the second switch T2; the control end of the first switch T1 and the control end of the second switch T2 are connected to the word line WL; in the write state or the read state, the word line WL controls the first switch T1 and the second switch T2 to be turned on.

[0091] Referring to Figure 16 the first end of the first tunnel junction 711 is connected to the first bit line BL1 through the first switch T1, and the second end of the nth tunnel junction 71n is connected to the (n+1)th bit line BLn+1 through the second switch T2; the control end of the first switch T1 and the control end of the second switch T2 are connected to the word line WL; in the write state or the read state, the word line WL controls the first switch T1 and the second switch T2 to be turned on.

[0092] Of course, the above only exemplarily provides several examples, and it can be understood that those skilled in the art can reasonably infer a scheme of connecting four or even more tunnel junctions in series in a storage unit to realize multiple write states according to the above scheme.

[0093] The memory provided by the scheme comprises array-distributed memory cells, the memory cells comprise n serially connected tunnel junctions, n is an integer greater than or equal to 2; a first end of an i th tunnel junction is connected to an i th bit line, and a second end of the i th tunnel junction is connected to an (i+1) th bit line; in this way, in a write state, the bit line is used to change the resistance of the tunnel junction; in a read state, the total resistance value of the n serially connected tunnel junctions read at the 1 st bit line and the (n+1) th bit line is used to indicate the data stored by the memory cell. Under the control of the bit line, the total resistance of the n serially connected tunnel junctions in one memory cell has a plurality of different resistance states, so that a plurality of data write states can be represented; therefore, the storage and reading of a plurality of data states can be realized, and compared with the prior art, one memory cell can only store one bit of two states, so that the area and power consumption of the memory can be reduced while ensuring the flexibility of writing.

[0094] Based on this, the embodiment of the present application further provides an electronic device, which comprises a circuit board and a memory connected with the circuit board, and the memory can be any one of the memories provided above. Wherein, the circuit board can be a printed circuit board (PCB), and of course the circuit board can also be a flexible circuit board (FPC), etc., and the embodiment does not limit the circuit board. Optionally, the electronic device is a computer, a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device, and different types of user equipment or terminal equipment, etc.; the electronic device can also be a network device such as a base station. Optionally, the electronic device further comprises a packaging substrate, the packaging substrate is fixed on the printed circuit board (PCB) through solder balls, and the memory is fixed on the packaging substrate through solder balls. It should be noted that the related description of the memory in the electronic device can be referred to the description of the memory in the above embodiment, and the embodiment of the present application will not be repeated here.

[0095] In another aspect of the present application, a non-transitory computer readable storage medium for use with a computer having software for creating integrated circuits, the computer readable storage medium having one or more computer readable data structures stored thereon, the one or more computer readable data structures having photomask data for fabricating the memory provided by any one of the figures provided above.

[0096] Finally, it should be noted that: the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory, comprising: The memory cell comprises a plurality of memory units arranged in an array, The memory unit comprises a track moment providing line, a first magnetic tunnel junction (MTJ) and a second magnetic tunnel junction (MTJ); The free layer of the first MTJ is connected to the track moment providing line, and the free layer of the second MTJ is connected to the track moment providing line. The track moment providing line is further connected to a first bit line, a second bit line and a third bit line, the connection ends of the first bit line and the second bit line on the track moment providing line are located on the two sides of the first MTJ and the second MTJ, and the connection end of the third bit line on the track moment providing line is between the first MTJ and the second MTJ. The reference layer of the first MTJ is provided with a first electrode, and the reference layer of the second MTJ is provided with a second electrode; wherein the second electrode is used to receive a read voltage; and the first electrode is used to output a read current; The second electrode and the first electrode are connected to a current detection circuit, the detection circuit is used to input the read voltage to the second electrode and detect the read current of the first electrode, and the total resistance value of the first MTJ and the second MTJ corresponding to the read current indicates the data stored in the memory unit.

2. The memory of claim 1, wherein, In the write state, the signals provided by the first bit line, the second bit line and the third bit line are used to change the resistance value of the first MTJ and / or the second MTJ; In the read state, the total resistance value of the first MTJ and the second MTJ read from the reference layer of the first MTJ and the reference layer of the second MTJ is used to indicate the data stored in the memory unit.

3. The memory of claim 1, wherein, The sizes of the first MTJ and the second MTJ are the same or different.

4. The memory of any of claims 1-3, wherein, If the sizes of the first MTJ and the second MTJ are the same, the resistance value of the first MTJ is the same as that of the second MTJ when the free layer and the reference layer of the first MTJ are in a parallel state and the free layer and the reference layer of the second MTJ are in a parallel state, and the resistance value of the first MTJ is the same as that of the second MTJ when the free layer and the reference layer of the first MTJ are in an anti-parallel state and the free layer and the reference layer of the second MTJ are in an anti-parallel state. If the sizes of the first MTJ and the second MTJ are different, the resistance value of the first MTJ is different from that of the second MTJ when the free layer and the reference layer of the first MTJ are in a parallel state and the free layer and the reference layer of the second MTJ are in a parallel state, and the resistance value of the first MTJ is different from that of the second MTJ when the free layer and the reference layer of the first MTJ are in an anti-parallel state and the free layer and the reference layer of the second MTJ are in an anti-parallel state.

5. The memory of any of claims 1-3, wherein, The reference layer of the first MTJ is connected to a source line, and the reference layer of the second MTJ is connected to a read word line through a gating switch. When the gating switch is gated by the read word line, the total resistance value of the first MTJ and the second MTJ is read from the source line and the read word line.

6. The memory of any of claims 1-3, wherein, The track moment providing line is connected to the first bit line through a first switch, and the control end of the first switch is connected to a write word line. The track moment provides a line through the second switch to connect the second bit line, wherein the control end of the second switch is connected to the write word line; In the write state, the write word line controls the first switch and the second switch to be turned on.

7. A memory, comprising: The memory unit includes n tunnel junctions in series, n being an integer greater than or equal to 2; the first end of the i-th tunnel junction is connected to the i-th bit line, and the second end of the i-th tunnel junction is connected to the (i+1)-th bit line; The first end of the first tunnel junction is connected to the current detection circuit through the first bit line, and the second end of the i-th tunnel junction is connected to the current detection circuit through the (i+1)-th bit line, the current detection circuit is used to input a read voltage on the first bit line and detect a read current on the (i+1)-th bit line, and the total resistance value of the n tunnel junctions corresponding to the read current indicates the data stored in the memory unit.

8. The memory of claim 7, wherein, In the write state, the signal provided by the bit line is used to change the resistance of the tunnel junction; in the read state, the total resistance value of the n tunnel junctions read on the first bit line and the (n+1)-th bit line is used to indicate the data stored in the memory unit.

9. The memory of claim 7, wherein, The tunnel junction includes an MTJ or a ferroelectric tunnel junction FTJ.

10. The memory of claim 7, wherein, The sizes of the tunnel junctions are the same or different.

11. The memory of claim 9, wherein, The MTJ includes a reference layer, a tunneling layer and a free layer, wherein when the magnetization directions of the reference layer and the free layer are the same, the MTJ has a first resistance, and when the magnetization directions of the reference layer and the free layer are different, the MTJ has a second resistance.

12. The memory of claim 9, wherein, The FTJ includes a first electrode, a ferroelectric layer and a second electrode, wherein when the ferroelectric layer has a first polarization direction, the FTJ has a first resistance, and when the ferroelectric layer has a second polarization direction, the FTJ has a second resistance.

13. The memory of any of claims 7-12, wherein, The first end of the first tunnel junction is connected to the first bit line through the first switch, and the second end of the n-th tunnel junction is connected to the (n+1)-th bit line through the second switch; the control end of the first switch and the control end of the second switch are connected to the word line; In the write state or the read state, the word line controls the first switch and the second switch to be turned on.

14. An electronic device, comprising: The memory includes a circuit board and a memory connected to the circuit board, and the memory is the memory according to any one of claims 1-13.

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