Complementary 2(n) bit redundancy for single event upset prevention

Abstract

This disclosure describes various aspects of complementary 2(N) bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit (104) includes a data storage element (206) to store a data value, another data storage element (202) to store a complementary data value, a multi-bit data storage element (e.g., 2-bit storage element (204)) to store both the data value and the complementary data value, and voting logic (124) that can enable a complementary data storage scheme with inter-circuit redundancy for preventing SEUs. Additionally, the voting logic of the integrated circuit can implement detection and correction of data value errors and / or implement programming of voting logic criteria, which can be dynamically implemented based on the type of SEU fault detected or corrected.

Description

Background Technology

[0001] Without protection, integrated circuits are often vulnerable under certain environmental conditions—such as when exposed to solar radiation. For example, charged solar particles can strike nodes of an integrated circuit, causing sudden voltage spikes. This phenomenon is called a single-event transient (SET). When a SET occurs at or propagates to a register input during the setup / hold window of a latch circuit, there is a risk that the circuit system may capture the SET. When a SET is captured by a latch circuit, it causes a single-event flip (SEU) that can affect the output value of the latch circuit. Therefore, an SEU can cause significant failures by introducing errors in the nodes of logic elements by changing bit values ​​from expected "1" values ​​to incorrect "0" values ​​or from expected "0" values ​​to incorrect "1" values. These circuit-level errors can adversely affect the operation of many types of safety or mission-critical devices, including aircraft, voting machines, medical devices, satellites, etc. Therefore, minimizing SEU vulnerabilities in circuits and related problems that can affect the operation of various types of electronic devices is of great importance.

[0002] Previous SEU prevention techniques attempted to reduce the likelihood of SEUs by creating hardware redundancy within integrated circuits. These redundant elements were separated by technology-specific distances to offset the risk of naturally occurring SEUs affecting all redundant elements. For example, triple module redundancy (TMR) replicates each critical latch / flip-flop, requiring three compliances with SEU tolerance. However, these redundancies do not address the inherent vulnerability of deliberate attacks. Such attacks can be easily executed when an attacker knows the approximate distances between redundant circuit elements, and because redundant elements are identical, an attack effective on one element will be effective on another. Therefore, previous SEU prevention techniques may be insufficient to defend against malicious actors or SETs (Set-Ups) in other circumstances. Summary of the Invention

[0003] This disclosure describes apparatus and techniques for complementary 2(N)-bit redundancy to prevent single-event upsets (SEUs). In some aspects, the integrated circuit includes a data storage element for storing data values, another data storage element for storing complementary data values, a multi-bit data storage element (e.g., a 2-bit storage element) for storing both the data values ​​and the complementary data values, and voting logic that can enable a complementary data storage scheme with inter-circuit redundancy for SEU prevention. Additionally, the voting logic of the integrated circuit can implement the detection and correction of data value errors and / or implement programming of voting logic standards, which can be dynamically implemented based on the type of SEU fault detected or corrected.

[0004] In one aspect, an integrated circuit for complementary 2(N)-bit redundancy for SEU prevention includes an input node for receiving data values; and a first data storage element having an input operatively coupled to the input node, the first data storage element being configured to store the data values. The integrated circuit also includes at least one inverter operatively coupled to the input node to provide complementary data values; and a second data storage element having an input operatively coupled to the at least one inverter, the second data storage element being configured to store complementary data values. A multi-bit data storage element of the integrated circuit has a first input operatively coupled to the input node; and a second input operatively coupled to the at least one inverter. The multi-bit data storage element is configured to store the data values ​​and complementary data values ​​as separate values. The integrated circuit includes voting logic having an output coupled to the output node of the integrated circuit; and a first input operatively coupled to the output of the first data storage element to receive a first logic value based on the data value stored by the first data storage element. The voting logic also includes a second input operatively coupled to the output of a second data storage element to receive a second logic value based on complementary data values ​​stored in the second data storage element; a third input coupled to the first output of a multi-bit data storage element to receive a third logic value based on data values ​​stored in the multi-bit data storage element; and a fourth input coupled to the second output of the multi-bit data storage element to receive a fourth logic value based on complementary data values ​​stored in the multi-bit data storage element. In each aspect, the voting logic is configured to provide an output data value to the output node of the integrated circuit based on a corresponding set of logic values ​​of at least three of the first, second, third, and fourth logic values. By doing so, the integrated circuit can implement complementary 2(N)-bit redundancy according to one or more aspects, which can prevent or other related errors from affecting the data stored by the circuit.

[0005] Details of one or more embodiments of complementary 2(N)-bit redundancy for SEU prevention are set forth in the accompanying drawings and the following detailed description. Other features and advantages will become apparent from the detailed description, the drawings, and the claims. This summary is provided to introduce the subject matter further described in the detailed description and the drawings. Therefore, the summary should not be construed as describing essential features, nor is it intended to limit the scope of the appended claims. Attached Figure Description

[0006] This disclosure describes, with reference to the following figures, a device and technique for complementary 2(N)-bit redundancy for SEU prevention:

[0007] Figure 1 The example operating environment includes a computing device having a circuit system implemented according to one or more aspects of complementary 2(N)-bit redundancy for SEU prevention.

[0008] Figure 2 This illustrates an example configuration of a complementary 2(N)-bit redundant circuit for SEU prevention;

[0009] Figure 3 This section describes an example configuration of voting logic with configurable logic for implementing one or more aspects of complementary 2(N)-bit redundancy.

[0010] Figure 4 Illustrate example methods for operating complementary 2(N)-bit redundant circuits according to one or more aspects;

[0011] Figure 5 Illustrate example methods for error detection and / or correction that can be implemented for complementary 2(N)-bit redundant circuits;

[0012] Figure 6 This section describes an example method for manufacturing and programming voting logic for complementary 2(N)-bit redundant circuits, based on various aspects.

[0013] Figure 7 An example electronic device illustrating aspects in which complementary 2(N)-bit redundancy can be implemented; and

[0014] Figure 8 This illustrates an example system-on-chip (SoC) environment in which complementary 2(N)-bit redundant circuitry systems can be implemented.

[0015] Using the same or similar reference numerals throughout the description and figures may indicate similar features or components. Detailed Implementation

[0016] Previous techniques for addressing single-event upsets (SEUs) typically attempted to reduce the likelihood of SEUs by creating hardware redundancy within integrated circuits. These redundant elements were separated by technology-specific distances to offset the risk of a naturally occurring SEU affecting all redundant elements. For example, triple module redundancy (TMR) replicates each critical latch / flip-flop, requiring three SEU tolerances. However, these redundancies do not address the inherent vulnerability of deliberate attacks. Such attacks can be easily executed when an attacker knows the approximate distances between redundant circuit elements, and because redundant elements are identical, an attack effective on one element will be effective on another. Therefore, previous SEU prevention techniques may be insufficient to defend against malicious actors or single-event transients (SETs) occurring under other circumstances.

[0017] Compared to the aforementioned techniques, this disclosure describes aspects of complementary 2(N)-bit redundancy for preventing single-event flips (SEUs). In the described aspects, the circuitry of the computing device can be configured to control or minimize vulnerability replication due to stored states by storing complementary logic states in replication cells. The described data storage element can be implemented as a single latch, a master-slave flip-flop register, or a circuit capable of storing data such that the data is stored as complementary values ​​in a single cell to avoid attack precision. As an example, consider a circuit implemented according to the complementary 2(N)-bit redundancy aspect, comprising a first register configured to store a complementary value (R2); and a second register configured to store the original data value (R1). In other words, these registers store different values ​​or have different voltages, and therefore the corresponding node values ​​are also different and have complementary vulnerabilities. Therefore, SEUs are unlikely to occur on both replicated register cells, causing voltages R1 and R2 to change state. Thus, it is unlikely for a malicious actor to cause an SEU because the circuit output is unaffected unless the malicious actor is able to change the corresponding states of both R1 and R2 to their complementary states. Additionally, the circuit may include voting logic that can be configured to enable voting from one or more complementary logic paths (e.g., R1B and / or R2B). As described herein, complementary 2(N)-bit redundancy aspects can prevent SEU from affecting data stored by the circuit's replication unit and can also enable error detection and / or reconfigurable voting logic to resolve detected errors.

[0018] In some aspects, an integrated circuit for complementary 2(N)-bit redundancy for SEU prevention includes an input node for receiving a data value; and a first register having an input operatively coupled to the input node, configured to store the data value. The integrated circuit also includes at least one inverter operatively coupled to the input node to provide a complementary data value; and a second register having an input operatively coupled to the at least one inverter, configured to store the complementary data value. The complementary data value may be an inverted version of the data value. The input of the second register may be coupled to the output of the at least one inverter. A multi-bit register of the integrated circuit has a first input operatively coupled to the input node and a second input operatively coupled to at least one inverter (e.g., the output of the at least one inverter). The multi-bit register is configured to store the data value and the complementary data value as separate values. The integrated circuit includes voting logic having an output coupled to the output node of the integrated circuit; and a first input operatively coupled to the output of the first register to receive a first logic value based on the data value stored in the first register. The voting logic also includes a second input operatively coupled to the output of a second register to receive a second logic value based on a complementary data value stored in the second register; a third input coupled to the first output of a multi-bit register to receive a third logic value based on a data value stored in the multi-bit register; and a fourth input coupled to the second output of the multi-bit register to receive a fourth logic value based on a complementary data value stored in the multi-bit register. In each aspect, the voting logic is configured to provide an output data value to the output node of the integrated circuit based on a corresponding set of logic values ​​of at least three of the first, second, third, and fourth logic values. By doing so, the integrated circuit can implement complementary 2(N)-bit redundancy according to one or more aspects, which can prevent SEU or other related errors from affecting the data stored by the circuit. These are just a few examples of complementary 2(N)-bit redundancy for preventing SEU; other examples are described throughout the disclosure.

[0019] The following discussion describes an operating environment, the technologies that can be employed within that operating environment, and various apparatuses or systems in which components of the operating environment can be embodied. In the context of this disclosure, operating environments are mentioned only by way of example.

[0020] Example Environment

[0021] Figure 1 At point 100, an electronic device 102 is described, in which complementary 2(N)-bit redundancy for SEU prevention can be implemented. The computing device 102 may include, for the sake of brevity, […]. Figure 1 Additional components and interfaces omitted. For example... Figure 1As shown, computing device 102 can be implemented as various consumer electronic devices. As a non-limiting example, computing device 102 can be a mobile phone 102-1, a tablet device 102-2, a laptop computer 102-3, a desktop computer 102-4, a computerized watch 102-5, a wearable computer 102-6, a video game console 102-7, or a voice assistance system 102-8. Although shown, computing device 102 can also be implemented as other types of systems or devices, which may include any of the following: a health monitoring device, a multimedia dongle, a set-top box, a vehicle-based computing system, a navigation device, an aviation computing system, a home automation device, a security system controller, etc. It should be noted that the computing device can be wearable or non-wearable, but can be mobile or relatively fixed (e.g., a broadband router, a mobile hotspot, or a smart device).

[0022] like Figure 1 As shown, computing device 102 includes at least one integrated circuit 104 that enables one or more functions of the computing device. In this example, integrated circuit 104 may be implemented as processor 106, computer-readable storage medium 108, communication interface 110, and / or input / output (I / O) control logic 112 of computing device 102, or a portion thereof. Although not shown, integrated circuit 104 may be implemented as or include other components, including communication units (e.g., modems), input / output controllers, and system interfaces of computing device 102.

[0023] Processor 106 may be implemented as a general-purpose processor, application-specific integrated circuit (ASIC), or system-on-a-chip (SoC), such as a multi-core central processing unit (CPU) or application processor (AP), wherein other components of computing device 102 are integrated therein. Computer-readable medium 108 may include any suitable type of memory medium or storage medium, such as read-only memory (ROM), programmable ROM (PROM), random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), or flash memory. In the context of this discussion, computer-readable medium 108 of computing device 102 is implemented as at least one hardware-based or physical storage device excluding transient signals or carrier waves. Applications, firmware, and / or operating systems (not shown) of computing device 102 may be embodied on computer-readable medium 108 as processor-executable instructions that can be executed by processor 106 to provide the various functions described herein. Computer-readable medium 108 may also store information and data, such as user data or user media accessible through applications, firmware, or operating systems of computing device 102.

[0024] Communication interface 110 enables wired and / or wireless communication of device data, such as received data, transmitted data, or other information described herein. Example communication interface 110 includes a Wireless Personal Area Network (WPAN) radio compliant with various IEEE 802.15 standards, a Wireless Local Area Network (WLAN) radio compliant with any of the various IEEE 802.11 standards, a Wireless Wide Area Network (WWAN, e.g., 3GPP compliant) radio for cellular phones, a Wireless Metropolitan Area Network (WMAN) radio compliant with various IEEE 802.16 standards, and a Wired Local Area Network (LAN) Ethernet transceiver. I / O control logic can be configured as one or more data input / output ports (data I / O ports) through which any type of data, media content, and / or other input can be received, such as user-selectable input, messages, applications, music, television content, recorded video content, and any other type of audio, video, and / or image data received from any content and / or data source. In all respects, integrated circuit 104 and its components may be implemented as any suitable circuit or part thereof in a computing device 102 including processor 106, computer-readable storage medium 108 (CRM 108), communication interface 110, or I / O control logic 112.

[0025] As a non-limiting example, integrated circuit 104 may include a system-on-a-chip (SoC), a central processing unit, a graphics processing unit, an ASIC, a field-programmable gate array (FPGA), a media controller, a memory controller, a tensor processing unit, or any other hardware circuitry including data storage capabilities. In this example, integrated circuit 104 includes an unprotected circuit system 114 and a protected circuit system 116, the protected circuit system 116 including a complementary 2(N)-bit redundant circuit system 118. In various aspects, the protected circuit system 116 of integrated circuit 104 provides some degree of fault prevention or fault tolerance, such as protection against SET or SEU, to increase the reliability of the digital system within and implemented by integrated circuit 104. The unprotected circuit system 114 of integrated circuit 104 may include other circuitry of integrated circuit 104 that does not propose or provide fault prevention or fault tolerance. Therefore, critical or sensitive electronic circuitry of integrated circuit 104 may be implemented as part of the protected circuit system 116 and according to one or more aspects of complementary 2(N)-bit redundancy for SEU prevention.

[0026] exist Figure 1In one example, the protected circuit system 116 includes a complementary 2(N)-bit redundant circuit system 118 implemented using a multi-bit supplementary storage device 120, data inversion logic 122, and voting logic 124. The multi-bit supplementary storage device 120 may include a two-bit register (e.g., a pair of dual interlocked cell (DICE) flip-flops) or latch circuitry that receives and stores a data value and a supplementary data value. The data inversion logic 122 includes any suitable type of inversion logic, inversion node, or inversion gate to provide a supplementary (e.g., inverted) data value (e.g., 0) based on a data value input (e.g., 1). In each aspect, the voting logic 124 is operatively coupled to the multi-bit supplementary storage device 120, an unsupplementary storage element, and a one-bit supplementary storage element. As described herein, storage elements may include one or more of the following: latches, bistable latches, set-reset latches (SR latches), master-slave latches, D latches, flip-flops, D flip-flops, T flip-flops, JK flip-flops, master-slave flip-flops, 1-bit registers, multi-bit registers, data storage circuitry, logic storage cells, charge storage cells, etc. Generally, voting logic 124 may be configured to provide an output data value based on at least three input data values ​​from multi-bit supplementary storage device 120, unsupplementary storage elements, and 1-bit supplementary storage elements. Voting logic 124 may be configured in one or more lifetime states, such as during fabrication (e.g., physical hard-coding), during manufacturing (e.g., fuse programming), or in the field (e.g., self-correcting logic change). As described herein, multi-bit supplementary storage device 120, data inversion logic 122, and voting logic 124 may be implemented in various ways to influence data stored by complementary 2(N)-bit redundant circuitry system 118.

[0027] Figure 2 Example configurations of the complementary 2(N)-bit redundancy circuit system 118 and components capable of implementing complementary 2(N)-bit redundancy for SEU prevention are illustrated at point 200. (See below.) Figure 2 and Figure 3The components and architecture described herein are presented as non-limiting examples of ways in which complementary 2(N)-bit redundancy for SEU prevention can be implemented. Therefore, the aspects described herein can be applied to or extended to any suitable data storage circuitry to implement various features of complementary 2(N)-bit redundancy for SEU prevention. Furthermore, any coupling or connection between the various components can be direct or indirect, such as through one or more intermediate components. For visual simplicity and / or clarity, some irrelevant or redundant components (e.g., logic gates or complementary data paths) or circuitry may be omitted from this or other circuit diagrams. Such omissions should not be construed as limiting, but rather as an example of many ways in which various aspects of the described circuitry can be used or applied to implement complementary 2(N)-bit redundancy for SEU prevention. In other words, the aspects described herein (e.g., circuitry) can also be implemented with any suitable number or combination of logic gates, data paths, and / or additional or separate redundant or duplicated units.

[0028] In all aspects, it can be like Figure 2 The complementary 2(N)-bit redundant circuit system 118 shown is implemented. Figure 2 This describes a multi-register redundant storage module with options for two- or three-level voting logic 124. In this example, the complementary 2(N)-bit redundant circuit system 118 includes a first 1-bit R1 register 202 implemented with corresponding latching circuitry (e.g., set-reset flip-flops) to store data values, a second dual 2-bit register R2 204 as a multi-bit supplementary storage device 120, and a third 1-bit register R3 206. In all aspects, any data storage element (e.g., a 1-bit or 2-bit storage element) including R1, R2, and / or R3 can be implemented as a latch (single latch), a bistable latch, a set-reset latch (SR latch), a master-slave latch, a D latch, a flip-flop, a D flip-flop, a T flip-flop, a JK flip-flop, a master-slave flip-flop, a 1-bit register, a multi-bit register, a data storage circuit, etc., when implemented as a reference. Figure 2When alternative data storage elements (e.g., a single latch or other type of flip-flop) to those data storage elements shown and described herein are used, the aspects described herein can be applied to R1, R2, or R3. The first R1 register 202 includes a primary latch 208 (e.g., a master latch) and an auxiliary latch 210, and is configured to store a supplementary data value (R1B). The second R2 register includes a first latch circuit having a primary latch 212 (e.g., a master latch) and an auxiliary latch 214, and is configured to store the original or unsupplemented data value (R2). The second latch circuit of the R2 register 204 includes a primary latch 216 (e.g., a master latch) and an auxiliary latch 218, and is configured to store a supplementary data value (R2B). In each aspect, the R2 register 204 includes shared logic 220, and the first and second latch circuits operate on the shared logic using a common clock and gating signals. The third R3 register 206 includes a primary latch 222 (e.g., a master latch) and an auxiliary latch 224, and is configured to store the original data value or the unpadded bit value. The respective inputs of registers 202, 204, and 206 can be coupled directly or via data inversion logic 122 to the data input 226 of the complementary 2(N)-bit redundant circuitry system 118 to receive the data value or the supplementary data value. The respective outputs of registers 202, 204, and 206 can be coupled directly or via another example of data inversion logic 122 to voting logic 124 to provide the data value or the supplementary data value to voting logic 124, which can be as described herein (e.g., see reference 124). Figure 3 It is configured to provide the output data value to the data output 228 of the complementary 2(N) bit redundant circuit system 118.

[0029] Generally, registers 202, 204, and 206 can be configured to implement triple modular redundancy (TMR) with additional aspects or features of the complementary 2(N)-bit redundant circuit system 118 for SEU prevention as described herein. For example, a 1-bit R1 register 202 can be configured to store a complementary logic value of NOT (R1) or R1B. As shown, data input D and data output Q are inverted using data inverting logic 122, which includes external NOT gates 230 and 232 that do not provide changes in logic equivalence. The second register R2 204 can be implemented as a dual flip-flop or a 2-bit storage element for 2-bit redundancy, wherein the first flip-flop or data storage element (e.g., bit 1) is configured to store the original data value or the unsupplemented data value (R2). The second flip-flop or data storage element (e.g., bit 2) is configured to store the supplemented data value R2B. Here, the data input D and data output Q of the second data storage element of the second register R2204 are inverted using data inverting logic 122, which includes external NOT gates 234 and 236 that do not provide logical equivalence changes. Similar to the first data storage element of register R2 204, the third register R3 is coupled to data input 226 and can be configured to store the original data value or the unsupplemented data value (R3).

[0030] Voting logic 124 can be coupled directly or via data inversion logic 122 to the corresponding outputs of registers 202, 204, and 206. Generally, voting logic 124 can provide an adaptive or configurable majority voter function to generate output data values ​​based on various combinations of corresponding data values ​​and / or complementary data values ​​stored in registers 202, 204, and / or 206. Voting logic 124, registers 202, 204, and / or 206, or other components, can be implemented in various ways to prevent single-event upsets based on complementary 2(N)-bit redundancy. In various aspects, voting logic 124 can include a majority voter function that can be tuned for a wide range of optimizations. For example, the majority voter function can compute a majority from at least three register outputs—such as R1B, R2, and R3; or R1B, R2B, and R3. As another example, the majority voter function can optionally compute a majority of R1, R2, and R3 instead of inverting the R1B output (e.g., similar to a TMR configuration). As yet another example, most voting functions can be implemented for programmable voting and / or performing round-robin voting. In other cases, voting logic 124 may include an XOR circuit that receives and evaluates complementary pairs (e.g., R1B / R2 or R2B / R3) to detect remote or local register failures. By doing so, voting logic 124 can detect whether one of the R1 or R2 stages has failed and use the other stage as a virtual replacement, thereby enabling the complementary 2(N)-bit redundant circuitry system 118 to implement error detection and correction.

[0031] In various aspects, the complementary 2(N)-bit redundant circuit system 118 can be configured to control or minimize defective copying due to stored states by storing complementary logic states in copy registers or cells. For example... Figure 3 As shown, the voltage values ​​at R1 and R2 are different, therefore the node values ​​are also different and have complementary vulnerabilities. In other words, a SEU is unlikely to occur at both replicated cells, causing voltages R1 and R2 to change state. Therefore, a malicious actor is unlikely to cause an SEU because the circuit output is unaffected unless the malicious actor can change the corresponding states of both R1 and R2 to their complementary states. Figure 3 The document further explains that the majority voting logic can be modified to allow for correction of the voting function from one or more complementary logic paths (e.g., R1B and / or R2B). Various variations of the implementation can be used to balance reliability with power, performance, and area (PPA) costs and overhead.

[0032] Figure 3 An example configuration of voting logic 124 with configurable logic for implementing one or more aspects of complementary 2(N)-bit redundancy is described at point 300. As previously stated, Figure 3 The components and architecture are presented as non-limiting examples of ways to implement complementary 2(N)-bit redundancy for SEU prevention. Therefore, the aspects described herein can be applied to or extended to any suitable data storage circuit to implement various features of complementary 2(N)-bit redundancy for SEU prevention. References Figure 3 The various components described can be implemented as separate hardware- or software-based modules, such as data storage elements and blocks or modules of configurable voting logic. Therefore, any structure or functionality described herein can be provided or configured by the processor core of the data storage module through fuse programming and / or instruction execution (e.g., for different voting algorithms).

[0033] like Figure 3As shown, the voting logic can be implemented using configurable voting logic 302, which may include a programmable fuse 304. Alternatively or additionally, voting logic 124 includes or is associated with an XOR circuit 306 capable of receiving, monitoring, and / or evaluating complementary pairs (e.g., R1B / R2, R2B / R3) to detect remote or local register faults. As described herein, voting logic 124 can provide an adaptive or configurable majority voter function to generate output data values ​​based on various combinations of corresponding data values ​​R2, R3 and / or complementary data values ​​R1B, R2B stored and / or output from registers 202, 204, and / or 206. Voting logic 124, configurable voting logic 302, and / or programmable fuse 304 can be implemented in various ways according to aspects of complementary 2(N)-bit redundancy for preventing single-event upsets. In various aspects, voting logic 124 may include a majority voter function, which can be adjusted or modified via configurable voting logic 302 for extensive optimization. For example, the majority voter function may output from at least three registers, such as R1B, R2, and R3, or R1B, R2B, and R3, to compute a majority. As another example, the majority voter function may optionally not invert the R1B output, but instead compute a majority of R1, R2, and R3 (e.g., similar to a TMR configuration). As yet another example, the majority voter function may be implemented for programmable voting and / or performing round-robin voting.

[0034] In various aspects, the configurable voting logic 302 can be changed, set, or reconfigured at different stages of the lifecycle of a chip or device implementing the 2(N)-bit redundant circuitry system 118. For example, a chip designer can configure multiple examples of the 2(N)-bit redundant circuitry system 118 in a chip with different corresponding voting configurations to mitigate the risk of malicious actor attacks. In other cases, device manufacturers can set the configurable voting logic by burning programmable fuses 304 to implement different custom or scrambled voting logics between manufactured devices. Alternatively or additionally, a self-calibrating implementation of the 2(N)-bit redundant circuitry system 118 can detect faulty registers or data inversion components and reconfigure the configurable voting logic 302 (e.g., by burning additional fuses) to exclude faulty registers from the majority voting function or voting algorithm. For example, voting logic 124 may include XOR circuitry that receives and evaluates complementary pairs (e.g., R1B / R2 or R2B / R3) to detect remote or local register faults. By doing so, voting logic 124 can detect whether one of the R1 or R2 stages is faulty and use the other stage as a virtual replacement, thereby enabling complementary 2(N)-bit redundant circuit system 118 to implement error detection and correction.

[0035] Example Method

[0036] Referencing one or more aspects of complementary 2(N)-bit redundancy used for SEU prevention respectively Figure 4 , Figure 5 and Figure 6 Example methods 400, 500, and 600 are described. Generally, methods 400, 500, and 600 can be, but are not limited to, the set of operations (or actions) performed in the order or combination shown herein. Furthermore, any one or more operations can be repeated, combined, rearranged, skipped, or linked to provide a wide variety of additional and / or alternative methods. References may be made in the following sections of discussion, only as examples. Figure 1 Example environment 100 Figure 2 and / or Figure 3 The circuit, components or configuration, Figure 7 or Figure 8 The device or system, and / or Figure 1 Or other entities detailed in the figures. The techniques and devices described in this disclosure are not limited to embodiments or performance of a circuit or the components or configurations of those circuits described with reference to the accompanying drawings.

[0037] Figure 4 This describes an example method 400 for operating a complementary 2(N)-bit redundant circuit, according to one or more aspects. In some aspects, the operation of method 400 can be implemented to store data values ​​in a manner that protects them from changes caused by single-event upsets.

[0038] At 402, a data value is received at the input of the complementary multi-bit redundancy circuit. The data value may have a voltage or logic state corresponding to a binary value, which may include a zero (0) or a one (1) value. In the context of method 400, it is assumed that the data value received at the input node of the complementary multi-bit redundancy circuit is 1 or a logic high value.

[0039] At position 404, the data value is stored in the first register of the complementary multi-bit redundancy circuit. For example, the data value (e.g., 1) is stored in the first 1-bit register of the complementary multi-bit redundancy circuit.

[0040] At position 406, a complementary data value is generated based on the data value. Generally, data inverting logic or gates, separate from or outside the data storage element of the complementary multi-bit redundancy circuit, provide a complementary or inverted data value with a logic state opposite to the original or unmodified data value. Continuing this example, the data inverting logic of the complementary multi-bit redundancy circuit provides the complementary data value 0.

[0041] At position 408, the complementary data value is stored in the second register of the complementary multi-bit redundancy circuit. For example, the complementary or inverted data value (e.g., 0) is stored in the second 1-bit register of the complementary multi-bit redundancy circuit.

[0042] At 410, the data value and complementary data value are stored in the corresponding storage elements of the multi-bit register of the complementary multi-bit redundancy circuit. The corresponding storage elements of the complementary multi-bit redundancy circuit (e.g., latches or dual interlocked element (DICE) flip-flops) can be timed or gated using the same clock or gating circuitry system within the multi-bit register. In the context of this example, a data value (e.g., 1) is stored in the first storage element of the multi-bit register, and a complementary or inverted data value (e.g., 0) is stored in the second storage element of the multi-bit register to provide complementary multi-bit redundancy using a multi-bit or 2-bit register.

[0043] At 412, voting logic based on complementary multi-bit redundancy circuitry is used to generate the output data value. As input, the voting logic uses at least three of the data value of the first register, the complementary data value of the second register, and the data value and complementary value of the multi-bit registers to generate the output data value. For example, the voting logic may provide an output data value of 1 based on a majority of the outputs from at least three registers—such as R1B, R2, and R3 as described herein, or R1B, R2B, and R3. Summarizing this example, at 414, voting majority logic based on R1B(0), R2(1), and R3(1) provides the output data value of 1 at the output of the complementary multi-bit redundancy circuitry.

[0044] Figure 5 This describes an example method 500 for error detection and / or correction that can be implemented for complementary 2(N)-bit redundant circuitry. In some aspects, method 500 can be implemented to detect and correct errors associated with storage elements in a complementary 2(N)-bit redundant circuitry system.

[0045] At 502, the complementary pair of the data value from the first register and the complementary data value from the second register is monitored. At 504, a fault in either the first or second register is detected based on the corresponding values ​​of the data value and the complementary data value. For example, the complementary pair of the data value and the complementary value can be provided to an XOR circuit, which generates an error when the corresponding values ​​match, indicating that one of the registers has been bit-flipped.

[0046] At point 506, the voting logic is modified to exclude either the first or second register from the voting criteria used to provide the output data value. Based on the detected error, the voting logic can determine which register is providing the incorrect value based on at least two other stored data values ​​and exclude the faulty register from the voting logic to prevent the propagation of data errors.

[0047] At 508, the voting logic is modified to include either the data value from the third register or the complementary data value in the voting criteria. In other words, the voting logic can be modified to introduce or add previously unused register outputs as part of an error self-detection and correction scheme implemented by the complementary 2(N)-bit redundant circuitry system. At 510, the modified voting logic generates an output data value, such as a corrected data value, based on at least one data value from the complementary pair and either the data value from the third register or the complementary data value.

[0048] Figure 6 This describes an example method 600 for manufacturing and programming voting logic for complementary 2(N)-bit redundant circuits, based on various aspects. In some aspects, method 600 can be implemented to provide a complementary 2(N)-bit redundant circuit system with various voting criteria or to resolve errors when they are detected in the complementary 2(N)-bit redundant circuit system. In some cases, the described manufacturing of the complementary 2(N)-bit redundancy and associated components may be biased towards noise tolerance for “high” / “low” logic values ​​in the design / technology.

[0049] At 602, the complementary 2(N)-bit redundant circuit is fabricated to have a first register for storing data values, a second register for storing complementary data values, and a multi-bit register for storing both data values ​​and complementary data values.

[0050] At 604, voting logic is fabricated, operatively coupled to the corresponding outputs of the first register, the second register, and the multi-bit register. The voting logic can be directly coupled to the register outputs or coupled via other fabricated or added components, which may include data inverting logic or gates. In various aspects, complementary 2(N)-bit redundant circuitry can be fabricated with or include voting logic such that operations 602 and 604 are performed together or simultaneously to provide voting logic to the complementary 2(N)-bit redundant circuitry. In various aspects, using multi-bit (Mbit) / 2-bit registers as described can prevent attacks with precision below approximately 10 to 15 nanometers in 5 to 7 nanometer node technologies, which would result in incorrect data flipping. Therefore, for less precise attacks, both the original data value and the supplementary data value are flipped, thus canceling out any data value changes caused by bit flipping. This also provides designers with options such as encoding random voter functions across the chip or in different silicon regions to detect whether the attack / flipping is a local SEU or a global attack. In other words, complementary memory devices ensure that a global attack that flips the same bits requires very high precision in determining which bits to flip or not flip, effectively propagating any data errors outside the described circuitry.

[0051] At 606, voting criteria are determined for the voting logic that provides the data output value based on at least three of the data value stored in the first register, the complementary data value stored in the second register, and the data value and complementary data value stored in the multi-bit register. At 608, the fuses of the voting logic are programmed to configure the voting logic with the determined voting criteria.

[0052] From operation 608, method 600 can return to the previous operation (operation 606) to perform another iteration of one or more operations of method 600, providing the same or different voting criteria to the additional complementary 2(N)-bit redundant circuitry. Alternatively, when the complementary 2(N)-bit redundant circuitry begins operation, method 600 can proceed to operation 610 to implement error detection and / or error correction.

[0053] At 610, an error is detected in one of the first register, second register, or multiple bit registers based on the corresponding output from the register. For example, a data value from a register and a complementary pair of complementary values ​​can be provided to an XOR circuit, which generates an error when the corresponding values ​​match, indicating that one of the registers has been bit-flipped.

[0054] At position 612, the voting logic is reconfigured to eliminate fault registers to correct the data output values ​​provided by the voting logic. Based on detected register errors, the voting logic can determine which register is providing the incorrect value based on at least two other stored data values ​​and eliminate the fault register from the voting logic to prevent the propagation of data errors. Alternatively or additionally, the voting logic can be modified to include data values ​​from a third register (e.g., previously unused) or complementary data values ​​in the voting criteria. In other words, the voting logic can be modified to introduce or add previously unused register outputs as part of an error self-detection and correction scheme implemented by a complementary 2(N)-bit redundant circuitry system.

[0055] Example devices and systems

[0056] Figure 7 This describes the various components of the example electronic device 700, which is based on the previous description. Figures 1 to 6One or more aspects described herein implement complementary 2(N)-bit redundancy for SEU prevention. Electronic device 700 can be implemented as any form of consumer device, computing device, portable device, user device, user equipment, server, communication device, telephone, navigation device, gaming device, media device, messaging device, media player, and / or other type of electronic device or wireless-enabled device, as any one or a combination of fixed or mobile devices. For example, electronic device 700 can be implemented as a smartphone, tablet PC (phablet), laptop computer, set-top box, wireless drone, computing glasses, vehicle-based computing system, or wireless broadband router.

[0057] Electronic device 700 includes a communication transceiver 702 that enables wired and / or wireless communication of device data 704, which is such as received data, transmitted data, or other information as described above. Example communication transceivers 702 include near field communication (NFC) transceivers, WPAN radios compliant with various IEEE 802.15 standards, WLAN radios compliant with any of the various IEEE 802.11 standards, WWAN (3GPP compliant) radios for cellular phones, WMAN radios compliant with various IEEE 802.16 standards, and wired local area network (LAN) Ethernet transceivers.

[0058] The electronic device 700 may also include one or more data input / output ports 706 (data I / O ports 706) that can receive any type of data, media content, and / or other input, such as user-selectable input, messages, applications, music, television content, recorded video content, and any other type of audio, video, and / or image data received from any content and / or data source. The data I / O ports 706 may include a Universal Serial Bus (USB) port, a coaxial cable port, and other serial or parallel connectors (including internal connectors) for flash memory, DVDs, CDs, etc. These data I / O ports 706 can be used to couple the electronic device to components, peripherals, or accessories, such as a keyboard, microphone, or camera.

[0059] The electronic device 700 in this example includes at least one processor 708 (e.g., one or more application processors, processor core microprocessors, digital signal processors (DSPs), controllers, etc.), which may include a combined processor and memory system that executes computer-executable instructions stored on a computer-readable medium to control operation or perform the functions of the device. Generally, the processor or processing system may be implemented at least partially in hardware, which may include components of integrated circuits or systems-on-a-chip, DSPs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and other implementations in silicon wafers and / or other hardware.

[0060] Alternatively or additionally, electronic device 700 may be implemented using any one or combination of electronic circuit systems 710, which may include hardware implemented in conjunction with processing and control circuitry, fixed logic circuit systems, or physical interconnects (e.g., traces or connectors). This electronic circuit system 710 may be implemented using logic circuit systems and / or hardware such as FPGAs or CPLDs to create executable or hardware-based modules (not shown). Although not shown, electronic device 700 may also include system buses, interconnect structures, crossbar switches, or data transfer systems coupling various components within the device. System buses or interconnect structures may include any one or combination of different bus architectures or IP blocks, such as memory buses, memory controllers, peripheral buses, universal serial buses, interconnect nodes, and / or processor or local buses utilizing any of various bus architectures.

[0061] Electronic device 700 also includes one or more memory devices 712 for implementing data storage. Examples of memory devices include random access memory (RAM), non-volatile memory (e.g., read-only memory (ROM), flash memory, EPROM, and EEPROM), and disk storage devices. Any or all memory devices 712 can implement persistent and / or non-transitory storage of information, data, or code, and therefore transient signals or carriers are not included in the general context of this disclosure. For example, memory device 712 provides data storage mechanisms to store device data 704 and other types of data (e.g., user data). Memory device 712 may also store the electronic device's operating system 714, firmware, and / or device applications 716 as instructions, code, or information. These instructions or code can be executed by processor 708 to implement various functions of the electronic device, such as providing a user interface, enabling data access, or managing connectivity to a wireless network. In various aspects, memory device 712 also stores processor-executable code or instructions for providing functions related to complementary 2(N)-bit redundancy for SEU prevention, such as references. Figures 1 to 6The described error detection, error correction, and / or voting logic configuration or reconfiguration.

[0062] like Figure 7 As shown, electronic device 700 may include an audio and / or video processing system 718 for processing audio data and / or transmitting audio and video data to audio system 720 and / or display system 722 (e.g., a video buffer or device screen). Audio system 720 and / or display system 722 may include any means for processing, displaying, and / or otherwise presenting audio, video, graphics, and / or image data. Display data and audio signals may be transmitted to the audio and / or display components via a radio frequency (RF) link, a super video link, HDMI (High Definition Multimedia Interface), a display port, a composite video link, a component video link, a DVI (Digital Video Interface), an analog audio connection, or other similar communication links such as media data port 724. In some embodiments, audio system 720 and / or display system 722 are external or separate components of electronic device 700. Alternatively, display system 722 may be an integrated component of example electronic device 700, such as part of an integrated display with a touch interface.

[0063] In various aspects, any component of electronic device 700 may include or be implemented with a complementary 2(N)-bit redundancy circuit system 118, such as for SEU prevention or for preventing malicious actors from affecting data stored by the electronic device. Alternatively or additionally, electronic device 700 may represent an example embodiment of computer device 102 as described throughout this disclosure. Thus, in some cases, processor 708 is an example of processor 106 (not shown), and / or memory device 712 is an example of computer-readable storage medium 108 (not shown) for storing various data, instructions, or code for implementing a diversity controller or other applications. Thus, the complementary 2(N)-bit redundancy aspect for SEU prevention as described herein may be provided by Figure 7 The electronic device 700 is implemented as a component or module or in combination with said component or module.

[0064] Figure 8 This illustrates an example system-on-chip (SoC) that can implement complementary 2(N)-bit redundancy for SEU prevention. The SoC 800 can be embodied as shown in the reference. Figures 1 to 7 Any computing device 102, user equipment, device, other device, or system of any type described herein, or embodied therein, is configured to implement complementary 2(N)-bit redundancy for SEU prevention. Although reference is made to the chip-based package description, Figure 8The components shown may also be represented as other system or component configurations, such as, but not limited to, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), digital signal processors (DSPs), complex programmable logic devices (CPLDs), system-in-package (SiP), package-in-package (PoP), processing and communication chipsets, communication coprocessors, sensor coprocessors, etc.

[0065] In this example, the SoC 800 includes a communication transceiver 802 and a wireless modem 804, which enable wired or wireless communication of data 806 (e.g., received data, data being received, data scheduled for broadcast, packetized data, etc.). In some aspects, the wireless modem 804 is a multi-mode, multi-band modem or baseband processor configured to communicate according to various communication protocols and / or in different frequency bands—such as those described throughout this disclosure. The wireless modem 804 may include a transceiver interface (not shown) for transmitting coded or modulated signals to the transceiver circuitry.

[0066] Data 806 or other system content may include configuration settings for the system or various components (e.g., voting function or voting logic configuration), media content stored by the system, and / or information associated with the system's users. Media content stored on the on-chip system 800 may include any type of audio, video, and / or image data. The on-chip system 800 also includes one or more data inputs 808, through which any type of data, media content, and / or input can be received, such as user input, user-selectable input (explicit or implicit), or any other type of audio, video, and / or image data received from content and / or data sources. Alternatively or additionally, data inputs 808 may include various data interfaces, which may be implemented as any one or more serial and / or parallel interfaces, wireless interfaces, network interfaces, and any other type of communication interface for enabling communication with other devices or systems.

[0067] The system-on-a-chip 800 includes one or more processor cores 810 that process various computer-executable instructions to control the operation of the system-on-a-chip 800. Alternatively or additionally, the system-on-a-chip 800 may be implemented using any or a combination of hardware, firmware, or fixed logic circuitry implemented in conjunction with processing and control circuitry typically shown at 812. Although not shown, the system-on-a-chip 800 may also include wiring, interconnects, cross switches, or structures that generally couple various components within the system.

[0068] The system-on-chip 800 also includes memory 814 (e.g., computer-readable media), such as one or more memory circuits that implement persistent and / or non-transitory data storage and therefore do not include transient signals or carriers. Examples of memory 814 include RAM, non-transitory memory (e.g., read-only memory (ROM), EPROM, EEPROM, etc.), or flash memory. Memory 814 provides data storage for system data 806, as well as firmware 816, applications 818, and any other types of information and / or data related to operational aspects of the system-on-chip 800. For example, firmware 816 may be held in memory 814 as processor-executable instructions of an operating system (e.g., a real-time OS) and executed on one or more processor cores 810.

[0069] Application 818 may include a system manager, such as any form of control application, software application, signal processing and control module, system-specific native code, abstraction module, or gesture module, etc. Memory 814 may also store system components or utilities for implementing aspects of complementary 2(N)-bit redundancy for SEU prevention, including voting algorithms and / or voting configurations for voting logic. These entities may be embodied as combined or individual components, examples of which are referenced in [reference needed]. Figures 1 to 7 The corresponding entity or function description described in the document.

[0070] In some aspects, the System-on-Chip 800 also includes additional processors or coprocessors to enable other functions, such as a graphics processor 820, an audio processor 822, and an image sensor processor 824. The graphics processor 820 can render graphical content associated with the user interface, operating system, or applications of the System-on-Chip 800. In some cases, the audio processor 822 encodes or decodes audio data and signals, such as audio signals and information associated with voice calls, or encoded audio data for playback. The image sensor processor 824 can be coupled to an image sensor and provides image data processing, video capture, and other visual media conditioning and processing functions.

[0071] The system-on-chip 800 may also include a security processor 826 to support various security, encryption, and cryptographic operations, such as providing secure communication protocols and encrypted data storage. Although not shown, the security processor 826 may include one or more cryptographic engines, cryptographic libraries, hash modules, or random number generators to support the encryption and cryptographic processing of information or communications of the system-on-chip 800 (SoC 800). Alternatively or additionally, the system-on-chip 800 may include a positioning and location engine 828 and a sensor interface 830. Typically, the positioning and location engine 828 can provide positioning or location data by processing signals from a Global Navigation Satellite System (GNSS) and / or other motion or inertial sensor data (e.g., dead reckoning navigation). The sensor interface 830 enables the system-on-chip 800 to receive data from various sensors such as capacitance and motion sensors. In some aspects, any of the components or functional blocks of the SoC800 may include or be implemented with a complementary 2(N) bit redundancy circuit system 118, such as for SEU prevention or for preventing malicious actors from affecting data stored by the electronic device.

[0072] Variant

[0073] Although the above-described devices and methods are described in the context of complementary 2(N)-bit redundancy for SEU prevention in a wireless network with access to one or more base stations, the described apparatus, systems, and methods are not limited and can be applied to other contexts, user equipment deployments, or wireless communication environments.

[0074] Generally, the components, modules, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry systems), manual processing, or any combination thereof. Some operations of the example methods can be described in the general context of executable instructions stored on computer-readable storage memory local and / or remote on a computer processing system, and implementations can include software applications, programs, functions, etc. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, FPGAs, ASICs, ASSPs, SoCs, CPLDs, coprocessors, context hubs, motion coprocessors, sensor coprocessors, etc.

[0075] Some examples are described below:

[0076] Example 1: An integrated circuit includes: an input node for receiving a data value; a first register having an input operably coupled to the input node, the register being configured to store the data value; at least one inverter operably coupled to the input node to provide a complementary data value; a second register having an input operably coupled to the at least one inverter, the second register being configured to store the complementary data value; a multi-bit register having a first input operably coupled to the input node and a second input operably coupled to the at least one inverter, the multi-bit register being configured to store the data value and the complementary data value as separate values; and voting logic including: an output coupled to an output node of the integrated circuit; and a... The voting logic comprises: a first input operably coupled to the output of the first register to receive a first logic value based on the data value stored in the first register; a second input operably coupled to the output of the second register to receive a second logic value based on the complementary data value stored in the second register; a third input coupled to the first output of the multi-bit register to receive a third logic value based on the data value stored in the multi-bit register; and a fourth input coupled to the second output of the multi-bit register to receive a fourth logic value based on the complementary data value stored in the multi-bit register, wherein the voting logic is configured to provide an output data value to the output node of the integrated circuit based on a corresponding set of logic values ​​of at least three of the first, second, third, and fourth logic values.

[0077] Example 2: An integrated circuit as described in Example 1, wherein the at least one inverter operatively coupled to the input node comprises: a first inverter operatively coupled between the input node and the input of the second register; and a second inverter operatively coupled between the input node and the second input of the multi-bit register.

[0078] Example 3: An integrated circuit as described in Example 1, wherein the at least one inverter operatively coupled to the input node includes a first inverter, and the integrated circuit further includes at least one of the following: a second inverter operatively coupled between the output of the second register and the second input of the voting logic; or a third inverter operatively coupled between the second output of the multi-bit register and the fourth input of the voting logic.

[0079] Example 4: An integrated circuit as described in Example 3, wherein at least one of the first inverter, the second inverter, and the third inverter includes an inverting logic gate implemented outside the first register, the second register, and the multi-bit register.

[0080] Example 5: An integrated circuit as described in any one of Examples 1 to 4, wherein the multi-bit register further comprises: a first latch circuit configured to store the data value; a second latch circuit configured to store the complementary data value; and a shared clock circuit operatively coupled to the first latch circuit and the second latch circuit.

[0081] Example 6: An integrated circuit as described in Example 5, wherein: the first latch circuit includes at least one of a first flip-flop or a first 1-bit storage element of the multi-bit register; and the second latch circuit includes at least one of a second flip-flop or a second 1-bit storage element of the multi-bit register.

[0082] Example 7: An integrated circuit as described in any one of Examples 1 to 6, wherein: the voting logic is configured to provide the output data value using a majority voting function based on: a first logic value based on the data value stored in the first register; a second logic value based on the complementary data value stored in the second register; and a third logic value based on the data value stored in the multi-bit register.

[0083] Example 8: An integrated circuit as described in any one of Examples 1 to 6, wherein the voting logic is configured to provide the output data value using a majority voting function based on: a first logic value based on the data value stored in the first register; a second logic value based on the complementary data value stored in the second register; and a fourth logic value based on the complementary data value stored in the multi-bit register.

[0084] Example 9: An integrated circuit as described in any one of Examples 1 to 6, wherein the voting logic is configured to provide the output data value using a majority voting function based on: a first logic value based on the data value stored in the first register; a second logic value based on a non-inverted version of the complementary data value stored in the second register; and a third logic value based on the data value stored in the multi-bit register.

[0085] Example 10: An integrated circuit as described in any one of Examples 1 to 9, wherein: the voting logic is based on a first set of corresponding logic values ​​for which it provides the output data value; and the voting logic is further configured to: detect a single-event upset (SEU) based on at least three of the first logic value, the second logic value, the third logic value, and the fourth logic value; and in response to detecting the SEU, to change the configurable logic of the voting logic to provide the output data value using a second set of corresponding logic values, which is different from the second set of corresponding logic values.

[0086] Example 11: An integrated circuit as described in Example 10, wherein the voting logic further includes corresponding XOR circuits for complementary pairs of the first logic value, the second logic value, the third logic value, and the fourth logic value, the XOR circuits being configured to detect the SEU.

[0087] Example 12: An integrated circuit as described in Example 10 or 11, wherein the voting logic is further configured to implement a triple module redundancy (TMR) mode in response to detecting that the SEU changes the configurable logic of the voting logic, in which the voting logic implements a voting function based on: a first logic value based on the data value stored in the first register; a second logic value based on a non-inverted version of the complementary data value stored in the second register; and a third logic value based on the data value stored in the multi-bit register.

[0088] Example 13: A method for storing data in a complementary multi-bit redundancy circuit, performed by an integrated circuit as described in any one of Examples 1 to 12, the method comprising: receiving a data value at an input of the complementary multi-bit redundancy circuit; storing the data value in a first 1-bit register of the complementary multi-bit redundancy circuit; generating a complementary data value based on the data value via a data inverting circuit system, the complementary data value having a logic state opposite to that of the data value; storing the complementary data value from the data inverting circuit system to a second 1-bit register of the complementary multi-bit redundancy circuit; storing the data value in a first storage element of a multi-bit register of the complementary multi-bit redundancy circuit; storing the complementary data value from the data inverting circuit system to a second storage element of the multi-bit register of the complementary multi-bit redundancy circuit; and generating an output data value based on at least three of the following using voting logic of the complementary multi-bit redundancy circuit: the data value stored in the first 1-bit register, the complementary data value stored in the second 1-bit register, the data value stored in the first storage element of the multi-bit register, and the complementary data value stored in the second storage element of the multi-bit register.

[0089] Example 14: The method of Example 13 further includes: monitoring complementary data value pairs, the complementary data value pairs including one of the data values ​​stored by the first storage element of the first 1-bit register or the multi-bit register, and one of the complementary data values ​​stored by the second storage element of the second 1-bit register and the multi-bit register; detecting a fault in one of the first 1-bit register, the second 1-bit register, the first storage element of the multi-bit register, or the second storage element of the multi-bit register based on the complementary data value pairs; and modifying the voting logic to exclude the faulty 1-bit register or the storage element of the multi-bit register.

[0090] Example 15: The method as described in Example 14, wherein: the voting logic does not use a corresponding or complementary data value of one of the first 1-bit register, the second 1-bit register, the first storage element of the multi-bit register, or the second storage element of the multi-bit register to provide the output data value, and the method further includes: changing the voting logic to include the corresponding or complementary data value of the first 1-bit register, the second 1-bit register, the first storage element of the multi-bit register, or the second storage element of the multi-bit register that the voting logic was not previously used to provide the data value.

Claims

1. An integrated circuit, comprising: Input node (226), the input node (226) is used to receive data values; A first data storage element (206) having an input operatively coupled to the input node, the first data storage element being configured to store the data value; At least one inverter (230) is operatively coupled to the input node to provide complementary data values; A second data storage element (202) having an input operatively coupled to the at least one inverter, the second data storage element being configured to store the complementary data values; A multi-bit data storage element (204) having a first input operatively coupled to the input node and a second input operatively coupled to the at least one inverter, the multi-bit data storage element being configured to store the data value and the complementary data value as separate values; as well as Voting logic (124), the voting logic (124) includes: The output is coupled to the output node (228) of the integrated circuit; The first input of the voting logic is operatively coupled to the output of the first data storage element (206) to receive a first logic value based on the data value stored by the first data storage element; The second input of the voting logic is operatively coupled to the output of the second data storage element (202) to receive a second logic value based on the complementary data value stored by the second data storage element; The third input of the voting logic, coupled to the first output of the multi-bit data storage element (204), receives a third logic value based on the data value stored by the multi-bit data storage element; and The fourth input of the voting logic, coupled to the second output of the multi-bit data storage element (204), receives a fourth logic value based on the complementary data values ​​stored by the multi-bit data storage element. The voting logic is configured to provide output data values ​​to the output node of the integrated circuit based on a first set of logic values, the first set of logic values ​​including at least three of the first logic value, the second logic value, the third logic value, and the fourth logic value.

2. The integrated circuit according to claim 1, wherein, The at least one inverter operatively coupled to the input node includes: A first inverter, operatively coupled between the input node and the input of the second data storage element; and A second inverter is operatively coupled between the input node and the second input of the multi-bit data storage element.

3. The integrated circuit according to claim 1, wherein, The at least one inverter operatively coupled to the input node includes a first inverter, and the integrated circuit further includes at least one of the following: A second inverter, which is operatively coupled between the output of the second data storage element and the second input of the voting logic; and A third inverter is operatively coupled between the second output of the multi-bit data storage element and the fourth input of the voting logic.

4. The integrated circuit according to claim 3, wherein, At least one of the first inverter, the second inverter, and the third inverter includes an inverting logic gate, which is implemented outside the first data storage element, the second data storage element, and the multi-bit data storage element.

5. The integrated circuit according to claim 1, wherein, The multi-bit data storage element further includes: A first latch circuit, configured to store the data value; A second latch circuit, configured to store the complementary data value; and A shared clock logic, which is operatively coupled to the first latch circuit and the second latch circuit.

6. The integrated circuit according to claim 5, wherein: The first latch circuit includes at least one of the first flip-flop of the multi-bit data storage element and the first 1-bit storage element; The second latch circuit includes at least one of the second flip-flop and the second 1-bit storage element of the multi-bit data storage element.

7. The integrated circuit according to claim 1, wherein: The voting logic is configured to provide the output data value using a majority voting function based on the following: The first logical value based on the data value stored by the first data storage element; The second logical value is based on the complementary data values ​​stored by the second data storage element; as well as The third logical value based on the data value stored by the multi-bit data storage element; or The voting logic is configured to provide the output data value using a majority voting function based on the following: The first logical value based on the data value stored by the first data storage element; The second logical value is based on the complementary data values ​​stored by the second data storage element; as well as The fourth logical value is based on the complementary data values ​​stored by the multi-bit data storage element.

8. The integrated circuit according to claim 1, wherein: The voting logic is configured to provide the output data value using a majority voting function based on the following: The first logical value based on the data value stored by the first data storage element; The second logical value is based on the non-inverted version of the complementary data value stored by the second data storage element; as well as The third logical value is based on the data value stored by the multi-bit data storage element.

9. The integrated circuit according to claim 1, wherein: The voting logic is further configured as follows: Single-particle flipping (SEU) is detected based on the first set of logical values; and In response to the detection of the SEU, the configurable logic of the voting logic is changed to provide the output data value using a second set of logic values, the second set of logic values ​​including at least three of the first logic value, the second logic value, the third logic value, and the fourth logic value, the first set of logic values ​​being different from the second set of logic values.

10. The integrated circuit according to claim 9, wherein: The voting logic also includes corresponding XOR circuits for complementary pairs of the first logic value, the second logic value, the third logic value, and the fourth logic value, the XOR circuits being configured to detect the SEU.

11. The integrated circuit according to claim 10, wherein: The voting logic is also configured to change its configurable logic in response to the detection of the SEU to implement a triple module redundancy (TMR) mode, in which the voting logic implements a voting function based on the following: The first logical value based on the data value stored by the first data storage element; The second logical value is based on the non-inverted version of the complementary data value stored by the second data storage element; as well as The third logical value is based on the data value stored by the multi-bit data storage element.

12. The integrated circuit according to any one of claims 1 to 11, wherein, The first data storage element, the second data storage element, or the multi-bit data storage element is implemented as one or more of the following: Latches, bistable latches, set-reset latches (SR latches), master-slave latches, D latches, flip-flops, D flip-flops, T flip-flops, JK flip-flops, master-slave flip-flops, 1-bit registers, multi-bit registers, logic storage units, charge storage units, and clock data storage circuits.

13. A method executed by an integrated circuit, the method comprising: Data values ​​are received at the input of the complementary multi-bit redundancy circuit; The data value is stored in the first 1-bit data storage element of the complementary multi-bit redundancy circuit; A complementary data value is generated based on the data value via a data inversion circuit system. The complementary data value has a logic state that is opposite to the logic state of the data value. The complementary data value is stored from the data inversion circuit system to the second 1-bit data storage element of the complementary multi-bit redundancy circuit; The data value is stored in the first storage element of the multi-bit data storage element of the complementary multi-bit redundancy circuit; The complementary data value is stored from the data inversion circuit system to the second storage element of the multi-bit data storage element of the complementary multi-bit redundancy circuit; as well as The voting logic using the complementary multi-bit redundancy circuit generates output data values ​​based on at least three of the following: the data value stored by the first 1-bit data storage element, the complementary data value stored by the second 1-bit data storage element, the data value stored in the first storage element of the multi-bit data storage element, and the complementary data value stored in the second storage element of the multi-bit data storage element.

14. The method according to claim 13, further comprising: Monitor complementary data value pairs, the complementary data value pairs including: one of the data values ​​stored by the first storage element of the first 1-bit data storage element or the first storage element of the multi-bit data storage element, and one of the complementary data values ​​stored by the second storage element of the second 1-bit data storage element and the second storage element of the multi-bit data storage element; Based on the complementary data value pair, a fault is detected in one of the first 1-bit data storage element, the second 1-bit data storage element, the first storage element of the multi-bit data storage element, or the second storage element of the multi-bit data storage element; and The voting logic is changed to eliminate the faulty 1-bit data storage element or the multi-bit data storage element.

15. The method according to claim 14, wherein, The method further includes the following: A corresponding or complementary data value of one of the first 1-bit data storage element, the second 1-bit data storage element, the first storage element of the multi-bit data storage element, or the second storage element of the multi-bit data storage element is not used by the voting logic to provide the output data value. The voting logic is modified to include the corresponding or complementary data values ​​of the first 1-bit data storage element, the second 1-bit data storage element, the first storage element of the multi-bit data storage element, or the second storage element of the multi-bit data storage element that were not previously used by the voting logic to provide the output data value.

Images