Angle position sensor measuring device

Abstract

The invention discloses an angle position sensor measuring device, comprising a grating encoder, a quadruple frequency circuit, a counter, a crystal oscillator, a CPU, a latch, a motor reducer component, and an angle position sensor. The device is characterized in that the device also comprises a frequency division circuit and a counter latch control circuit, wherein the latch control end of the latch receives a counter latch output signal LOCKOUT of the counter latch control circuit, the count latch input signal LOCKIN output by the CPU is connected to the counter latch control circuit, the counter latch control circuit performs latch control on the latch, and the CPU outputs a clear counter external latch state signal LOCKCLE; the crystal oscillator is connected to the frequency division circuit, and the divided clock signal CLKIN is connected to the count latch control circuit; the latch is connected to the CPU through a data bus, the angle position sensor outputs an external latch signal EDGEIN connected to the CPU, and the CPU outputs a motor control output signal to control the motor reducer component to rotate forward or reverse.

Description

Technical Field

[0001] The invention belongs to aviation instrument testing equipment, and in particular relates to an angle position sensor measuring device. Background Art

[0002] Working principle of the angle position sensor: When the input shaft rocker of the angle position sensor rotates through a certain angle, the internal contact group is disconnected, and the angle position sensor measuring device is used to detect the angle value of the angle input shaft rocker leaving the zero position.

[0003] The function of the angle position sensor measuring device is:

[0004] The output shaft of the motor reducer assembly, the input shaft of the grating encoder and the input shaft of the angle position sensor are located on the same axis, and the output shaft of the motor reducer assembly drives the input shaft of the grating encoder and the input shaft rocker of the angle position sensor to rotate synchronously. The motor reducer assembly drives the angle position sensor to rotate forward from the zero position. When the contact group inside the angle position sensor changes from "on" to "off", the encoder count value is latched; the motor reducer assembly is controlled to drive the angle position sensor to rotate in the opposite direction. After passing the "zero position", when the contact group inside it changes from "on" to "off", the encoder count value is latched again. Calculate the angle value of clockwise rotation from the zero position and the angle value of counterclockwise rotation from the zero position.

[0005] The structure of a current angle position sensor measuring device is shown in Figure 1 , it consists of a grating encoder, a quadruple frequency circuit, a counter, a crystal oscillator, a CPU, a latch, a motor reducer assembly, and an angle position sensor. The orthogonal pulse signal output by the grating encoder is connected to the quadruple frequency circuit, which processes the signal and outputs an up-count pulse and a down-count pulse, which are connected to the counter. The counter is connected to the latch through a data bus, and the counter clear signal CLE of the counter comes from the CPU. The latch control terminal of the latch is connected to the counter latch input signal LOCKIN output by the CPU, and the data output signal after latching by the latch is connected to the CPU through the data bus. The CPU outputs a read signal RD to read the latched data from the data bus. The crystal oscillator is connected to the CPU to provide a clock signal CLK for the system. The CPU outputs a motor control output signal to control the forward or reverse rotation of the motor reducer assembly, and the external latch signal EDGEIN output by the angle position sensor is connected to the CPU.

[0006] Its working principle is: first, the CPU drives the motor reducer assembly, grating encoder and angle position sensor to rotate forward together, and at the same time, the CPU executes the Figure 2In the main program flow, when the counter latch state variable bLockState is 0, the CPU sends a counter latch signal, that is, the CPU pin counter latch input LOCKIN signal connected to the latch is set to 0 to generate a falling edge, and the current count value of the external counter is latched in the latch. After an instruction cycle, the CPU pin counter latch input LOCKIN signal is set to 1. The real-time position of the grating encoder is read from the latch through the read signal RD.

[0007] When the internal contact group of the angle position sensor changes from "on" to "off" or "off" to "on", the external latch signal EDGEIN generates a falling edge or rising edge external interrupt signal on the external interrupt pin of the CPU, and the CPU enters the external interrupt program and executes Figure 2 The interrupt program flow shown. Specific description: After entering the interrupt program, first query whether the main program flow currently allows external latching, that is, query whether the counter latch state variable bLockState is 0. If bLockState is not 0, do not do anything and exit the interrupt program directly. If bLockState is 0, the CPU in the interrupt program sends a counter latch signal, that is, first set the CPU pin counter latch input LOCKIN signal connected to the latch to 0 to generate a falling edge, and latch the current count value of the external counter in the latch. After an instruction cycle, set the CPU pin counter latch input LOCKIN signal to 1 to allow the subsequent main program flow to control the reading of the count value from the latch through the read signal RD. Then set the counter latched flag variable bLockState to 1 in the interrupt program, and then exit the interrupt program.

[0008] In the main program flow, when the query counter latch state variable bLockState is 1, the grating encoder position value latched by the interrupt program is directly read from the latch through the read signal RD. Then the switch state variable EDGEINEW obtained by the CPU pin external latch signal EDGEIN last time in the main loop program is stored in the variable EDGESAVED, and then the current external latch signal EDGEIN state is read from the CPU pin into the variable EDGEINEW. In this way, the variables EDGESAVED and EDGEINEW store the states of the external latch signal EDGEIN that caused the interrupt twice. If the two adjacent states are equal, it means that the external latch signal EDGEIN has not jumped effectively; if they are not equal, it is determined whether the new state EDGEINEW is 0, that is, whether the internal contact group of the angle position sensor has changed from "on" to "off". If the internal contact group of the angle position sensor has changed from "on" to "off", the measurement result is recorded as valid, and the measurement result value is recorded. Finally, the counter latch state variable bLockState is cleared to 0, and this round of main program loop ends.

[0009] The disadvantages are:

[0010] (1) When the output signal of the angle position sensor changes, the counter value is not latched in real time. The latching delay time of the counter value is the CPU's external interrupt response time, the execution time of the judgment statement and the counter latch statement. Therefore, for the same angle position sensor, at the same action time point, when the rotation speed of the driving angle position sensor is different, the measurement results are also different.

[0011] (2) In the system, when the CPU has a higher-level interrupt event to respond to, the delay time affecting the latch counter value is longer, resulting in greater measurement result deviation. Summary of the invention

[0012] The present invention is an angle position sensor measuring device provided to solve the above problems.

[0013] The present invention achieves the above-mentioned purpose through the following technical scheme, including a grating encoder, a quadruple frequency circuit, a counter, a crystal oscillator, a CPU, a latch, a motor reducer assembly, an angle position sensor, and also includes a frequency division circuit and a counter latch control circuit. The latch control end of the latch receives the counter latch output signal LOCKOUT of the counter latch control circuit, and the count latch input signal LOCKIN output by the CPU is connected to the counter latch control circuit, and the latch is latched by the counter latch control circuit. The CPU reads whether there is an external latch state from the counter latch control circuit output by the counter latch control circuit. The CPU outputs a clear counter external latch state signal LOCKCLE, which can clear the counter. The counter of the latch control circuit has been externally latched by the state signal LOCKST; the crystal oscillator is connected to the frequency division circuit on the one hand, and the divided clock signal CLKIN is connected to the counting latch control circuit, and is connected to the CPU on the other hand to provide the clock signal CLK for the main program; the orthogonal pulse signal output by the grating encoder is connected to the quadruple frequency circuit, and the quadruple frequency circuit outputs a pulse signal to the counter after signal processing, and the counter is connected to the latch through a data bus, and the counter clear signal CLE comes from the CPU; the data output signal after latching by the latch is connected to the CPU through the data bus, and the angle position sensor outputs an external latch signal EDGEIN connected to the CPU, and the CPU outputs a motor control output signal to control the forward or reverse rotation of the motor reducer assembly.

[0014] Preferably, when the internal contact group of the angle position sensor changes from "on" to "off" or from "off" to "on", the external latch signal EDGEIN generates a falling edge signal or a rising edge signal.

[0015] Preferably, when the clear counter external latch state signal LOCKCLE is at a low level, the falling edge or rising edge signal of the external latch signal EDGEIN is converted into a low-level valid counter latch output signal LOCKOUT with a cycle width of the CLKIN pin input clock signal, and at the same time, the counter has been externally latched state signal LOCKST is set to a high level; when the clear counter external latch state signal LOCKCLE is at a high level, the counter latch output signal LOCKOUT is prohibited from outputting a low-level pulse, and at the same time, the counter has been externally latched state signal LOSKST is set to a low level.

[0016] Preferably, the counter latch control circuit comprises: 2 D flip-flops, namely a first D flip-flop F1 and a second D flip-flop F2; 5 NOT gates, namely a first NOT gate G1, a second NOT gate G2, a third NOT gate G3, a fourth NOT gate G4 and a fifth NOT gate G5; 5 AND gates, namely a first AND gate G6, a second AND gate G7, a third AND gate G8, a fourth AND gate G9 and a fifth AND gate G10; 2 NOR gates, namely a first NOR gate G11 and a second NOR gate G12;

[0017] The divided clock signal CLKIN is respectively connected to the clock signal input terminal C of the first D flip-flop F1 and the clock signal input terminal C of the second D flip-flop F2, the external latch signal EDGEIN is connected to the trigger signal input terminal D of the first D flip-flop F1, the output terminal Q of the first D flip-flop F1 is respectively connected to the trigger signal input terminal D of the second D flip-flop F2, the input terminal of the second NOT gate G2, the second input terminal of the second AND gate G7, and the second input terminal of the fifth AND gate G10, the output terminal Q of the second D flip-flop F2 is respectively connected to the input terminal of the third NOT gate G3, the third input terminal of the second AND gate G7, and the third input terminal of the fourth AND gate G9; the input terminal of the first NOT gate G1 is connected to the output terminal of the first NOR gate G11, and at the same time serves as the LOCKST signal that the counter has been externally latched;

[0018] The output end of the first NOT gate G1 is connected to the first input end of the first AND gate G6, the first input end of the second AND gate G7, and the second input end of the third AND gate G8 respectively; the output end of the second NOT gate G2 is connected to the second input end of the first AND gate G6 and the second input end of the fourth AND gate G9 respectively; the output end of the third NOT gate G3 is connected to the third input end of the first AND gate G6 and the third input end of the fifth AND gate G10 respectively; the output end of the first AND gate G6 is connected to the first input end of the first NOR gate G11, and the output end of the second AND gate G7 is connected to the second input end of the first NOR gate G11;

[0019] The clear counter external latch state LOCKCLE signal is respectively connected to the third input terminal of the first NOR gate G11 and the input terminal of the fourth NOR gate G4, and the output terminal of the fourth NOR gate G4 is respectively connected to the first input terminal of the third AND gate G8, the first input terminal of the fourth AND gate G9, and the first input terminal of the fifth AND gate G10;

[0020] The counter latch input LOCKIN signal is connected to the input end of the fifth NOT gate G5, and the output end of the fifth NOT gate G5 is connected to the third input end of the third AND gate G8; the output end of the third AND gate G8 is connected to the first input end of the second NOR gate G12, the output end of the fourth AND gate G9 is connected to the second input end of the second NOR gate G12, the output end of the fifth AND gate G10 is connected to the third input end of the second NOR gate G12, and the output end of the second NOR gate G12 is the counter latch output LOCKOUT signal.

[0021] Preferably, the CPU controls the reading of the real-time position of the grating encoder from the data bus through a read signal RD.

[0022] Preferably, the main program flow is:

[0023] S1: Determine the value of the counter latch state signal LOCKST;

[0024] S2: If LOCKST is 0, a counter latch signal is issued, and then the grating encoder position value is read from the latch, and the process goes to step S5;

[0025] S3: If LOCKST is 1, read the grating encoder position value latched by the counter latch control circuit from the latch, and the CPU compares the value of the external latch signal EDGEIN in the previous cycle with the value of the external latch signal EDGEIN currently read. If the two adjacent values ​​are equal, go to step S4; if they are not equal, judge the current state, record the measurement result value if it is 0, and go to step S4 if it is 1;

[0026] S4: The CPU sends a clear counter external latch state signal LOCKCLE to the counter latch control circuit. First, LOCKCLE is set to 1 to clear the external latch state, and then LOCKCLE is set to 0 to allow external latching again.

[0027] S5: End this round of main program loop.

[0028] Preferably, the step S2 of sending a counter latch signal is to first set the CPU pin counter latch input signal LOCKIN connected to the latch to 0 to generate a falling edge, latch the current count value of the external counter in the latch, and then set the count latch input signal LOCKIN to 1 after an interval of a CPU instruction cycle.

[0029] Preferably, the method for comparing the value of EDGEIN in step S3 is that the CPU stores the switch state variable EDGEINEW obtained by the CPU external latch signal EDGEIN in the previous cycle into a temporary variable EDGESAVED, and then the CPU reads the current external latch signal EDGEIN state into the switch state variable EDGEINEW, and compares the values ​​of EDGEINEW and EDGESAVED.

[0030] The beneficial effects of the present invention are:

[0031] The present invention uses the transition edge of the output signal of the angle position sensor to latch the count value in real time, reducing the delay and measurement error caused by the CPU external hardware latching. The output shaft of the motor reducer assembly drives the input shaft of the grating encoder and the rocker of the input shaft of the angle position sensor to rotate synchronously. The motor reducer assembly drives the angle position sensor to rotate forward from the zero position. When the contact group inside the angle position sensor changes from "on" to "off", the count value of the encoder is latched; the motor reducer assembly is controlled to drive the angle position sensor to rotate in the opposite direction. After passing the "zero position", the contact group inside the angle position sensor changes from "on" to "off" again, and the count value of the encoder is latched again. The same action time point reduces the measurement error caused by the different rotation speeds of the driving angle position sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a principle block diagram of a commonly used angle position sensor measurement device.

[0033] Figure 2 This is the main program flow chart of a commonly used angle position sensor measuring device.

[0034] Figure 3 The present invention is a principle block diagram of an angle position sensor measuring device.

[0035] Figure 4 The present invention is a schematic diagram of a counter latch control circuit of an angle position sensor measuring device.

[0036] Figure 5 This is a main program flow chart of an angle position sensor measuring device of the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the embodiments are preferred implementations of the present invention, but the present invention is not limited to the above implementations. Without departing from the essential content of the present invention, any obvious improvements, substitutions or modifications made by ordinary technicians in the field without making creative work are within the scope of protection of the present invention.

[0038] See also Figure 3 , Figure 4 In an angle position sensor measuring device, the orthogonal pulse signal output by the grating encoder is connected to a quadruple frequency circuit, and the quadruple frequency circuit processes the signal and outputs an up-count pulse and a down-count pulse to a counter. The counter is connected to the latch through a data bus, and the counter clear signal CLE of the counter comes from the CPU. The data output signal after latching by the latch is connected to the CPU through the data bus. The CPU outputs a read signal RD to read the latched data from the data bus. The crystal oscillator is connected to the CPU to provide a clock signal CLK for the system. The CPU outputs a motor control output signal to control the forward or reverse rotation of the motor reducer assembly, and the external latch signal EDGEIN output by the angle position sensor is connected to the CPU.

[0039] The components of the angle position sensor also include a frequency division circuit and a counter latch control circuit. The latch control terminal of the latch is connected to the counter latch output signal LOCKOUT of the counter latch control circuit. The counter latch input LOCKIN signal output by the CPU is connected to the counter latch control circuit. The latch is latched by the counter latch control circuit. The CPU reads whether there is an external latch state from the counter external latch state LOCKST signal output by the counter latch control circuit. The CPU outputs a clear counter external latch state LOCKCLE signal, which can clear the counter external latch state LOCKST signal of the counter latch control circuit. The crystal oscillator is connected to the frequency division circuit, and the divided clock signal CLKIN is connected to the counter latch control circuit.

[0040] When the clear counter external latch state signal LOCKCLE signal is at a low level, the falling edge or rising edge signal of the external latch signal EDGEIN is converted into a low-level valid counter latch output signal LOCKOUT with a cycle width of the CLKIN pin input clock signal, and the counter has been externally latched state signal LOCKST is set to a high level at the same time; when the clear counter external latch state signal LOCKCLE signal is at a low level, and the counter latch output signal LOCKOUT is prohibited from being at a low level, the input terminal LOCKIN level state is transmitted to the counter latch output signal LOCKOUT prohibited in real time; when the clear counter external latch state signal LOCKCLE signal is at a high level, the counter latch output signal LOCKOUT is prohibited from outputting a low-level pulse, and the counter has been externally latched state signal LOSKST is set to a low level at the same time.

[0041] When the measuring device runs according to the main program flow:

[0042] First, the CPU drives the motor reducer assembly, grating encoder and angle position sensor to rotate forward together, and the CPU executes the cycle Figure 5In the main program flow, when the counter latch state signal LOCKST output to the CPU pin by the counter latch control circuit is 0, the CPU sends a counter latch signal, that is, the CPU pin counter latch input signal LOCKIN connected to the latch is first set to 0 to generate a falling edge, and the current count value of the external counter is latched in the latch. After an instruction cycle, the CPU pin counter latch input signal LOCKIN is set to 1. The real-time position of the grating encoder is read from the latch through the read signal RD.

[0043] If the counter latch state signal LOCKST output by the counter latch control circuit to the CPU pin is 1, it means that the counter has been latched by the counter latch control circuit, and the grating encoder position value latched by the counter latch control circuit is directly read from the latch through the read signal RD. Then the switch state variable EDGEINEW obtained by the CPU pin external latch signal EDGEIN last time in the main loop program is stored in the variable EDGESAVED, and then the current external latch signal EDGEIN state is read from the CPU pin into the variable EDGEINEW. In this way, the variables EDGESAVED and EDGEINEW store the latch signal EDGEIN states that cause the counter latch control circuit to latch the output twice. If the two adjacent states are equal, it means that the external latch signal EDGEIN has not changed effectively; if they are not equal, it is determined whether the new state EDGEINEW is 0, that is, whether the internal contact group of the angle position sensor has changed from "on" to "off". If the internal contact group of the angle position sensor changes from "on" to "off", the measurement result is recorded as valid, and the measurement result value is recorded. Finally, the CPU sends a clear counter external latch state signal LOCKCLE to the counter latch control circuit, first sets LOCKCLE to 1, clears the external latch state, and then sets LOCKCLE to 0, allowing the external latch again, ending this round of main program loop.

[0044] The input and output signals of the counter latch control circuit are described as follows:

[0045] Input signal:

[0046] 1. CLKIN clock signal, comes from the system clock

[0047] 2. EDGEIN external latch signal comes from the internal contact group of the angle position sensor being measured and is 1 when connected.

[0048] 3. LOCKCLE clears the external latch status of the counter, which comes from the CPU. When it is 1, it clears the external latch and prohibits latching again. It is set to 1 during power-on initialization and set to 0 after initialization is completed.

[0049] 4. LOCKIN counter latch input, comes from CPU, latched on falling edge, high level allows reading, set to 1 during power-on initialization.

[0050] Output signal:

[0051] 1. The LOCKST counter has been externally latched, and the status output is connected to the CPU. When it is 1, it has been latched by the external latch signal, and the CPU is prohibited from repeatedly latching.

[0052] 2. LOCKOUT counter latch output, connected to the latch, latched on the falling edge, high level allows reading.

[0053] The main program flow is described as follows:

[0054] The program cycle executes the tasks of reading the switch status and counter value under test:

[0055] Execution cycle: about 50ms;

[0056] Output:

[0057] 1. Current counter value lxValue;

[0058] 2. Whether the deflection angle value of the switch under test is valid (bResultState);

[0059] 3. The deflection angle value of the switch under test, lxResultValue.

Claims

1. An angle position sensor measuring device, comprising a grating encoder, a quadruple frequency circuit, a counter, a crystal oscillator, a CPU, a latch, a motor reducer assembly, and an angle position sensor, characterized in that: It also includes a frequency division circuit and a counter latch control circuit, the latch control end of the latch receives the counter latch output signal LOCKOUT of the counter latch control circuit, the count latch input signal LOCKIN output by the CPU is connected to the counter latch control circuit, and the latch is latched by the counter latch control circuit. The CPU reads whether there is an external latch state from the counter external latch state signal LOCKST output by the counter latch control circuit, and the CPU outputs a clear counter external latch state signal LOCKCLE, which can clear the counter external latch state signal LOCKST of the counter latch control circuit; the crystal oscillator On the one hand, it is connected to the frequency division circuit, and the divided clock signal CLKIN is connected to the counting latch control circuit, and on the other hand, it is connected to the CPU to provide the clock signal CLK for the main program; the orthogonal pulse signal output by the grating encoder is connected to the quadruple frequency circuit, and the quadruple frequency circuit outputs a pulse signal to the counter after signal processing, and the counter is connected to the latch through a data bus, and the counter clear signal CLE comes from the CPU; the data output signal after latching by the latch is connected to the CPU through the data bus, and the angle position sensor outputs an external latch signal EDGEIN connected to the CPU, and the CPU outputs a motor control output signal to control the forward or reverse rotation of the motor reducer component.

2. An angular position sensor measuring device according to claim 1, characterized in that: When the internal contact group of the angle position sensor changes from “on” to “off” or from “off” to “on”, the external latch signal EDGEIN generates a falling edge or a rising edge signal.

3. The angular position sensor measuring device according to claim 1, characterized in that: When the clear counter external latch state signal LOCKCLE is at a low level, the falling edge or rising edge signal of the external latch signal EDGEIN is converted into a low-level valid counter latch output signal LOCKOUT with a cycle width of the CLKIN pin input clock signal, and at the same time, the counter has been externally latched state signal LOCKST is set to a high level; when the clear counter external latch state signal LOCKCLE is at a high level, the counter latch output signal LOCKOUT is prohibited from outputting a low-level pulse, and at the same time, the counter has been externally latched state signal LOSKST is set to a low level.

4. The angular position sensor measuring device according to claim 1, characterized in that: The counter latch control circuit comprises: 2 D flip-flops, namely a first D flip-flop (F1) and a second D flip-flop (F2); 5 NOT gates, namely a first NOT gate (G1), a second NOT gate (G2), a third NOT gate (G3), a fourth NOT gate (G4) and a fifth NOT gate (G5); 5 AND gates, namely a first AND gate (G6), a second AND gate (G7), a third AND gate (G8), a fourth AND gate (G9) and a fifth AND gate (G10); 2 NOR gates, namely a first NOR gate (G11) and a second NOR gate (G12); The divided clock signal CLKIN is respectively connected to the clock signal input terminal (C) of the first D flip-flop (F1) and the clock signal input terminal (C) of the second D flip-flop (F2); the external latch signal EDGEIN is connected to the trigger signal input terminal (D) of the first D flip-flop (F1); the output terminal (Q) of the first D flip-flop (F1) is respectively connected to the trigger signal input terminal (D) of the second D flip-flop (F2), the input terminal of the second NOT gate (G2), the second input terminal of the second AND gate (G7), and the second input terminal of the fifth AND gate (G10); the output terminal (Q) of the second D flip-flop (F2) is respectively connected to the input terminal of the third NOT gate (G3), the third input terminal of the second AND gate (G7), and the third input terminal of the fourth AND gate (G9); the input terminal of the first NOT gate (G1) is connected to the output terminal of the first NOR gate (G11), and at the same time serves as a LOCKST signal indicating that the counter has been externally latched; The output end of the first NOT gate (G1) is respectively connected to the first input end of the first AND gate (G6), the first input end of the second AND gate (G7), and the second input end of the third AND gate (G8); the output end of the second NOT gate (G2) is respectively connected to the second input end of the first AND gate (G6) and the second input end of the fourth AND gate (G9); the output end of the third NOT gate (G3) is respectively connected to the third input end of the first AND gate (G6) and the third input end of the fifth AND gate (G10); the output end of the first AND gate (G6) is connected to the first input end of the first NOR gate (G11), and the output end of the second AND gate (G7) is connected to the second input end of the first NOR gate (G11); The clear counter external latch state LOCKCLE signal is respectively connected to the third input end of the first NOR gate (G11) and the input end of the fourth NOR gate (G4), and the output end of the fourth NOR gate (G4) is respectively connected to the first input end of the third AND gate (G8), the first input end of the fourth AND gate (G9), and the first input end of the fifth AND gate (G10); The counter latch input LOCKIN signal is connected to the input end of the fifth NOT gate (G5), and the output end of the fifth NOT gate (G5) is connected to the third input end of the third AND gate (G8); the output end of the third AND gate (G8) is connected to the first input end of the second NOR gate (G12), the output end of the fourth AND gate (G9) is connected to the second input end of the second NOR gate (G12), the output end of the fifth AND gate (G10) is connected to the third input end of the second NOR gate (G12), and the output end of the second NOR gate (G12) is the counter latch output LOCKOUT signal.

5. The angular position sensor measuring device according to claim 1, characterized in that: The CPU controls the reading of the real-time position of the grating encoder from the data bus through the read signal RD.

6. The angular position sensor measuring device according to claim 1, characterized in that: The main program flow is: S1: Determine the value of the counter latch state signal LOCKST; S2: If LOCKST is 0, a counter latch signal is issued, and then the grating encoder position value is read from the latch, and the process goes to step S5; S3: If LOCKST is 1, read the grating encoder position value latched by the counter latch control circuit from the latch, and the CPU compares the value of the external latch signal EDGEIN in the previous cycle with the value of the external latch signal EDGEIN currently read. If the two adjacent values ​​are equal, go to step S4; if they are not equal, judge the current state, record the measurement result value if it is 0, and go to step S4 if it is 1; S4: The CPU sends a clear counter external latch state signal LOCKCLE to the counter latch control circuit. First, LOCKCLE is set to 1 to clear the external latch state, and then LOCKCLE is set to 0 to allow external latching again. S5: End this round of main program loop.

7. The angular position sensor measuring device according to claim 6, characterized in that: The step S2 of sending the counter latch signal is to first set the CPU pin counter latch input signal LOCKIN connected to the latch to 0 to generate a falling edge, latch the current count value of the external counter in the latch, and then set the count latch input signal LOCKIN to 1 after an interval of a CPU instruction cycle.

8. The angular position sensor measuring device according to claim 6, characterized in that: The method for comparing the value of EDGEIN in step S3 is that the CPU stores the switch state variable EDGEINEW obtained by the CPU external latch signal EDGEIN in the previous cycle into a temporary variable EDGESAVED, and then the CPU reads the current external latch signal EDGEIN state into the switch state variable EDGEINEW, and compares the values ​​of EDGEINEW and EDGESAVED.

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