A method and apparatus for determining a signature map for chip failure analysis, and an electronic device

Abstract

Embodiments of the present application disclose a method and device for determining an identification map for chip failure analysis, and an electronic device, and relate to the technical field of chip failure analysis. The method is used to determine a failure position in physical failure analysis. The method comprises: if a current metal layer is a metal layer above a specified metal layer, determining a first mapping position corresponding to a first suspected failure position in the current metal layer; zooming in on a region around the first mapping position to obtain a zoomed-in metal layer; collecting an image in a specified window region to obtain a window region image; the specified window region is a local region in the zoomed-in metal layer, and the first mapping position is located in the specified window region; performing image recognition on the window region image to identify a target pattern; and performing identification on the target pattern to obtain an identification map. The present application is suitable for chip failure analysis.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a method, apparatus and electronic device for determining an identification pattern for chip failure analysis. Background Technology

[0002] Typically, after the electrical failure analysis of a chip is performed by the design company, the physical failure analysis is outsourced to a third party. In this outsourcing process, in addition to providing a sample of the failed chip, the third party also needs to provide the coordinates of the suspected failure location (also known as a suspected failure point or probable failure point) within the chip. This coordinates are used to locate the final target location during subsequent physical failure analysis.

[0003] In the process of realizing this invention, the inventors discovered that because the location of the suspected failure location is relatively small in the global layout of the chip, it is not easy to gradually locate the suspected failure location from the top layer of the chip and narrow down the scope to the suspected failure location by relying solely on the coordinates of the suspected failure location during the physical failure analysis of the chip by a third party. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method, apparatus, electronic device, and readable storage medium for determining an identification map for chip failure analysis. During the physical failure analysis of a chip, it is convenient to gradually locate the chip from the top layer down and narrow down the scope to the suspected failure location.

[0005] In a first aspect, embodiments of this application provide a method for determining an identifier map for chip failure analysis. The chip includes at least two metal layers arranged vertically, with a dielectric layer between the different metal layers, and the different metal layers are connected through vias in the dielectric layer. The method for determining the identifier map includes: determining whether the current metal layer is a metal layer above a specified metal layer; if the current metal layer is a metal layer above the specified metal layer, determining a first mapping position corresponding to the first suspected failure location in the current metal layer; the first suspected failure location is obtained in advance through electrical failure analysis; magnifying the area around the first mapping position to obtain a magnified metal layer; acquiring an image within a specified window area to obtain a window area image; the specified window area is a local area in the magnified metal layer, and the first mapping position is located within the specified window area; performing image recognition on the window area image to identify a target graphic; and marking the target graphic to obtain an identifier map.

[0006] According to a specific implementation of an embodiment of this application, determining the first mapping position corresponding to the first suspected failure position in the current metal layer includes: mapping the first suspected failure position onto the current metal layer along a direction perpendicular to the current metal layer to obtain the first mapping position corresponding to the first suspected failure position in the current metal layer.

[0007] According to a specific implementation of this application, the step of magnifying the area surrounding the first mapping position to obtain a magnified metal layer includes: determining the width of the narrowest metal line in the current metal layer; determining a magnification factor based on the width of the narrowest metal line; and magnifying the area surrounding the first mapping position based on the magnification factor to obtain a magnified metal layer.

[0008] According to a specific implementation of this application, determining the magnification factor based on the width of the narrowest metal line includes: determining the magnification factor according to the following formula:

[0009]

[0010] Where F is the magnification factor; W min R1 is the width of the narrowest metal line in the current metal layer, in mm; R2 is the human eye resolution coefficient, ranging from 0.29 to 5 mm; R3 is the ratio of the display size of the target display to the design size of the chip; the target display is a display used for physical failure analysis of the chip.

[0011] According to a specific implementation of an embodiment of this application, the step of performing image recognition on the window region image to identify the target graphic includes: extracting an initial contour line from the image within the window region; extracting feature contour lines in a first direction and / or a second direction from the initial contour line as the target graphic; wherein the first direction and the second direction are perpendicular to each other; or...

[0012] Feature contour lines in directions other than the first and second directions are extracted from the initial contour lines to form the target graphic; wherein the first and second directions are perpendicular to each other; or...

[0013] Feature contour lines in each direction are extracted from the initial contour lines to form the target graphic.

[0014] According to a specific implementation of an embodiment of this application, the step of extracting a feature contour line in a first direction from the initial contour line as a target graphic includes: establishing a first reference line in the current metal layer from the first mapping position along a first direction; determining each metal line in the current metal layer that intersects with the first reference line; and selecting the metal lines among the metal lines that intersect with the first reference line whose line width exceeds a first line width threshold or is less than a second line width threshold as the target graphic; wherein the first line width threshold is greater than the second line width threshold.

[0015] According to a specific implementation of an embodiment of this application, the step of extracting a feature contour line in a second direction from the initial contour line as a target graphic includes: establishing a second reference line in the current metal layer from the first mapping position along the second direction; determining each metal line in the current metal layer that intersects with the second reference line; and selecting the metal lines among the metal lines that intersect with the second reference line whose line width exceeds a third line width threshold or is less than a fourth line width threshold as the target graphic; wherein the third line width threshold is greater than the fourth line width threshold.

[0016] According to a specific implementation of this application, the number of feature contour lines extracted from the initial contour line is two or more; after extracting the feature contour lines from the initial contour line, the method for determining the identifier image further includes: calculating the merge width value of at least two adjacent feature contour lines, wherein the merge width value is the sum of the widths of the at least two adjacent feature contour lines; sorting the merge width values ​​according to their size; and taking at least two feature contour lines corresponding to merge width values ​​that are greater than a preset threshold as the target image.

[0017] According to a specific implementation of this application, the step of extracting feature contour lines in directions other than the first and second directions from the initial contour lines as the target graphic includes: deleting the contour lines in the first and second directions from the initial contour lines, and retaining the remaining contour lines as the target graphic.

[0018] According to a specific implementation of an embodiment of this application, the step of extracting feature contour lines in various directions from the initial contour line as a target graphic includes: deleting contour lines in the first direction and contour lines in the second direction from the initial contour line to obtain remaining contour lines; matching the remaining contour lines with the initial contour line to extract the graphic from the initial contour line that matches the remaining contour lines as the target graphic; wherein, the graphic extracted from the initial contour line that matches the remaining contour lines includes the remaining contour lines and at least one contour line connected to the remaining contour lines.

[0019] According to a specific implementation of an embodiment of this application, marking the target graphic to obtain a marked image includes: highlighting the target graphic to obtain a marked image.

[0020] Secondly, embodiments of this application provide an apparatus for determining an identifier pattern for chip failure analysis, comprising:

[0021] The judgment module is used to determine whether the current metal layer is the metal layer above the specified metal layer;

[0022] The mapping module is used to determine the first mapping position of the first suspected failure position in the current metal layer if the judgment module determines that the current metal layer is the metal layer above the specified metal layer; the first suspected failure position is obtained in advance through electrical failure analysis.

[0023] An amplification module is used to amplify the area around the first mapping position to obtain an amplified metal layer;

[0024] The image acquisition module is used to acquire images within a specified window area to obtain an image of the window area; the specified window area is a local area in the magnified metal layer, and the first mapping position is located within the specified window area;

[0025] The image recognition module is used to perform image recognition on the window area image and identify the target image;

[0026] The identification module is used to identify the target graphic to obtain an identification image.

[0027] According to a specific implementation of an embodiment of this application, the mapping module is specifically used to: map the first suspected failure location onto the current metal layer along a direction perpendicular to the current metal layer, thereby obtaining a first mapped location corresponding to the first suspected failure location in the current metal layer.

[0028] According to a specific implementation of an embodiment of this application, the amplification module is specifically used for: determining the width of the narrowest metal line in the current metal layer; determining the amplification factor based on the width of the narrowest metal line; and amplifying the area around the first mapping position based on the amplification factor to obtain an amplified metal layer.

[0029] According to a specific implementation of an embodiment of this application, the amplification module determines the amplification factor according to the following formula:

[0030]

[0031] Where F is the magnification factor; W minR1 is the width of the narrowest metal line in the current metal layer, in mm; R2 is the human eye resolution coefficient, ranging from 0.29 to 5 mm; R3 is the ratio of the display size of the target display to the design size of the chip; the target display is a display used for physical failure analysis of the chip.

[0032] According to a specific implementation of an embodiment of this application, the image recognition module is specifically used for: extracting an initial contour line from the image within the window area; extracting feature contour lines in a first direction and / or a second direction from the initial contour line as a target image; wherein the first direction and the second direction are perpendicular to each other; or...

[0033] Feature contour lines in directions other than the first and second directions are extracted from the initial contour lines to form the target graphic; wherein the first and second directions are perpendicular to each other; or...

[0034] Feature contour lines in each direction are extracted from the initial contour lines to form the target graphic.

[0035] According to a specific implementation of an embodiment of this application, the graphic recognition module is specifically used for: establishing a first reference line in the current metal layer from the first mapping position along a first direction; determining each metal line in the current metal layer that intersects with the first reference line; and taking the metal lines among the metal lines that intersect with the first reference line whose line width exceeds a first line width threshold or is less than a second line width threshold as target graphics; wherein the first line width threshold is greater than the second line width threshold.

[0036] According to a specific implementation of an embodiment of this application, the graphic recognition module is specifically used for: establishing a second reference line in the current metal layer from the first mapping position along a second direction; determining each metal line in the current metal layer that intersects with the second reference line; and taking the metal lines among the metal lines that intersect with the second reference line whose line width exceeds a third line width threshold or is less than a fourth line width threshold as target graphics; wherein the third line width threshold is greater than the fourth line width threshold.

[0037] According to a specific implementation of this application, the number of feature contour lines extracted from the initial contour line is two or more; the device for determining the identifier image further includes: a filtering module, used to calculate the merge width value of at least two adjacent feature contour lines, wherein the merge width value is the sum of the widths of the at least two adjacent feature contour lines; sort the merge width values ​​according to their size; and take at least two feature contour lines corresponding to merge width values ​​that are greater than a preset threshold as target graphics.

[0038] According to a specific implementation of an embodiment of this application, the graphic recognition module is specifically used to: delete the contour lines in the first direction and the contour lines in the second direction of the initial contour lines, and retain the remaining contour lines as the target graphic.

[0039] According to a specific implementation of an embodiment of this application, the graphic recognition module is specifically used for: deleting the contour lines in the first direction and the contour lines in the second direction from the initial contour lines to obtain the remaining contour lines; matching the remaining contour lines with the initial contour lines to extract the graphic in the initial contour lines that matches the remaining contour lines as the target graphic; wherein, the graphic extracted from the initial contour lines that matches the remaining contour lines includes the remaining contour lines and at least one contour line connected to the remaining contour lines.

[0040] According to a specific implementation of an embodiment of this application, the marking module is specifically used to: highlight the target graphic to obtain a marking image.

[0041] Thirdly, embodiments of this application also provide an electronic device, the electronic device comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the identification diagram determination method described in any of the foregoing embodiments.

[0042] Fourthly, embodiments of this application also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the identification map determination method described in any of the foregoing embodiments.

[0043] In the embodiments of the method, apparatus, electronic device, and readable storage medium for determining the identification map for chip failure analysis, this application determines whether the current metal layer is the metal layer above the lowest metal layer for physical failure analysis of the first suspected failure location on the chip. If so, the first mapping position corresponding to the first suspected failure location in the current metal layer is determined, and the area around the first mapping position is magnified to obtain the magnified metal layer. By acquiring and recognizing the image within a specified window area, the target graphic is identified and marked to obtain the identification map. Thus, after providing the window area image with the marked map to a third party, the third party can use the identification map on the metal layer as a reference graphic during the physical peeling process of the chip, facilitating gradual positioning from the top layer of the chip downwards and narrowing the scope to the first suspected failure location. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a flowchart illustrating the first embodiment of the method for determining the identification pattern used in chip failure analysis according to this application.

[0046] Figure 2 This is a magnified schematic diagram of the area surrounding the first mapping position in one embodiment;

[0047] Figure 3 This is a schematic diagram illustrating the process of performing image recognition on a window area image to identify a target graphic in one embodiment of this application;

[0048] Figure 4a This is a schematic diagram of a first reference line established from a first mapping position along a first direction within a window area, passing through multiple metal lines in one embodiment.

[0049] Figure 4b The image shows the source. Figure 4a The target graphic defined within the shown window area;

[0050] Figure 5 This is a partial flowchart illustrating a second embodiment of the method for determining the identifier map used in chip failure analysis according to this application.

[0051] Figure 6a This is a schematic diagram of a second reference line established from a first mapping position along a second direction within a window area, passing through multiple metal lines in one embodiment.

[0052] Figure 6b The image shows the source. Figure 6a The target graphic defined within the shown window area;

[0053] Figure 7 This is a partial flowchart illustrating a third embodiment of the method for determining the identifier map used in chip failure analysis according to this application.

[0054] Figure 8a This is a schematic diagram of the initial outline within the window area in one embodiment;

[0055] Figure 8b The image shown is in Figure 8a The schematic diagram of the target graphic obtained by deleting the first and second direction contour lines in the initial contour lines within the window area shown, and retaining the remaining contour lines;

[0056] Figure 9 This is a flowchart illustrating the fourth embodiment of the method for determining the identification map for chip failure analysis in this application.

[0057] Figure 10a The figure shown is a schematic diagram of the initial outline within the window area in one embodiment;

[0058] Figure 10b In order to Figure 10a The diagram shows the target graphic identified by searching for graphics in various directions within the window area shown.

[0059] Figure 11 This is a schematic block diagram of a first embodiment of the device for determining the identification pattern for chip failure analysis according to this application;

[0060] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0061] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0062] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0063] This application provides a method, apparatus, electronic device, and storage medium for determining an identification map for chip failure analysis. By using image recognition, an identification map is determined near the location corresponding to the suspected failure location on at least one metal layer above the lowest metal layer used for physical failure analysis of the suspected failure location. In this way, during the physical failure analysis of the chip, the identification map on the metal layer facilitates gradual positioning from the upper layer of the chip downwards and narrows down the scope to the suspected failure location.

[0064] Figure 1 This is a flowchart illustrating a first embodiment of the method for determining the identification pattern used in chip failure analysis according to this application. The chip includes at least two metal layers, which are arranged vertically, with a dielectric layer between them. The different metal layers are connected through vias in the dielectric layer. See also... Figure 1 The method for determining the identification map for chip failure analysis in this embodiment includes steps S10-S20.

[0065] S10. Determine whether the current metal layer is the metal layer above the specified metal layer.

[0066] The designated metal layer is the lowest metal layer pre-determined for physical failure analysis of the first suspected failure location on the chip. The designated metal layer can be the metal layer containing the first suspected failure location, or a metal layer below the first suspected failure location. The first suspected failure location is a suspected failure location pre-determined based on electrical failure analysis.

[0067] The first suspected failure location may involve multiple suspected metal layers.

[0068] In some embodiments, the bottommost metal layer among the plurality of suspected metal layers can be identified as the designated metal layer. For example, if the first suspected failure location involves three metal layers from bottom to top: the third metal layer, the fourth metal layer, and the fifth metal layer, then the third metal layer is identified as the designated metal layer.

[0069] In some cases, the multiple suspected metal layers involved in the first suspected failure location determined by electrical failure analysis may not be accurate enough. Therefore, in other embodiments, the metal layer below the bottommost metal layer among the multiple suspected metal layers can be identified as the designated metal layer. For example, if the first suspected failure location involves three metal layers from bottom to top: the 3rd metal layer, the 4th metal layer, and the 5th metal layer, then the metal layer below the 3rd metal layer, i.e., the 2nd metal layer, is identified as the designated metal layer.

[0070] The first suspected failure location may also involve only one suspected metal layer.

[0071] In some embodiments, the suspected metal layer may be identified as the designated metal layer. For example, if the first suspected failure location involves only one metal layer: the fifth metal layer, then the fifth metal layer may be identified as the designated metal layer.

[0072] As mentioned earlier, the suspected metal layer involved in the first suspected failure location determined by electrical failure analysis may not be accurate enough. Therefore, in some embodiments, a metal layer below the suspected metal layer can be identified as the designated metal layer. For example, if the first suspected failure location involves only one metal layer: the 5th metal layer, then a metal layer below the 5th metal layer, i.e., the 4th metal layer, can be identified as the designated metal layer.

[0073] Electrical failure analysis can be performed using scan diagnostic analysis or bitmap analysis.

[0074] By scanning and diagnostic analysis, the locations of potential failure points and their corresponding circuit layouts can be obtained. Specifically, numerous registers reserved during the design phase are used to form effective links. By inputting different types of test vectors (patterns) during testing, the results are compared and analyzed to identify potential link problems, providing information such as the coordinates of defective points in the chip.

[0075] Bitmap analysis targets various high-density memory cell devices, employing testing algorithms and logic. Based on pass or fail results, the locations of the memory cell array are marked, forming a corresponding bitmap.

[0076] Accordingly, the first suspected failure location can be the location of a suspected netpath defect or the location of a suspected memory cell failure point (Fail Bit).

[0077] The current metal layer is the metal layer on which the identification map is currently determined. It can be the topmost metal layer or any metal layer between the specified metal layer and the topmost metal layer.

[0078] If the current metal layer is the metal layer above the specified metal layer, then step S12 is executed.

[0079] S12. Determine the first mapping position corresponding to the first suspected failure position in the current metal layer.

[0080] The first suspected failure location is determined by electrical failure analysis. Electrical failure analysis can provide the coordinates of the first suspected failure location within the chip, thereby defining the metal layer in which the first suspected failure location is located and its relative position within that metal layer.

[0081] The first suspected failure location can be mapped to the current metal layer to determine the first mapped location corresponding to the first suspected failure location in the current metal layer.

[0082] S14. Magnify the area around the first mapping position to obtain the magnified metal layer.

[0083] In the current metal layer, the area around the first mapping position can be magnified to obtain a magnified metal layer so that the metal lines or patterns on the metal layer can be observed with the naked eye on the display.

[0084] Figure 2 This is a magnified schematic diagram of the area surrounding the first mapping position in one embodiment. Figure 2 The dashed box in the global graph represents the area surrounding the first mapping location.

[0085] S16. Acquire the image within the specified window area to obtain the window area image.

[0086] The specified window area is designated as the inspection window. Existing image processing techniques can be used to extract the outline of the graphic within the window area in order to identify the target graphic.

[0087] The designated window area is a local region within the magnified metal layer, and the first mapping position is located within this designated window area. In one example, the size of the designated window area may be the same as the size of the display window of the monitor, facilitating the display of the magnified metal layer on the monitor. This monitor may be a monitor used by a third party when performing physical failure analysis on the chip.

[0088] S18. Perform image recognition on the window area image to identify the target graphic.

[0089] Target patterns are auxiliary graphics used in physical failure analysis to facilitate the gradual localization from the top layer of the chip downwards, narrowing down the scope to the suspected failure location. Target patterns are easily observable graphics; they can be specific shapes or patterns, thicker metal lines, or denser combinations of metal lines, etc.

[0090] Existing image recognition technologies can be used to perform image recognition on the window area image in order to identify the target graphic.

[0091] S20. Mark the target graphic to obtain the marked image.

[0092] After the target graphic is identified using image recognition technology, it can be labeled to enhance its visual effect and facilitate quick identification.

[0093] The identification method can be text labeling, or the target graphic can be given a specified color, such as a striking red color, or the target graphic can be highlighted, and so on.

[0094] In this embodiment, the identification pattern can be determined layer by layer from the top down for each metal layer above the specified metal layer. In other embodiments, the identification pattern can be determined only for a portion of the metal layers above the specified metal layer.

[0095] In this embodiment, it is determined whether the current metal layer is the metal layer above the lowest metal layer used for physical failure analysis of the first suspected failure location on the chip. If so, the first mapping position corresponding to the first suspected failure location in the current metal layer is determined, and the area around the first mapping position is magnified to obtain the magnified metal layer. By acquiring and recognizing the image within a specified window area, the target graphic is identified and marked to obtain the marking image. In this way, after providing the window area image with the marking image to a third party, the third party can use the marking image on the metal layer as a reference graphic during the physical peeling process of the chip, which facilitates gradual positioning from the top layer of the chip downwards and narrows down the scope to the first suspected failure location.

[0096] In some embodiments, determining the first mapping position corresponding to the first suspected failure location in the current metal layer (step S12) may include: mapping the first suspected failure location onto the current metal layer along a direction perpendicular to the current metal layer (or perpendicular to the substrate in the chip) to obtain the first mapping position corresponding to the first suspected failure location in the current metal layer.

[0097] The first suspected failure location can be marked as a rectangular or square area, with the coordinates of its two opposite corners denoted as (x1, y1) and (x2, y2) respectively. The coordinate system corresponding to the coordinates of the two opposite corners is a Cartesian coordinate system parallel to the substrate of the chip.

[0098] In one example, the first suspected failure location is mapped onto the current metal layer along a direction perpendicular to the current metal layer to obtain the first mapped position corresponding to the first suspected failure location in the current metal layer. This may include: mapping the first original coordinates of the first suspected failure location in the chip (such as the lower left corner coordinates (x1, y1)) onto the current metal layer along a direction perpendicular to the current metal layer to obtain the first mapped coordinates of the first suspected failure location on the current metal layer; the first mapped coordinates are the first mapped position corresponding to the first suspected failure location in the current metal layer.

[0099] In another example, the first suspected failure location is mapped onto the current metal layer along a direction perpendicular to the current metal layer to obtain the first mapped position corresponding to the first suspected failure location in the current metal layer. This can include: mapping the second original coordinates of the first suspected failure location in the chip (such as the upper right corner coordinates (x2, y2)) onto the current metal layer along a direction perpendicular to the current metal layer to obtain the second mapped coordinates of the first suspected failure location on the current metal layer; the second mapped coordinates are the second mapped position corresponding to the second suspected failure location in the current metal layer.

[0100] In another example, mapping the first suspected failure location onto the current metal layer along a direction perpendicular to the current metal layer to obtain the first mapped position corresponding to the first suspected failure location in the current metal layer can include: mapping the first original coordinates (e.g., the lower left corner coordinates (x1, y1)) and the second original coordinates (e.g., the upper right corner coordinates (x2, y2)) of the first suspected failure location in the chip onto the current metal layer along a direction perpendicular to the current metal layer to obtain the first mapped coordinates and the second mapped coordinates of the first suspected failure location on the current metal layer; the first mapped coordinates are the first mapped position corresponding to the first suspected failure location in the current metal layer; the second mapped coordinates are the second mapped position corresponding to the second suspected failure location in the current metal layer; the first mapped position and the second mapped position together define the position corresponding to the first suspected failure location in the current metal layer.

[0101] In the first two examples, the first suspected failure location can be locally mapped to the current metal layer. In the third example, the first suspected failure location can be mapped entirely to the current metal layer, making the first mapped location in the current metal layer a physical region with a larger area, which is easier to observe.

[0102] In some embodiments, in the current metal layer, the area surrounding the first mapping position is magnified to obtain a magnified metal layer (step S14), which may include:

[0103] S140. Determine the width of the narrowest metal line in the current metal layer.

[0104] The width of the narrowest metal line in the current metal layer can be obtained by querying the PDK (Process Design Kit).

[0105] S141. Determine the magnification factor based on the width of the narrowest metal line.

[0106] The magnification can be determined using the following formula:

[0107]

[0108] Where F is the magnification factor; W min R1 is the width of the narrowest metal line in the current metal layer, in mm; R2 is the human eye resolution coefficient, ranging from 0.29 to 5 mm; R3 is the ratio of the display size of the target display to the design size of the chip.

[0109] In one example, R1 is 1 mm; in another, R1 is 2 mm; and in yet another, R1 is 3 mm.

[0110] The target display's size can be either the width or the height of the chip's design dimensions, both measured in millimeters (mm). The target display is used for physical failure analysis of the chip, such as a display used by the wafer manufacturer or a third party.

[0111] S142. Based on the magnification factor, the area around the first mapping position is magnified to obtain the magnified metal layer.

[0112] The center of the first mapping position can be used as the magnification center point, and magnification can be performed according to the magnification factor to obtain the magnified metal layer.

[0113] See Figure 3 In some embodiments, graphics with vertical features within a specified window area can be searched to identify the target graphic. Specifically, the image recognition of the window area image to identify the target graphic (step S18) may include:

[0114] S180a, Extract the initial contour lines from the image within the window area.

[0115] The initial outline can be the layout design outline within the window area. The image within the window area can be first grayscaled, and then the initial outline can be extracted from the grayscaled image.

[0116] S181a. Extract the feature contour line in the first direction from the initial contour line as the target graphic.

[0117] The feature contour line is visually distinct from the surrounding contour lines, such as being thicker or having multiple adjacent contour lines more densely packed. The first direction is vertical, or approximately vertical. The approximately vertical direction can be a direction with a deviation from the vertical direction of more than 0 degrees and less than 15 degrees.

[0118] In one example, extracting a feature contour line in a first direction from the initial contour line as a target graphic (S181a) may include: establishing a first reference line in the current metal layer from a first mapping position along the first direction; determining each metal line in the current metal layer that intersects with the first reference line; and selecting the metal lines among the metal lines that intersect with the first reference line whose line width exceeds a first line width threshold or is less than a second line width threshold as the target graphic; wherein the first line width threshold is greater than the second line width threshold.

[0119] The first linewidth threshold may include the sum of the average width value of each metal line intersecting with the first reference line and N times the root mean square deviation; the second linewidth threshold may include the difference between the average width value of each metal line intersecting with the first reference line and N times the root mean square deviation; the value of N ranges from [0.5, 6], and in one example, the value of N is 3; the root mean square deviation is the root mean square deviation of the width values ​​of each metal line intersecting with the first reference line.

[0120] Figure 4a The diagram shows a first reference line established from a first mapping position along a first direction within a window area, passing through multiple metal lines. Figure 4b The image shows the source. Figure 4a The target graphic defined within the shown window area, that is... Figure 4a The five adjacent thin metal lines within the dashed box are used as the target graphic.

[0121] In other embodiments, the first linewidth threshold may also be a predetermined multiple of the average width value of the metal lines intersecting the first reference line, such as 1.2 times or 1.5 times. Correspondingly, the second linewidth threshold may also be a predetermined multiple of the average width value of the metal lines intersecting the first reference line, such as 0.8 times or 0.6 times.

[0122] The number of feature contour lines extracted from the initial contour line may be more than two. When too many feature contour lines are extracted from the initial contour line, the recognition accuracy of the target graphic may be reduced. Therefore, feature contour lines with more obvious features can be selected from a large number of feature contour lines as the target graphic. In one example, after extracting feature contour lines from the initial contour line, the method for determining the identifier image further includes: calculating the merged width value of at least two adjacent feature contour lines, where the merged width value is the sum of the widths of the at least two adjacent feature contour lines; sorting the merged width values ​​by size; and selecting at least two feature contour lines corresponding to merged width values ​​greater than a preset threshold as the target graphic.

[0123] Figure 5 This is a partial flowchart illustrating a second embodiment of the method for determining the identifier pattern for chip failure analysis according to this application. The method for determining the identifier pattern for chip failure analysis in this embodiment is similar to... Figure 1 The first implementation shown is basically the same, except that in this implementation, when searching for graphics within the window area, graphics with horizontal features within the window area can be searched to identify the target graphic. Specifically, the step of performing image recognition on the window area image to identify the target graphic (step S18) may include:

[0124] S180b: Extract the initial contour lines from the image within the window area;

[0125] In this embodiment, the extraction of the initial contour line in the image within the window area can be referred to the relevant description in step S180a of the above embodiment.

[0126] S181b: Extract the feature contour line in the second direction from the initial contour line as the target graphic; wherein, the second direction is the horizontal direction.

[0127] In one example, extracting a feature contour line in the second direction from the initial contour line as a target graphic (S181b) may include: establishing a second reference line in the current metal layer from the first mapping position along the second direction; determining each metal line in the current metal layer that intersects with the second reference line; and selecting the metal lines among the metal lines that intersect with the second reference line whose line width exceeds a third line width threshold or is less than a fourth line width threshold as the target graphic; wherein the third line width threshold is greater than the fourth line width threshold.

[0128] The third linewidth threshold may include: the sum of the average width value of each metal line intersecting with the second reference line and N times the root mean square deviation; the fourth linewidth threshold may include: the difference between the average width value of each metal line intersecting with the second reference line and N times the root mean square deviation; the value of N is in the range of [0.5, 6], and the root mean square deviation is the root mean square deviation of the width values ​​of each metal line intersecting with the second reference line.

[0129] In this embodiment, the method of extracting the horizontal feature contour lines from the initial contour lines is basically the same as the method of extracting the vertical feature contour lines in the previous embodiment.

[0130] Figure 6a The diagram shows a second reference line established from the first mapping position along the second direction within the window area, passing through multiple metal lines. Figure 6b The image shows the source. Figure 6a The target graphic defined within the shown window area, that is... Figure 6a The metal line with the largest medium width is used as the target graphic.

[0131] In the two embodiments described above, graphics with vertical or horizontal features within the window area are searched separately to identify the target graphic. In other embodiments, graphics with both vertical and horizontal features within the window area can be searched together to identify the target graphic. Target graphics identified in this way have more obvious visual characteristics compared to target graphics that only exhibit vertical or horizontal features.

[0132] Figure 7 This is a partial flowchart illustrating a third embodiment of the method for determining the identifier pattern for chip failure analysis according to this application. The method for determining the identifier pattern for chip failure analysis in this embodiment is similar to... Figure 1 The first implementation shown is basically the same, except that in this implementation, when searching for graphics within the window area, graphics with non-vertical and non-horizontal features within the window area can be searched to identify the target graphic. Specifically, the step of performing image recognition on the window area image to identify the target graphic (step S18) may include:

[0133] S180c: Extract the initial contour lines from the image within the window area.

[0134] In this embodiment, the extraction of the initial contour line in the image within the window area can be referred to the relevant description in step S180a of the above embodiment.

[0135] S181c: Extract feature contour lines from the initial contour lines in directions other than the first and second directions, and use them as the target graphic.

[0136] The first direction and the second direction are perpendicular to each other; the first direction is vertical or approximately vertical.

[0137] Specifically, in this step, the contour lines in the first and second directions of the initial contour lines can be deleted, leaving the remaining contour lines as the target graphic. Figure 8a The image shown is a schematic diagram of the initial outline within the window area in one embodiment. Figure 8b The image shown is in Figure 8a The schematic diagram of the target graphic obtained by deleting the first and second direction contour lines from the initial contour lines within the window area shown, and retaining the remaining contour lines.

[0138] Most metal traces in a chip layout can have a first direction and a second direction. The target pattern identified in this embodiment differs from the direction of most traces in the layout, making it easier to identify.

[0139] Figure 9This is a flowchart illustrating the fourth embodiment of the method for determining the identifier pattern for chip failure analysis according to this application. The method for determining the identifier pattern for chip failure analysis in this embodiment is similar to... Figure 1 The first implementation shown is basically the same, except that in this implementation, when searching for graphics within the window area, graphics in all directions within the window area can be searched to identify the target graphic. Specifically, the step of performing image recognition on the window area image to identify the target graphic (step S18) may include:

[0140] S180d: Extract the initial contour lines from the image within the window area.

[0141] In this embodiment, the extraction of the initial contour line in the image within the window area can be referred to the relevant description in step S180a of the above embodiment.

[0142] S181d: Extract feature contour lines in each direction from the initial contour lines to form the target graphic.

[0143] The target graphic identified in this way can have a continuous outline, and the pattern features of the graphic composed of different metal lines are more obvious and easier to identify.

[0144] In one example, the following steps can be used to extract feature contour lines in various directions from the initial contour lines, which can then be used as the target graphic:

[0145] Delete the contour lines in the first and second directions from the initial contour lines to obtain the remaining contour lines.

[0146] The remaining contour lines are matched with the initial contour lines, and the graphic that matches the remaining contour lines in the initial contour lines is extracted as the target graphic.

[0147] The graphic extracted from the initial contour line that matches the remaining contour line includes the remaining contour line and at least one contour line connected to the remaining contour line.

[0148] Figure 10a The image shown is a schematic diagram of the initial outline within the window area in one embodiment. Figure 10b The image shown is in the context of... Figure 10a The diagram shows the target graphic identified by searching for graphics in various directions within the window area shown.

[0149] Figure 11 This is a schematic block diagram of a first embodiment of the device for determining the identification pattern for chip failure analysis according to this application. The chip includes at least two metal layers, which are disposed one above the other, with a dielectric layer between them. The different metal layers are connected through vias in the dielectric layer. See also... Figure 11 The identification device 1 for chip failure analysis in this embodiment may include: a judgment module 10, a mapping module 12, a magnification module 14, an image acquisition module 16, a pattern recognition module 18, and an identification module 20; wherein, the judgment module 10 is used to determine whether the current metal layer is a metal layer above a specified metal layer; the specified metal layer is a pre-determined lowest metal layer used for physical failure analysis of the first suspected failure location on the chip; the mapping module 12 is used to determine the first suspected failure location on the current metal layer if the judgment module 10 determines that the current metal layer is a metal layer above the specified metal layer. The first mapping position in the metal layer; the first suspected failure position is obtained in advance through electrical failure analysis; the magnification module 14 is used to magnify the area around the first mapping position to obtain the magnified metal layer; the image acquisition module 16 is used to acquire the image within a specified window area to obtain the window area image; the specified window area is a local area in the magnified metal layer, and the first mapping position is located within the specified window area; the image recognition module 18 is used to perform image recognition on the window area image to identify the target image; the identification module 20 is used to identify the target image to obtain the identification image.

[0150] The apparatus described in the above embodiments can be used to perform... Figure 1 The technical solutions of the methods and implementations shown are similar in principle and technical effect, and will not be described again here.

[0151] In one embodiment, the mapping module 12 is specifically used to: map the first suspected failure location onto the current metal layer along a direction perpendicular to the current metal layer, thereby obtaining a first mapped position corresponding to the first suspected failure location in the current metal layer. More specific mapping methods can be found in the relevant descriptions in the foregoing method embodiments, and will not be repeated here.

[0152] In one embodiment, the amplification module 14 is specifically used for: determining the width of the narrowest metal line in the current metal layer; determining a magnification factor based on the width of the narrowest metal line; and magnifying the area surrounding the first mapping position based on the magnification factor to obtain an amplified metal layer. More specific amplification methods can be found in the relevant descriptions in the foregoing method embodiments, and will not be repeated here.

[0153] In one embodiment, the amplification module 14 determines the amplification factor according to the following formula:

[0154]

[0155] Where F is the magnification factor; W minR1 is the width of the narrowest metal line in the current metal layer, in mm; R2 is the human eye resolution coefficient, ranging from 0.29 to 5 mm; R3 is the ratio of the display size of the target display to the design size of the chip; the target display is a display used for physical failure analysis of the chip.

[0156] In one embodiment, the image recognition module 18 is specifically configured to: extract an initial contour line from the image within the window area; extract feature contour lines in a first direction and / or a second direction from the initial contour line as a target image; wherein the first direction and the second direction are perpendicular to each other; or, extract feature contour lines in directions other than the first and second directions from the initial contour line as a target image; wherein the first direction and the second direction are perpendicular to each other; or,

[0157] Feature contour lines in each direction are extracted from the initial contour lines to form the target graphic.

[0158] For a more detailed process of identifying the target graphic from the initial contour lines, please refer to the relevant description in the foregoing method implementation.

[0159] In one embodiment, the pattern recognition module 18 is specifically configured to: establish a first reference line in the current metal layer from the first mapping position along a first direction; determine each metal line in the current metal layer that intersects with the first reference line; and take the metal lines among the metal lines that intersect with the first reference line whose line width exceeds a first line width threshold or is less than a second line width threshold as target patterns; wherein the first line width threshold is greater than the second line width threshold.

[0160] The process of determining the target graphic from the first mapping position along the first direction can be found in the relevant description in the foregoing method implementation. Figure 4a The diagram shows a first reference line established from the first mapping position along the first direction within the window area, passing through multiple metal lines. Figure 4b The image shown is the target graphic determined from the window area, that is... Figure 4a The five adjacent thin metal lines within the dashed box are used as the target graphic.

[0161] In one embodiment, the pattern recognition module 18 is specifically configured to: establish a second reference line in the current metal layer from the first mapping position along a second direction; determine each metal line in the current metal layer that intersects with the second reference line; and take the metal lines among the metal lines that intersect with the second reference line whose line width exceeds a third line width threshold or is less than a fourth line width threshold as target patterns; wherein the third line width threshold is greater than the fourth line width threshold.

[0162] The process of determining the target graphic from the first mapping position along the second direction can be found in the relevant description in the foregoing method implementation. Figure 6a The diagram shows a second reference line established from the first mapping position along the second direction within the window area, passing through multiple metal lines. Figure 6b The image shown is the target graphic determined from the window area, that is... Figure 6a The metal line with the largest medium width is used as the target graphic.

[0163] The number of feature contour lines extracted from the initial contour line may be more than two. When the number of feature contour lines extracted from the initial contour line is too large, it may reduce the recognition of the target graphic. Therefore, feature contour lines with more obvious features can be selected from a large number of feature contour lines as the target graphic.

[0164] In one embodiment, the number of feature contour lines extracted from the initial contour line is two or more; the device for determining the identifier image further includes: a filtering module, used to calculate the merge width value of at least two adjacent feature contour lines, the merge width value being the sum of the widths of the at least two adjacent feature contour lines; sorting the merge width values ​​according to their size; and using at least two feature contour lines corresponding to merge width values ​​that are greater than a preset threshold as target graphics.

[0165] In one embodiment, the graphic recognition module 18 is specifically used to: delete the contour lines in the first direction and the second direction from the initial contour lines, and retain the remaining contour lines as the target graphic. Figure 8 shows a schematic diagram of the target graphic obtained after deleting the contour lines in the first direction and the second direction from the initial contour lines within a window area and retaining the remaining contour lines.

[0166] In one embodiment, the graphic recognition module 18 is specifically used to: delete the contour lines in the first direction and the contour lines in the second direction from the initial contour lines to obtain the remaining contour lines; match the remaining contour lines with the initial contour lines to extract the graphic from the initial contour lines that matches the remaining contour lines as the target graphic; wherein, the graphic extracted from the initial contour lines that matches the remaining contour lines includes the remaining contour lines and at least one contour line connected to the remaining contour lines.

[0167] This method can also be described as identifying the target graphic by searching for and recognizing graphics in various directions within a window area. Figure 10 shows a schematic diagram of the target graphic identified by searching for and recognizing graphics in various directions within a window area. The target graphic identified in this way can have a continuous outline, and the pattern features of graphics composed of different metal lines are more obvious and easier to identify.

[0168] In one embodiment, the identification module 20 is specifically used to: highlight the target graphic to obtain an identification image.

[0169] After the target graphic is identified using image recognition technology, it can be labeled to enhance its visual effect and facilitate quick identification.

[0170] The labeling method can be text labeling, or the target graphic can be given a specified color, such as a striking red, or the target graphic can be highlighted, etc.

[0171] The apparatus described in the above embodiments can be used to execute the technical solutions of the above method embodiments. The implementation principle and technical effects are similar, and will not be repeated here.

[0172] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, as shown below. Figure 12 As shown, the electronic device may include: a housing 61, a processor 62, a memory 63, a circuit board 64, and a power supply circuit 65. The circuit board 64 is disposed inside the space enclosed by the housing 61, and the processor 62 and the memory 63 are disposed on the circuit board 64. The power supply circuit 65 is used to supply power to the various circuits or devices of the electronic device. The memory 63 is used to store executable program code. The processor 62 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 63, and executes the method for determining the identification map for chip failure analysis provided in any of the foregoing embodiments. Therefore, it can also achieve the corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0173] The aforementioned electronic devices exist in various forms, including but not limited to desktop computers and servers. Servers consist of components such as processors, hard drives, memory, and system buses. While servers share a similar architecture with general-purpose computers, they require higher levels of processing power, stability, reliability, security, scalability, and manageability due to the need to provide highly reliable services.

[0174] Accordingly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the method for determining the identification map for chip failure analysis provided in any of the foregoing embodiments. Therefore, it can also achieve the corresponding technical effects, as has been described in detail above and will not be repeated here.

[0175] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0176] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0177] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0178] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0179] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0180] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for determining an identification pattern for chip failure analysis, characterized in that, include: Determine whether the current metal layer is the metal layer above the specified metal layer; If the current metal layer is the metal layer above the specified metal layer, then determine the first mapping position corresponding to the first suspected failure position in the current metal layer; The first suspected failure location was obtained in advance through electrical failure analysis; The area surrounding the first mapping position is magnified to obtain the magnified metal layer; An image is acquired within a specified window area to obtain a window area image; the specified window area is a local area in the magnified metal layer, and the first mapping position is located within the specified window area; Image recognition is performed on the window area image to identify the target graphic; The target graphic is labeled to obtain a labeled image; The step of performing image recognition on the window region image to identify the target graphic includes: Extract the initial contour lines from the image within the window area; Feature contour lines in a first direction and / or a second direction are extracted from the initial contour lines to form the target graphic; wherein the first direction and the second direction are perpendicular to each other; or... Feature contour lines in directions other than the first and second directions are extracted from the initial contour lines to form the target graphic; wherein the first and second directions are perpendicular to each other; or... Feature contour lines in each direction are extracted from the initial contour lines to form the target graphic. Extracting the feature contour line in the first direction from the initial contour line as the target graphic includes: In the current metal layer, a first reference line is established from the first mapping position along a first direction; Identify the metal lines in the current metal layer that intersect with the first reference line; Among the metal lines that intersect with the first reference line, the metal lines whose line width exceeds the first line width threshold or is less than the second line width threshold are taken as the target pattern; the first line width threshold is greater than the second line width threshold. Extracting the feature contour line in the second direction from the initial contour line as the target graphic includes: In the current metal layer, a second reference line is established from the first mapping position along the second direction; Identify the metal lines in the current metal layer that intersect with the second reference line; Among the metal lines that intersect with the second reference line, the metal lines whose line width exceeds the third line width threshold or is less than the fourth line width threshold are taken as the target pattern; the third line width threshold is greater than the fourth line width threshold.

2. The method for determining the identification pattern for chip failure analysis according to claim 1, characterized in that, Determining the first mapped position corresponding to the first suspected failure location in the current metal layer includes: The first suspected failure location is mapped onto the current metal layer along a direction perpendicular to the current metal layer to obtain the first mapped location of the first suspected failure location in the current metal layer.

3. The method for determining the identification pattern for chip failure analysis according to claim 1, characterized in that, The process of magnifying the area surrounding the first mapping position to obtain a magnified metal layer includes: Determine the width of the narrowest metal line in the current metal layer; The magnification factor is determined based on the width of the narrowest metal line. Based on the magnification factor, the area surrounding the first mapping position is magnified to obtain an magnified metal layer.

4. The method for determining the identification pattern for chip failure analysis according to claim 3, characterized in that, Determining the magnification factor based on the width of the narrowest metal line includes: determining the magnification factor according to the following formula: F= ； Where F is the magnification factor; This represents the width of the narrowest metal line in the current metal layer, in mm. The human eye resolution coefficient has a value range of 0.29-5mm. The ratio of the display size of the target display to the design size of the chip; the target display is a display used for physical failure analysis of the chip.

5. The method for determining the identification pattern for chip failure analysis according to claim 1, characterized in that, The number of feature contour lines extracted from the initial contour line in the first direction and / or the second direction is two or more; After extracting the feature contour lines from the initial contour lines, the method for determining the identifier map further includes: Calculate the combined width value of at least two adjacent feature contour lines, where the combined width value is the sum of the widths of the at least two adjacent feature contour lines; Sort the merged width values ​​by size; At least two feature contour lines corresponding to merge width values ​​greater than a preset threshold are selected as the target graphic.

6. The method for determining the identification pattern for chip failure analysis according to claim 1, characterized in that, The step of extracting feature contour lines in directions other than the first and second directions from the initial contour lines as the target graphic includes: Delete the contour lines in the first direction and the second direction from the initial contour lines, and retain the remaining contour lines as the target graphic.

7. The method for determining the identification pattern for chip failure analysis according to claim 1, characterized in that, The step of extracting feature contour lines in various directions from the initial contour lines as the target graphic includes: Delete the contour lines in the first direction and the contour lines in the second direction from the initial contour lines to obtain the remaining contour lines. The remaining contour lines are matched with the initial contour lines, and the graphic that matches the remaining contour lines in the initial contour lines is extracted as the target graphic; wherein, the graphic that matches the remaining contour lines extracted from the initial contour lines includes the remaining contour lines and at least one contour line connected to the remaining contour lines.

8. The method for determining the identification pattern for chip failure analysis according to claim 1, characterized in that, The step of marking the target graphic to obtain a marked image includes: highlighting the target graphic to obtain a marked image.

9. A device for determining an identification pattern for chip failure analysis, characterized in that, include: The judgment module is used to determine whether the current metal layer is the metal layer above the specified metal layer; The mapping module is used to determine the first mapping position of the first suspected failure position in the current metal layer if the judgment module determines that the current metal layer is the metal layer above the specified metal layer; The first suspected failure location was obtained in advance through electrical failure analysis; An amplification module is used to amplify the area around the first mapping position to obtain an amplified metal layer; The image acquisition module is used to acquire images within a specified window area to obtain an image of the window area; the specified window area is a local area in the magnified metal layer, and the first mapping position is located within the specified window area; The image recognition module is used to perform image recognition on the window area image and identify the target image; The identification module is used to identify the target graphic to obtain an identification image; Specifically, the image recognition module is used for: Extract the initial contour lines from the image within the window area; Feature contour lines in a first direction and / or a second direction are extracted from the initial contour lines to form the target graphic; wherein the first direction and the second direction are perpendicular to each other; or... Feature contour lines in directions other than the first and second directions are extracted from the initial contour lines to form the target graphic; wherein the first and second directions are perpendicular to each other; or... Feature contour lines in each direction are extracted from the initial contour lines to form the target graphic. The image recognition module is specifically used for: In the current metal layer, a first reference line is established from the first mapping position along a first direction; Identify the metal lines in the current metal layer that intersect with the first reference line; Among the metal lines that intersect with the first reference line, the metal lines whose line width exceeds the first line width threshold or is less than the second line width threshold are taken as the target pattern; the first line width threshold is greater than the second line width threshold. The image recognition module is specifically used for: In the current metal layer, a second reference line is established from the first mapping position along the second direction; Identify the metal lines in the current metal layer that intersect with the second reference line; Among the metal lines that intersect with the second reference line, the metal lines whose line width exceeds the third line width threshold or is less than the fourth line width threshold are taken as the target pattern; the third line width threshold is greater than the fourth line width threshold.

10. The apparatus for determining the identification pattern for chip failure analysis according to claim 9, characterized in that, The mapping module is specifically used to: map the first suspected failure location onto the current metal layer along a direction perpendicular to the current metal layer, thereby obtaining the first mapped location corresponding to the first suspected failure location in the current metal layer.

11. The apparatus for determining the identification pattern for chip failure analysis according to claim 9, characterized in that, The amplification module is specifically used for: Determine the width of the narrowest metal line in the current metal layer; The magnification factor is determined based on the width of the narrowest metal line. Based on the magnification factor, the area surrounding the first mapping position is magnified to obtain an magnified metal layer.

12. The apparatus for determining the identification pattern for chip failure analysis according to claim 11, characterized in that, The amplification module determines the amplification factor according to the following formula: F= ； Where F is the magnification factor; This represents the width of the narrowest metal line in the current metal layer, in mm. The human eye resolution coefficient has a value range of 0.29-5mm. The ratio of the display size of the target display to the design size of the chip; the target display is a display used for physical failure analysis of the chip.

13. The apparatus for determining the identification pattern for chip failure analysis according to claim 9, characterized in that, The number of feature contour lines extracted from the initial contour line in the first direction and / or the second direction is two or more; The device for determining the identification image further includes: A filtering module is used to calculate the combined width value of at least two adjacent feature contour lines, wherein the combined width value is the sum of the widths of the at least two adjacent feature contour lines; Sort the merged width values ​​by size; At least two feature contour lines corresponding to merge width values ​​greater than a preset threshold are selected as the target graphic.

14. The apparatus for determining the identification pattern for chip failure analysis according to claim 9, characterized in that, The graphic recognition module is specifically used to: delete the contour lines in the first direction and the second direction in the initial contour lines, and retain the remaining contour lines as the target graphic.

15. The apparatus for determining the identification pattern for chip failure analysis according to claim 9, characterized in that, The image recognition module is specifically used for: Delete the contour lines in the first direction and the contour lines in the second direction from the initial contour lines to obtain the remaining contour lines. The remaining contour lines are matched with the initial contour lines, and the graphic that matches the remaining contour lines in the initial contour lines is extracted as the target graphic; wherein, the graphic that matches the remaining contour lines extracted from the initial contour lines includes the remaining contour lines and at least one contour line connected to the remaining contour lines.

16. The apparatus for determining the identification pattern for chip failure analysis according to claim 9, characterized in that, The identification module is specifically used to: highlight the target graphic to obtain an identification image.

17. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the identification diagram determination method according to any one of claims 1-8.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the method for determining the identifier image as described in any one of claims 1-8.

Images