Power supply circuit

Abstract

The power supply circuit of the embodiment includes: a first transistor whose on / off state is controlled according to a control signal supplied to its gate, and which outputs an output voltage that follows a predetermined voltage; a second transistor whose current path is connected at one end to an input terminal supplying the power supply voltage and at the other end to one end of a resistor, and which outputs the predetermined voltage according to the control signal; and an amplifier circuit that amplifies the voltage difference between a reference voltage and the predetermined voltage input through the other end of the resistor, and outputs it as the control signal.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-155264 (filed on September 24, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to power supply circuits. Background Technology

[0003] The power supply circuit has the following overvoltage clamping function: by clamping the output voltage when a large surge voltage is generated, it prevents excessive voltage from being applied to subsequent circuit components. Summary of the Invention

[0004] The implementation provides a power supply circuit capable of clamping the output voltage at high speed when a large surge voltage is generated.

[0005] The power supply circuit of the embodiment includes: a first transistor whose on / off state is controlled according to a control signal supplied to its gate, and which outputs an output voltage that follows a predetermined voltage; a second transistor whose current path is connected at one end to an input terminal supplying the power supply voltage and at the other end to one end of a resistor, and which outputs the predetermined voltage according to the control signal; and an amplifier circuit that amplifies the voltage difference between a reference voltage and the predetermined voltage input through the other end of the resistor, and outputs it as the control signal. Attached Figure Description

[0006] Figure 1 This is a circuit diagram illustrating an example of the power supply circuit according to the first embodiment.

[0007] Figure 2 This is a circuit diagram illustrating an example of the power supply circuit according to the second embodiment. Detailed Implementation

[0008] The embodiments will now be described with reference to the accompanying drawings.

[0009] (First Embodiment)

[0010] Figure 1 This is a circuit diagram illustrating an example of the power supply circuit according to the first embodiment.

[0011] The power supply circuit of this embodiment includes a voltage source So1, NMOS transistors (hereinafter referred to as transistors) T1, T2, T3, an amplifier circuit Amp1, resistors R1, R2, R3, and capacitor C1.

[0012] The negative terminal of voltage source So1 is connected to the reference potential point, generating a power supply voltage Vin at the positive terminal. The power supply voltage Vin from voltage source So1 is supplied to the drains of transistors T1 and T2 and capacitor C1 via the input terminal IN of the power supply circuit.

[0013] The source of transistor T1, which constitutes the main switch, is connected to the output terminal OUT of the power supply circuit. A load (not shown, such as a circuit component) is connected to the output terminal OUT. A control signal Vgate is applied to the gate of transistor T1. This control signal Vgate controls whether the output Vout is supplied from the power supply circuit to the load or the supply to the output Vout is stopped. The control signal Vgate is output from amplifier circuit Amp1.

[0014] Transistor T1, through a source follower structure, outputs Vout, which tracks a predetermined voltage Vs (described later). Transistor T1 is turned on by a high-level (hereinafter referred to as H-level) control signal Vgate, supplying Vout based on the power supply voltage Vin to the load. It is turned off by a low-level (hereinafter referred to as L-level) control signal Vgate, ceasing the supply of Vout based on the power supply voltage Vin to the load.

[0015] Transistor T2 is connected in parallel with transistor T1. The drain of transistor T2 is connected to the positive terminal of the power supply So1. The source of transistor T2 is connected to one end of resistor R1. The other end of resistor R1 is connected to one end of resistor R2. The other end of resistor R2 is connected to a reference potential. A control signal Vgate, output from amplifier circuit Amp1, is applied to the gate of transistor T2, and a voltage Vs controlled by the control signal Vgate is output from the source.

[0016] The voltage Vs is divided by resistors R1 and R2 and supplied to the inverting input terminal of amplifier circuit Amp1. The reference voltage VREF is supplied to the non-inverting input terminal of amplifier circuit Amp1. The output terminal of amplifier circuit Amp1 is connected to the gate of transistor T1, the gate of transistor T2, and the drain of transistor T3.

[0017] The amplifier circuit Amp1 amplifies the voltage difference between the reference voltage VREF supplied to the non-inverting input terminal and the voltage supplied to the inverting input terminal, and outputs it as the control signal Vgate.

[0018] The source of transistor T2 outputs a voltage Vs corresponding to the control signal Vgate. Through a source follower structure, the source of transistor T1 outputs Vout in a manner that follows the voltage Vs, i.e., the output Vout is clamped to the voltage Vs.

[0019] One end of capacitor C1 is connected to the positive input terminal of voltage source So1 via input terminal IN. The other end of capacitor C1 is connected to one end of resistor R3. The other end of resistor R3 is connected to a reference potential point.

[0020] The gate of transistor T3 is connected to the node between capacitor C1 and resistor R3. The source of transistor T3 is connected to the reference potential. When the power supply voltage Vin rises sharply, it is supplied to the gate of transistor T3 through capacitor C1, and transistor T3 turns on. This pulls down the control signal Vgate, clamping the output Vout.

[0021] Thus, this embodiment is configured as follows: transistor T2 feeds back the voltage Vs generated based on the power supply voltage Vin from the power supply voltage So1 to the amplifier circuit Amp1 according to the control signal Vgate.

[0022] Therefore, the power supply circuit of this embodiment can immediately control the control signal Vgate according to the power supply voltage Vin when a large surge voltage is generated, thus enabling high-speed response.

[0023] Furthermore, the power supply circuit in this embodiment does not provide feedback to the output Vout, so it is not affected by the current flowing in transistor T1. Therefore, it is easy to ensure the phase margin of amplifier circuit Amp1.

[0024] Furthermore, in this embodiment, transistor T1, through its source follower structure, enables the output Vout to be approximately equal to the voltage Vs. That is, by fixing the voltage Vs using amplifier circuit Amp1 and transistor T2, the output Vout can also be fixed to the voltage Vs, thus clamping the output Vout to the voltage Vs when the power supply voltage Vin generates a large surge voltage.

[0025] Furthermore, this embodiment includes: a capacitor C1 connected to a voltage source So1 via an input terminal IN; and a transistor T3, one end of whose current path is connected to the output terminal of the amplifier circuit Amp1, the other end connected to a reference potential point, and its gate connected to the capacitor C1. Thus, when a large surge voltage is generated by the power supply voltage Vin, the transistor T3 is turned on via the capacitor C1, pulling down the control signal Vgate, thereby clamping the output Vout at high speed.

[0026] Therefore, the power supply circuit according to this embodiment can clamp the output voltage at high speed when a large surge voltage is generated.

[0027] (Second Implementation)

[0028] Next, the second embodiment will be described.

[0029] Figure 2 This is a circuit diagram illustrating an example of the power supply circuit according to the second embodiment. Furthermore, in Figure 2 China and Figure 1 The same constituent elements are assigned the same label and their descriptions are omitted.

[0030] The power supply circuit configuration of this embodiment is as follows: the amplifier circuit Amp1 of the first embodiment is replaced by the amplifier circuit Amp2 and the NMOS transistor T4, and a charge pump circuit CP, a PMOS transistor T5, and an NMOS transistor T6 are added.

[0031] A node between resistors R1 and R2 is connected to the non-inverting input terminal of amplifier circuit Amp2. The reference voltage VREF is input to the inverting input terminal of amplifier circuit Amp2. The output terminal of amplifier circuit Amp2 is connected to the gate of transistor T4.

[0032] The drain of transistor T4 is connected to the gates of transistors T1 and T2, and its source is connected to the reference potential. The on / off state of transistor T4 is controlled by the output of amplifier circuit Amp2. When a large surge voltage is generated, a high-level signal (H-level) is input from amplifier circuit Amp2 to the gate of transistor T4, turning on transistor T4 and pulling down the control signal Vgate.

[0033] In this embodiment, the control signal Vgate is generated by the charge pump circuit CP and transistors T5 and T6. For transistor T1 to conduct, the control signal Vgate needs to be a voltage higher than the supply voltage Vin. The supply voltage Vin is supplied to the charge pump circuit CP. The charge pump circuit CP uses the supply voltage Vin to generate and output a voltage higher than Vin.

[0034] A current path for transistors T5 and T6 is connected in series between the output terminal of the charge pump circuit CP and the reference potential point. Specifically, the source of transistor T5 is connected to the output of the charge pump circuit CP, and its drain is connected to the gate of transistor T1, where an output control signal is provided. Similarly, the drain of transistor T6 is connected to the gate of transistor T1, and its source is connected to the reference potential point, where an output control signal is provided.

[0035] When the output control signal is at level H, transistor T5 is off, transistor T6 is on, the control signal Vgate becomes level L, and transistor T1 is off. That is, when an output control signal of level H is supplied to the gates of transistors T5 and T6, the supply of output Vout to the load is stopped. In other words, according to the output control signal of level H, the main switch is in the OFF state.

[0036] When the output control signal is at level L, transistor T5 is turned on, transistor T6 is turned off, and the control signal Vgate becomes level H through the output of the charge pump circuit CP, turning transistor T1 on. That is, when the level L output control signal is supplied to the gates of transistors T5 and T6, the output Vout is supplied to the load. In other words, according to the level L output control signal, the main switch is in the ON state.

[0037] In this embodiment, the configuration is the same as in the first embodiment: transistor T2 feeds back voltage Vs generated based on power supply voltage Vin from voltage source So1 to amplifier circuit Amp1 according to control signal Vgate.

[0038] Therefore, the power supply circuit of this embodiment can, in the same manner as the first embodiment, immediately control the control signal Vgate according to the power supply voltage Vin when a large surge voltage is generated, thus enabling high-speed response.

[0039] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A power supply circuit, comprising: The first transistor is turned on and off according to the control signal supplied to the gate, and the output voltage follows a predetermined voltage. The second transistor has one end of its current path connected to the input terminal supplying the power supply voltage, and the other end connected to one end of a resistor, and outputs the predetermined voltage according to the control signal; An amplifier circuit that amplifies the voltage difference between a reference voltage and a predetermined voltage input through the other end of the resistor, and outputs it as the control signal. The third transistor has one end of its current path connected to the output terminal of the amplifier circuit and the other end connected to a reference potential point, and is switched on and off according to the gate voltage; and A capacitor is connected between the input terminal of the power supply voltage and the gate of the third transistor.

2. A power supply circuit, comprising: The first transistor is turned on and off according to the control signal supplied to the gate, and the output voltage follows a predetermined voltage. The second transistor has one end of its current path connected to the input terminal of the power supply voltage and the other end connected to one end of a resistor, and outputs the predetermined voltage according to the control signal. A charge pump circuit that is input to the power supply voltage and generates and outputs a voltage higher than the power supply voltage. The fourth transistor outputs the output of the charge pump circuit as the control signal, based on the output control signal. The fifth transistor outputs the output of the reference potential point as the control signal according to the output control signal; The sixth transistor has one end of its current path connected to the node between the fourth and fifth transistors, and the other end connected to the reference potential point, and is turned on and off according to the gate voltage; as well as A capacitor is connected between the input terminal of the power supply voltage and the gate of the sixth transistor.

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