A multi-channel DDS signal source

Abstract

This invention discloses a multi-channel DDS signal source, comprising: an FPGA, a clock chip, a clock fan-out chip, and multiple DDS signal channels; wherein, each DDS signal channel includes: a DDS chip, a balun, a low-pass filter, a variable attenuator, a fixed attenuator, an amplifier, and an analog switch connected in sequence; the clock chip provides a sampling clock for each DDS chip and a reference clock for the FPGA; the clock fan-out chip provides a SYNC_IN signal for each DDS chip; the FPGA monitors the SYNC_SMP_ERR signal of each DDS chip, and if a SYNC_SMP_ERR signal is detected to be high, the delay value of each DDS chip receiving the SYNC_IN signal is dynamically adjusted; the attenuation value of each variable attenuator is controlled according to a preset amplitude curve within the passband; therefore, this invention not only improves the synchronization accuracy of the signal channels, but also achieves stepped attenuation of amplitude while ensuring output flatness.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, and in particular to a multi-channel DDS signal source. Background Technology

[0002] Direct Digital Synthesizers (DDS) offer advantages such as digital control and adjustment of output signal frequency, phase, and amplitude, high output frequency resolution, and fast frequency change, making them widely applicable in fields such as communications, radar, and ultrasound. However, as the required bandwidth of the intermediate frequency (IF) signal output by DDS increases, the control design of DDS synchronization accuracy and passband flatness presents significant challenges. Summary of the Invention

[0003] This invention provides a multi-channel DDS signal source that not only improves the synchronization accuracy of the signal channels, but also achieves amplitude step attenuation while ensuring output flatness.

[0004] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0005] A multi-channel DDS signal source includes: an FPGA, a clock chip, a clock fan-out chip, and multiple DDS signal channels; wherein,

[0006] The DDS signal channel includes: a DDS chip, a balun, a low-pass filter, a variable attenuator, a fixed attenuator, an amplifier, and an analog switch connected in sequence;

[0007] The clock chip is used to provide a sampling clock for the DDS chip of each DDS signal channel and a reference clock for the FPGA;

[0008] The clock fan-out chip is used to provide a SYNC_IN signal to the DDS chip for each of the DDS signal channels;

[0009] The FPGA is connected to the DDS chip, controllable attenuator, and analog switch of each DDS signal channel, respectively, to monitor the SYNC_SMP_ERR signal of each DDS chip. If a high level SYNC_SMP_ERR signal is detected, the delay value of each DDS chip receiving the SYNC_IN signal is dynamically adjusted. The attenuation value of each variable attenuator is controlled according to a preset passband amplitude curve. And, according to the set number of channels, the corresponding number of analog switches are controlled to turn on their respective DDS signal channels.

[0010] In one specific implementation, the trace lengths from the clock chip to the sampling clock input pin of the DDS chip in each of the DDS signal channels are equal; the trace lengths from the clock fan-out chip to the SYNC_IN signal input pin of the DDS chip in each of the DDS signal channels are also equal.

[0011] In one specific implementation, the trace lengths of the FPGA connected to the I / O_RESET pins of the DDS chips in each DDS signal channel are equal, the trace lengths of the FPGA connected to the SYNC_CLK pins of the DDS chips in each DDS signal channel are equal, the trace lengths of the FPGA connected to the I / O_UPDATE pins of the DDS chips in each DDS signal channel are equal, and the trace lengths of the FPGA connected to the PROFILE pins of the DDS chips in each DDS signal channel are equal.

[0012] In one specific implementation, the FPGA is configured to output an I / O_RESET signal, an I / O_UPDATE signal, and a PROFILE signal through a programmable input / output unit; and, on the falling edge of the SYNC_CLK signal, to output the I / O_UPDATE signal to the I / O_UPDATE pin of the DDS chip, and / or to output the PROFILE signal to the PROFILE pin of the DDS chip.

[0013] In one specific implementation, the signal input of the clock fan-out chip is provided by a signal output from the SYNC_OUT pin of the DDS chip.

[0014] In one specific implementation, the variable attenuator provides adjustable attenuation steps of 0.5 dB.

[0015] In one specific implementation, the FPGA is configured to control the operation of the clock chip and each DDS chip according to the program loaded thereon.

[0016] In one specific implementation, the FPGA is connected to a FLASH module and a DDR3 module; wherein, the FLASH module is used to store the FPGA's program; and the DDR3 module is used to cache the FPGA's running data.

[0017] In one specific embodiment, the multi-channel DDS signal source of the present invention further includes: a digital power supply module and an analog power supply module; wherein, the digital power supply module is used to provide power to the FPGA, the FLASH module and the DDR3 module; the analog power supply module is used to provide power to the clock chip, the DDS chip in each DDS signal channel, the variable attenuator, the amplifier and the analog switch.

[0018] In one specific implementation, the FPGA is configured with a network interface or a serial interface for interacting with a host computer.

[0019] Thus, the multi-channel DDS signal source provided in this embodiment of the invention can not only improve the synchronization accuracy of the signal channels, but also achieve the step attenuation function of amplitude while ensuring the flatness of the output. Attached image description:

[0020] Figure 1 A schematic diagram of the architecture of a multi-channel DDS signal source provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram showing the connection between the FPGA, clock chip, clock fan-out chip, and multiple DDS chips provided in an embodiment of the present invention. Detailed Implementation

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. However, this should not be construed as limiting the scope of the present invention to the following embodiments; all technologies implemented based on the content of the present invention fall within the scope of the present invention.

[0023] like Figure 1 and Figure 2 As shown, this invention provides a multi-channel DDS signal source, which includes: an FPGA, a clock chip, a clock fan-out chip, and multiple DDS signal channels; wherein,

[0024] The DDS signal channel includes: a DDS chip, a balun, a low-pass filter, a variable attenuator, a fixed attenuator, an amplifier, and an analog switch connected in sequence;

[0025] The clock chip is used to provide a sampling clock for the DDS chip of each DDS signal channel and a reference clock for the FPGA;

[0026] The clock fan-out chip is used to provide a SYNC_IN signal to the DDS chip for each of the DDS signal channels;

[0027] The FPGA is connected to the DDS chip, controllable attenuator, and analog switch of each DDS signal channel, respectively, to monitor the SYNC_SMP_ERR signal of each DDS chip. If a high level SYNC_SMP_ERR signal is detected, the delay value of each DDS chip receiving the SYNC_IN signal is dynamically adjusted. The attenuation value of each variable attenuator is controlled according to a preset passband amplitude curve. And, according to the set number of channels, the corresponding number of analog switches are controlled to turn on their respective DDS signal channels.

[0028] In this invention, the DDS chip used is AD9910, a direct digital frequency synthesizer (DDS) with a built-in 14-bit DAC, supporting sampling rates up to 1 GSPS, with a tuning resolution of ~0.23 Hz at 1 GSPS sampling rate. Simultaneously, users can program the internal control registers of AD9910 via the serial I / O port to control the AD9910. AD9910 integrates static RAM, supporting various combinations of frequency, phase, and / or amplitude modulation. Furthermore, AD9910's built-in high-speed parallel data input port can achieve direct modulation of frequency, phase, amplitude, or poles to support more advanced modulation functions.

[0029] In this invention, the DDS chip is monitored to determine whether it has received the SYNC_IN signal normally. If the SYNC_SMP_ERR signal is high or unstable, the synchronous reception delay value of the chip needs to be dynamically adjusted to ensure that the input meets the setup and hold time.

[0030] To ensure synchronization between DDS signal channels at the hardware level, the hardware requires that the trace lengths from the clock chip to the sampling clock input pin of each DDS signal channel's DDS chip be equal; the trace lengths from the clock fan-out chip to the SYNC_IN signal input pin of each DDS signal channel's DDS chip be equal; the trace lengths from the FPGA to the I / O_RESET pin of each DDS signal channel's DDS chip be equal; the trace lengths from the FPGA to the SYNC_CLK pin of each DDS signal channel's DDS chip be equal; the trace lengths from the FPGA to the I / O_UPDATE pin of each DDS signal channel's DDS chip be equal; and the trace lengths from the FPGA to the PROFILE pin of each DDS signal channel's DDS chip be equal.

[0031] To ensure synchronization between DDS signal channels from a software perspective, considering that when the DDS signal source is working, the FPGA may not meet the setup and hold time requirements after changing the corresponding state by issuing PROFILE and I / O_UPDATE signals, thus affecting the synchronization between DDS signal channels, the FPGA is configured to output I / O_RESET, I / O_UPDATE, and PROFILE signals through a programmable input / output unit. In this way, the FPGA can fine-tune the signals in 78ps steps through its internal programmable input / output unit (IOB). At the same time, to ensure synchronization stability, the impedance matching between the FPGA and AD9910 must be very good, and the overshoot and undershoot must not exceed the TTL misjudgment level.

[0032] Furthermore, on the falling edge of the SYNC_CLK signal, the I / O_UPDATE signal is output to the I / O_UPDATE pin of the DDS chip, and / or the PROFILE signal is output to the PROFILE pin of the DDS chip, thereby ensuring that the setup and hold time is fully satisfied when the FPGA outputs all PROFILE signals and I / O_UPDATE signals and the rising edge of the SYNC clock signal of each DDS chip.

[0033] Regarding the flatness of the DDS signal generated by the DDS signal channel, the amplitude curve throughout the entire passband was pre-planned through preliminary testing. Later, an algorithm was used to control the variable attenuator at different frequency points to prevent attenuation parameters, thus ensuring output flatness. This allows for stepped amplitude attenuation while maintaining output flatness. Furthermore, the variable attenuator provides 0.5dB adjustable attenuation steps, which, combined with the fixed attenuator, enables a maximum attenuation of -30dB.

[0034] Specifically, the clock chip used is the HMC7044. An external reference clock or an on-board temperature-compensated crystal oscillator can be input to the HMC7044 as the PLL's reference clock. The HMC7044 generates a 1GHz clock for the AD9910 as a sampling clock and also generates a clock for the FPGA as a reference clock. The clock fan-out chip can be connected to an external SYNC input or the SYNC_OUT of a DDS chip. Connecting the SYNC_OUT of one DDS chip to the clock fan-out chip effectively uses one DDS chip as the master chip and the others as slave chips. This not only reduces the complexity of synchronization control but also simplifies system design.

[0035] Through the aforementioned technical means, the multi-channel DDS signal source of this invention can generate multi-channel 0-400MHz intermediate frequency signals by controlling the DDS chip and clock chip via an FPGA. It also features the ability to individually control and program each channel for amplitude attenuation, phase, frequency, and step control, and achieves multi-channel phase synchronization through logic control. Taking the AD9910 DDS chip and HMC7044 clock chip as an example, the synchronization accuracy between channels can be improved to within 50ps.

[0036] Specifically, the FPGA is configured to control the operation of the clock chip and each DDS chip according to the program loaded on it. Furthermore, the FPGA is connected to a FLASH module and a DDR3 module; wherein the FLASH module is used to store the FPGA's program; and the DDR3 module is used to cache the FPGA's runtime data.

[0037] After the system powers on, the FPGA begins loading the program from the FLASH module. Once the program starts, the FPGA automatically configures the clock chip according to the internal clock mode set in the program. After clock locking, it begins controlling the power-on and initialization of each DDS signal channel. Once the DDS chip initialization is successful, the overall system initialization is complete. Users can control a host computer to interact with the FPGA via serial or Ethernet ports, thereby controlling functions such as DDS chip reading / writing, analog front-end data configuration, PROFILE_PIN selection, DDR3 data reading / writing, clock mode switching, and channel switching. The host computer can connect to the FPGA's serial port via a USB-to-serial chip (CP2103).

[0038] Specifically, the multi-channel DDS signal source of the present invention further includes: a digital power supply module and an analog power supply module; wherein, the digital power supply module is used to provide power to the FPGA, the FLASH module and the DDR3 module; the analog power supply module is used to provide power to the clock chip, the DDS chip in each DDS signal channel, the variable attenuator, the amplifier and the analog switch.

[0039] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-channel DDS signal source, characterized in that, include: FPGA, clock chip, clock fan-out chip, and multiple DDS signal channels; among them, The DDS signal channel includes: a DDS chip, a balun, a low-pass filter, a variable attenuator, a fixed attenuator, an amplifier, and an analog switch connected in sequence; The clock chip is used to provide a sampling clock for the DDS chip of each DDS signal channel and a reference clock for the FPGA; The clock fan-out chip is used to provide a SYNC_IN signal to the DDS chip for each of the DDS signal channels; The FPGA is connected to the DDS chip, variable attenuator, and analog switch of each DDS signal channel, respectively, for monitoring the SYNC_SMP_ERR signal of each DDS chip. If a high level SYNC_SMP_ERR signal is detected, the delay value of each DDS chip receiving the SYNC_IN signal is dynamically adjusted; the attenuation value of each variable attenuator is controlled according to a preset passband amplitude curve; and the corresponding number of analog switches are controlled to turn on their respective DDS signal channels according to the set number of channels. The trace lengths from the clock chip to the sampling clock input pin of the DDS chip in each of the DDS signal channels are equal; the trace lengths from the clock fan-out chip to the SYNC_IN signal input pin of the DDS chip in each of the DDS signal channels are also equal. The trace lengths of the FPGA connected to the I / O_RESET pins of the DDS chips in each DDS signal channel are equal; the trace lengths of the FPGA connected to the SYNC_CLK pins of the DDS chips in each DDS signal channel are equal; the trace lengths of the FPGA connected to the I / O_UPDATE pins of the DDS chips in each DDS signal channel are equal; and the trace lengths of the FPGA connected to the PROFILE pins of the DDS chips in each DDS signal channel are equal.

2. The multi-channel DDS signal source as described in claim 1, characterized in that, The FPGA is configured to output I / O_RESET, I / O_UPDATE, and PROFILE signals through a programmable input / output unit; and, on the falling edge of the SYNC_CLK signal, to output the I / O_UPDATE signal to the I / O_UPDATE pin of the DDS chip, and / or to output the PROFILE signal to the PROFILE pin of the DDS chip.

3. A multi-channel DDS signal source as described in claim 1, characterized in that, The signal input of the clock fan-out chip is provided by the signal output from the SYNC_OUT pin of the DDS chip.

4. A multi-channel DDS signal source as described in claim 1, characterized in that, The variable attenuator provides adjustable attenuation steps of 0.5 dB.

5. A multi-channel DDS signal source as described in any one of claims 1 to 4, characterized in that, The FPGA is configured to control the operation of the clock chip and each DDS chip according to the program loaded thereon.

6. A multi-channel DDS signal source as described in claim 5, characterized in that, The FPGA is connected to a FLASH module and a DDR3 module; wherein... The FLASH module is used to store the program of the FPGA; The DDR3 module is used to cache the FPGA's operating data.

7. A multi-channel DDS signal source as described in claim 6, characterized in that, Also includes: Digital power modules and analog power modules; among which, The digital power module is used to provide power to the FPGA, the FLASH module and the DDR3 module; The analog power supply module is used to provide power to the clock chip, the DDS chip in each DDS signal channel, the variable attenuator, the amplifier, and the analog switch.

8. A multi-channel DDS signal source as described in claim 1, characterized in that, The FPGA is configured with a network interface or a serial interface for interacting with a host computer.

Images