Dynamic graph execution method and apparatus under artificial intelligence graph framework

Abstract

The present disclosure provides a dynamic graph execution method and device under an artificial intelligence graph framework, relates to the field of artificial intelligence, and particularly relates to the field of dynamic graph calculation in a deep learning framework. The implementation scheme is: obtaining an artificial intelligence graph framework, the artificial intelligence graph framework processes first data and includes multiple subgraphs, each of the multiple subgraphs indicates a corresponding operation to be performed on a corresponding type of tensor in multiple types of tensors obtained based on the first data; obtaining at least one target subgraph in the multiple subgraphs, each of the at least one target subgraph indicates a corresponding operation to be performed on a target type of tensor in the multiple types of tensors corresponding to related data of the first data, wherein the data amount of the related data is less than the data amount of the first data; and obtaining a virtualization instruction corresponding to each of the at least one target subgraph.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence, and more particularly to the field of dynamic graph computation in deep learning frameworks, specifically to a dynamic graph execution method, apparatus, electronic device, computer-readable storage medium, and computer program product under an artificial intelligence graph framework. Background Technology

[0002] Artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies mainly include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0003] With the development of artificial intelligence technology, deep learning frameworks have been applied to fields such as computer vision, speech recognition, and natural language processing, achieving excellent results. Dynamic graphs in computational graph-based deep learning frameworks have garnered significant attention due to their intuitive and clear concepts, which better align with human thought processes.

[0004] The methods described in this section are not necessarily methods that had been previously conceived or adopted. Unless otherwise specified, no method described in this section should be assumed to be prior art simply because it is included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to be accepted in any prior art. Summary of the Invention

[0005] This disclosure provides a dynamic graph execution method, apparatus, electronic device, computer-readable storage medium, and computer program product within an artificial intelligence graph framework.

[0006] According to one aspect of this disclosure, a dynamic graph execution method under an artificial intelligence graph framework is provided, comprising: obtaining an artificial intelligence graph framework, the artificial intelligence graph framework processing first data and including a plurality of subgraphs, each of the plurality of subgraphs indicating a corresponding operation to be performed on a tensor of a corresponding type among a plurality of tensors obtained based on the first data; obtaining at least one target subgraph among the plurality of subgraphs, each target subgraph indicating a corresponding operation to be performed on a tensor of a target type among the plurality of tensors corresponding to related data of the first data, wherein the amount of related data is less than the amount of first data; and obtaining virtualization instructions corresponding to each target subgraph among the at least one target subgraph, so that a virtual machine executes the virtualization instructions corresponding to each target subgraph among the at least one target subgraph, thereby realizing the corresponding operation to be performed by the target subgraph on the tensor of the target type.

[0007] According to another aspect of this disclosure, a dynamic graph execution apparatus under an artificial intelligence graph framework is provided, comprising: an artificial intelligence graph framework acquisition unit configured to acquire an artificial intelligence graph framework, the artificial intelligence graph framework processing first data and including a plurality of subgraphs, each of the plurality of subgraphs indicating a corresponding operation to be performed on a tensor of a corresponding type among a plurality of types of tensors obtained based on the first data; a target subgraph acquisition unit configured to acquire at least one target subgraph among the plurality of subgraphs, each target subgraph indicating a corresponding operation to be performed on a tensor of a target type among the plurality of types of tensors corresponding to related data of the first data, wherein the amount of related data is less than the amount of first data; and a virtualization instruction acquisition unit configured to acquire a virtualization instruction corresponding to each target subgraph among the at least one target subgraph, so as to cause a virtual machine to execute the virtualization instruction corresponding to each target subgraph among the at least one target subgraph, thereby realizing the corresponding operation to be performed by the target subgraph on the tensor of the target type.

[0008] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method according to embodiments of this disclosure.

[0009] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described according to embodiments of this disclosure.

[0010] According to another aspect of this disclosure, a computer program product is provided, including a computer program, wherein the computer program, when executed by a processor, implements the method described according to embodiments of this disclosure.

[0011] According to one or more embodiments of this disclosure, the overhead of computing resources can be reduced during the execution of dynamic graphs.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0013] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0014] Figure 1 A flowchart of a dynamic graph execution method under an artificial intelligence graph framework according to an embodiment of the present disclosure is shown;

[0015] Figure 2 A schematic diagram of an artificial intelligence graph framework in a dynamic graph execution method according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A flowchart illustrating the process of obtaining at least one target subgraph among the plurality of subgraphs in a dynamic graph execution method under an artificial intelligence graph framework according to an embodiment of the present disclosure is shown.

[0017] Figure 4 A schematic diagram is shown illustrating the extraction of at least one target subgraph from an artificial intelligence graph framework in a dynamic graph execution method under an artificial intelligence graph framework according to embodiments of the present disclosure.

[0018] Figure 5 The illustration shows a schematic diagram of a dynamic graph execution method under an artificial intelligence graph framework according to an embodiment of the present disclosure, in which at least one target subgraph is stored in the order of at least one corresponding operation by traversing the artificial intelligence graph framework to obtain at least one target subgraph among a plurality of subgraphs.

[0019] Figure 6 The illustration shows a schematic diagram of a virtual machine executing virtualization instructions corresponding to each target subgraph in at least one target subgraph in a dynamic graph execution method under an artificial intelligence graph framework according to an embodiment of the present disclosure, in accordance with the storage order of multiple virtualization instructions;

[0020] Figure 7 A structural block diagram of a dynamic graph execution apparatus under an artificial intelligence graph framework according to embodiments of the present disclosure is shown; and

[0021] Figure 8 A structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0022] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0023] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0024] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof.

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0026] In related technologies, all operations on subgraphs within a computational graph framework for artificial intelligence are executed on accelerators. During execution, data is acquired sequentially and a kernel is deployed to perform the operation, with each execution incurring the overhead of starting the kernel function. However, the various subgraphs within an AI graph framework often have different computational overheads due to the different types of tensors they process. For example, in a computational graph for image processing, the processing often involves both the image itself and other image-related data (such as shape and size). Since the amount of other data is much smaller than the amount of image data, the computational overhead of processing tensors obtained from other data is often small, and in some cases, far less than the overhead of starting the kernel function. This results in a significant amount of runtime overhead being wasted on starting the kernel function, failing to improve efficiency.

[0027] According to embodiments of this disclosure, a dynamic graph execution method within an artificial intelligence graph framework is disclosed. See also... Figure 1 The dynamic graph execution method 100 under the artificial intelligence graph framework according to some embodiments of the present disclosure includes:

[0028] Step S110: Obtain an artificial intelligence graph framework, which processes the first data and includes multiple subgraphs, each of the multiple subgraphs indicating a corresponding operation to be performed on a tensor of a corresponding type among multiple types of tensors obtained based on the first data;

[0029] Step S120: Obtain at least one target subgraph from the plurality of subgraphs, each target subgraph indicating a corresponding operation to be performed on a tensor of a target type corresponding to the related data of the first data among the plurality of tensors, wherein the amount of related data is less than the amount of the first data; and

[0030] Step S130: Obtain the virtualization instruction corresponding to each target subgraph in the at least one target subgraph, so that the virtual machine executes the virtualization instruction corresponding to each target subgraph in the at least one target subgraph, thereby realizing the corresponding operation to be performed by the target subgraph for the tensor of the target type.

[0031] By transforming the target subgraph in the AI ​​graph framework, which indicates operations on tensors of a target type, into virtual instructions executed by a virtual machine, the process of executing the target subgraph to perform operations on tensors of the target type does not need to be sent to the kernel startup function, reducing the overhead of the kernel startup function. Simultaneously, since the tensors of the target type correspond to the related data of the first data being processed by the AI ​​graph framework, and the amount of related data is smaller than the amount of the first data, the computational overhead in the process of executing the target subgraph to perform operations on tensors of the target type is lower. Executing virtualized instructions through a virtual machine to perform operations on tensors of the target type avoids increasing the computational time overhead in the process of executing the target subgraph, thereby improving the overall execution efficiency of the dynamic graph.

[0032] In some embodiments, the artificial intelligence graph framework can be a computational graph-based deep learning language framework applied to fields such as computer vision, speech recognition, and natural language processing. Depending on the application domain, the first data it processes differs. During the processing of the first data, a graph compiler compiles the artificial intelligence graph framework to achieve the processing of the first data. Within the graph compiler, there exist tensors of different types obtained based on the first data.

[0033] For example, an artificial intelligence graph framework could be a computational graph-based deep learning language framework applied to computer vision, where the first type of data to be processed is image data. During image data processing, there exist tensors corresponding to the image data itself, for example, denoted by T1; and tensors corresponding to the shape data of the image data, for example, denoted by T2. The amount of data in T1 is significantly greater than the amount of data in T2.

[0034] See Figure 2 The diagram illustrates an artificial intelligence graph framework according to some embodiments of the present disclosure. Solid boxes indicate subgraphs, subgraphs within dashed boxes 201 indicate operations on tensors of type T2, and subgraphs outside dashed boxes 201 indicate operations on tensors of type T1.

[0035] In related technologies, all subgraphs are distributed to devices used for intensive computing (e.g., accelerator cards), and the kernel function is activated to perform operations on tensors of the corresponding types, thereby achieving the execution of the subgraph.

[0036] In embodiments according to this disclosure, by converting the subgraph within the dashed box into virtualization instructions, computation is performed on the CPU side. Since there is no overhead of starting a kernel function on the CPU side, the overall operating efficiency is greatly improved.

[0037] In some embodiments, the plurality of subgraphs are arranged in order such that the indicated plurality of corresponding operations are executed sequentially, and wherein the at least one target subgraph is a plurality of subgraphs with interconnected regions, such that the indicated at least one corresponding operation is a plurality of operations that are executed consecutively among the plurality of corresponding operations.

[0038] For example, continue to see Figure 2 The arrows between the solid-line boxes indicate the order of operations indicated by the subgraphs. For example, the arrow between subgraphs 210 and 220 points to subgraph 220, indicating that the operation indicated by subgraph 210 precedes the operation indicated by subgraph 220. Furthermore, when the operations indicated by multiple subgraphs are executed consecutively, it indicates that the multiple subgraphs are located in a connected region. For example, if the operation indicated by subgraph 210 is executed consecutively with the operation indicated by subgraph 220, it means that subgraphs 210 and 220 are located in a connected region.

[0039] By identifying multiple interconnected subgraphs as at least one target subgraph, data exchange between subgraphs during execution will not introduce H2D (host to device) or D2H (device to host) operations, further reducing the overhead during subgraph execution.

[0040] In some embodiments, in the artificial intelligence graph framework, each subgraph is assigned a preset identifier to indicate the type of tensor it targets. In step S120, the at least one target subgraph is obtained based on the preset identifier of each subgraph among the multiple subgraphs.

[0041] In some embodiments, such as Figure 3 As shown, step S120, obtaining at least one target subgraph among the plurality of subgraphs, includes:

[0042] Step S310: Obtain a preset subgraph template, the subgraph template indicating the target operation to be performed on the tensor of the target type; and

[0043] Step S320: Based on the preset subgraph template, traverse the artificial intelligence graph framework to obtain at least one target subgraph, wherein the corresponding operation performed by the at least one target subgraph corresponds to the target operation.

[0044] By pre-setting subgraph templates and traversing the AI ​​graph framework, the system can automatically identify and merge subgraphs, simplifying the process of acquiring target subgraphs and reducing manual operation costs.

[0045] In some embodiments, the AI ​​graph framework begins with a subgraph that performs the "shape_of" operation on tensors of type T2 and ends with a subgraph that performs the operations "dyn.strided_slice", "dyn.tile", "dyn.reshape", and "dyn.full" on tensors of type T2. For example, as... Figure 3 As shown, in the AI ​​graph framework, the subgraph that performs the "shape_of" operation on a tensor of type T2 starts with "shape_of" and ends with the subgraph that performs the "dyn.reshape" operation on a tensor of type T2. During the traversal, the subgraphs that perform the "shape_of" operation on a tensor of type T2 and the subgraphs that perform the "dyn.***" operation on a tensor of type T2 are used as subgraph templates. By traversing each operator in the subgraphs, wildcard separation is performed on each subgraph, extracting the subgraphs that originally existed on the XPU side, thereby obtaining multiple target subgraphs.

[0046] In some embodiments, in step S130, each target subgraph in at least one target subgraph is compiled using a compiler to obtain its corresponding virtualization instructions. These virtualization instructions, when executed by a virtual machine, execute the subgraph, thereby implementing the tensor operations indicated by the subgraph. In this process, because the subgraph execution process and the computation process in the derivation process are implemented on the central processing unit (CPU), without distributing the subgraph to other computing devices (e.g., accelerator cards), it is unnecessary to start the kernel function, thus reducing computational overhead.

[0047] See Figure 4 The diagram illustrates a dynamic graph execution method according to an embodiment of the present disclosure, in which subgraphs originally stored on the XPU (including subgraphs that perform the "shape_of" operation on tensors of type T2, subgraphs that perform the "strided_slice" operation on tensors of type T2, subgraphs that perform the "Make_tuple" operation on tensors of type T2, etc.) are extracted and uniformly placed on a new wildcard operator New.Dyn.reshape. By converting the wildcard operator New.Dyn.reshape into virtualization instructions, the computation process in the derivation process runs on a virtual machine.

[0048] In some embodiments, step S120, obtaining at least one target subgraph among the plurality of subgraphs, includes:

[0049] The at least one target subgraph is stored in the order of the at least one corresponding operation; and wherein step S130, obtaining the virtualization instruction corresponding to each target subgraph in the at least one target subgraph includes:

[0050] Obtain the instruction set corresponding to the at least one target subgraph, and arrange the multiple virtualization instructions in the instruction set according to the storage order of the at least one target subgraph, so that the virtual machine executes the virtualization instructions corresponding to each target subgraph in the at least one target subgraph according to the storage order of the multiple virtualization instructions.

[0051] By obtaining an instruction set arranged according to the storage order of at least one target subgraph, the virtual machine can read instructions sequentially from the instruction set during the execution of virtualization instructions, further reducing the overhead of logical processing between instructions.

[0052] like Figure 5 As shown, during the traversal of the AI ​​graph framework, by traversing each operator in the graph, the operations along the traversal path and their related inputs are recorded to obtain an operation pool (OPpool) corresponding to at least one target subgraph. The operation pool stores at least one corresponding operation in sequence as indicated by at least one target subgraph; that is, at least one target subgraph is stored according to the order of at least one corresponding operation. Figure 6 As shown, in the process of obtaining the virtualization instructions corresponding to each target subgraph in at least one target subgraph, the instructions for the corresponding operations are obtained by reading the corresponding operations in the operation pool one by one, so that the virtualization instructions in the obtained instruction set are arranged according to the storage order of at least one target subgraph. Further, in some embodiments, during the execution of virtualization instructions, instructions are read one by one from the instruction set for computation, thereby realizing the execution of virtualization. The computation input is obtained from the data pool Num pool, and the computation output is filled into the data pool Num pool for use in the execution of the next virtualization instruction.

[0053] In some embodiments, the corresponding operation indicated by the first target subgraph in the at least one target subgraph corresponds to multiple algorithmic logics, and step S230, obtaining the virtualization instructions corresponding to each target subgraph in the at least one target subgraph, includes:

[0054] Obtaining virtualization instructions corresponding to each of a plurality of algorithmic logics corresponding to the first target subgraph; and wherein, the virtual machine executing the virtualization instructions corresponding to each target subgraph in the at least one target subgraph includes:

[0055] For the corresponding operation indicated by the first target subgraph, obtain the input corresponding to that operation; and

[0056] Execute the virtualization instructions corresponding to the algorithm logic corresponding to the input among the multiple algorithm logics corresponding to the first target subgraph.

[0057] In the framework of artificial intelligence graphs, the functions of each subgraph indicated by the operation are often quite complex. This means that when the logic is expanded for the corresponding operator, multiple algorithm logics are often obtained. In the process of executing the corresponding operator to implement the indicated operation, it is often necessary to traverse each algorithm logic for the input to obtain the corresponding result.

[0058] According to the embodiments of this disclosure, during the process of obtaining virtualization instructions, the operators corresponding to the corresponding operations indicated by the first target subgraph are simplified into virtualization instructions. At the same time, during the execution process, the virtualization instructions corresponding to the algorithm logic corresponding to the input in multiple algorithm logics are determined based on the input, thereby further reducing the overhead in the execution process of virtualization instructions.

[0059] For example, by performing algorithmic expansion on the operators corresponding to the operations indicated by the first target subgraph, four algorithmic logics are obtained. In obtaining the corresponding virtualization instructions, each algorithmic logic typically has its own virtualization instruction, resulting in four virtualization instructions. Since only one algorithmic logic is implemented during computation for different inputs, the virtualization instruction corresponding to the first target subgraph is often selected for execution based on the current input during the virtualization instruction execution process. This achieves the execution of the first target subgraph. Compared to executing the first target subgraph by executing the operators corresponding to the operations indicated by the first target subgraph within the AI ​​graph framework, this reduces the time overhead of traversing the other three algorithmic logics, further reducing the overhead of executing the first target subgraph.

[0060] According to another aspect of this disclosure, a dynamic graph execution device within an artificial intelligence graph framework is also provided, such as... Figure 7As shown, the apparatus 700 includes: an artificial intelligence graph framework acquisition unit 710, configured to acquire an artificial intelligence graph framework, the artificial intelligence graph framework being processed for first data and including multiple subgraphs, each of the multiple subgraphs indicating a corresponding operation to be performed on a tensor of a corresponding type among multiple types of tensors obtained based on the first data; a target subgraph acquisition unit 720, configured to acquire at least one target subgraph among the multiple subgraphs, each target subgraph indicating a corresponding operation to be performed on a tensor of a target type among the multiple types of tensors corresponding to related data of the first data, wherein the amount of related data is less than the amount of first data; and a virtualization instruction acquisition unit 730, configured to acquire a virtualization instruction corresponding to each target subgraph among the at least one target subgraph, so that a virtual machine executes the virtualization instruction corresponding to each target subgraph among the at least one target subgraph, thereby realizing the corresponding operation to be performed by the target subgraph on the tensor of the target type.

[0061] In some embodiments, the plurality of subgraphs are arranged in order such that the indicated plurality of corresponding operations are executed sequentially, and wherein the at least one target subgraph is a plurality of subgraphs with interconnected regions, such that the indicated at least one corresponding operation is a plurality of operations that are executed consecutively among the plurality of corresponding operations.

[0062] In some embodiments, the target subgraph acquisition unit includes: a preset subgraph template acquisition unit configured to acquire a preset subgraph template, the subgraph template indicating a target operation to be performed on a tensor of the target type; and a traversal unit configured to traverse the artificial intelligence graph framework based on the preset subgraph template to acquire the at least one target subgraph, wherein the corresponding operation performed on the at least one target subgraph corresponds to the target operation.

[0063] In some embodiments, the target subgraph acquisition unit includes: a first acquisition subunit configured to store the at least one target subgraph in the order of the at least one corresponding operation; and wherein the virtualization instruction acquisition unit includes: an instruction set acquisition unit configured to obtain an instruction set corresponding to the at least one target subgraph, wherein a plurality of virtualization instructions in the instruction set are arranged in the storage order of the at least one target subgraph, such that the virtual machine executes the virtualization instruction corresponding to each target subgraph in the at least one target subgraph in the storage order of the plurality of virtualization instructions.

[0064] In some embodiments, the corresponding operation indicated by the first target subgraph in the at least one target subgraph corresponds to a plurality of algorithmic logics. The target subgraph acquisition unit includes: obtaining a virtualization instruction corresponding to each of the plurality of algorithmic logics corresponding to the first target subgraph; and wherein the virtual machine executes the virtualization instruction corresponding to each target subgraph in the at least one target subgraph including: obtaining the input corresponding to the corresponding operation indicated by the first target subgraph; and executing the virtualization instruction corresponding to the algorithmic logic corresponding to the input among the plurality of algorithmic logics corresponding to the first target subgraph.

[0065] In some embodiments, the first data is image data, and the related data is the shape data of the graphic data.

[0066] According to embodiments of this disclosure, an electronic device, a readable storage medium, and a computer program product are also provided.

[0067] refer to Figure 8 The present invention describes a structural block diagram of an electronic device 800 that can serve as a server or client of the present disclosure, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0068] like Figure 8 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0069] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, output unit 807, storage unit 808, and communication unit 809. Input unit 806 can be any type of device capable of inputting information to electronic device 800. Input unit 806 can receive input digital or character information and generate key signal inputs related to user settings and / or function control of electronic device, and can include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 807 can be any type of device capable of presenting information, and can include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 808 can include, but is not limited to, a hard disk and an optical disk. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and can include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth™ devices, 802.11 devices, WiFi devices, WiMax devices, cellular communication devices, and / or the like.

[0070] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as method 200. For example, in some embodiments, method 200 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of method 200 described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform method 200 by any other suitable means (e.g., by means of firmware).

[0071] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0072] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0073] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0074] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0075] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0076] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0077] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0078] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of the invention is not limited by these embodiments or examples, but only by the granted claims and their equivalents. Various elements in the embodiments or examples may be omitted or substituted with their equivalents. Furthermore, it is possible to refer to D-EF222061

[0079] The steps may be performed in a different order than that described in this disclosure. Furthermore, various elements of the embodiments or examples can be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalent elements that appear after this disclosure.

Claims

1. A dynamic graph execution method within an artificial intelligence graph framework, comprising: An artificial intelligence graph framework is obtained, which processes first data and includes multiple subgraphs, each of which indicates a corresponding operation to be performed on a tensor of a corresponding type among multiple types of tensors obtained based on the first data, wherein the multiple types of tensors include tensors obtained based on the first data itself and tensors obtained based on related data of the first data; Obtain at least one target subgraph from the plurality of subgraphs, each target subgraph indicating a corresponding operation to be performed on a tensor of a target type corresponding to the relevant data of the first data among the tensors of the plurality of types; wherein the amount of the relevant data is less than the amount of the first data; and Obtain the virtualization instructions corresponding to each target subgraph in the at least one target subgraph, so that the virtual machine executes the virtualization instructions corresponding to each target subgraph in the at least one target subgraph on the central processing unit without starting the kernel function, thereby realizing the corresponding operation to be performed by the target subgraph for the tensor of the target type.

2. The method according to claim 1, wherein, The plurality of subgraphs are arranged in order such that the indicated plurality of corresponding operations are executed in order, and wherein the at least one target subgraph is a plurality of subgraphs in which regions are connected, such that the indicated at least one corresponding operation is a plurality of operations that are executed consecutively among the plurality of corresponding operations.

3. The method according to claim 2, wherein, Obtaining at least one target subgraph from the plurality of subgraphs includes: Obtain a preset subgraph template, the subgraph template indicating the target operation to be performed on a tensor of the target type; and Based on the preset subgraph template, the artificial intelligence graph framework is traversed to obtain at least one target subgraph, wherein the corresponding operation performed by the at least one target subgraph corresponds to the target operation.

4. The method according to claim 2, wherein, Obtaining at least one target subgraph from the plurality of subgraphs includes: The at least one target subgraph is stored in the order of the at least one corresponding operation; and wherein obtaining the virtualization instruction corresponding to each target subgraph in the at least one target subgraph includes: Obtain the instruction set corresponding to the at least one target subgraph, and arrange the multiple virtualization instructions in the instruction set according to the storage order of the at least one target subgraph, so that the virtual machine executes the virtualization instructions corresponding to each target subgraph in the at least one target subgraph according to the storage order of the multiple virtualization instructions.

5. The method according to claim 2, wherein, The corresponding operation indicated by the first target subgraph in the at least one target subgraph corresponds to multiple algorithmic logics. The virtualization instructions for obtaining each target subgraph corresponding to the at least one target subgraph include: Obtaining virtualization instructions corresponding to each of a plurality of algorithmic logics corresponding to the first target subgraph; and wherein, the virtual machine executing the virtualization instructions corresponding to each target subgraph in the at least one target subgraph includes: For the corresponding operation indicated by the first target subgraph, obtain the input corresponding to that operation; and Execute the virtualization instructions corresponding to the algorithm logic corresponding to the input among the multiple algorithm logics corresponding to the first target subgraph.

6. The method according to any one of claims 1-5, wherein, The first data is image data, and the related data is the shape data of the image data.

7. A dynamic graph execution device within an artificial intelligence graph framework, comprising: An AI graph framework acquisition unit is configured to acquire an AI graph framework, which processes first data and includes multiple subgraphs. Each subgraph in the multiple subgraphs indicates a corresponding operation to be performed on a tensor of a corresponding type among multiple types of tensors obtained based on the first data. The multiple types of tensors include tensors obtained based on the first data itself and tensors obtained based on related data of the first data. A target subgraph acquisition unit is configured to acquire at least one target subgraph from the plurality of subgraphs, each target subgraph indicating a corresponding operation to be performed on a tensor of a target type corresponding to the related data of the first data among the plurality of tensors, wherein the amount of the related data is less than the amount of the first data; and The virtualization instruction acquisition unit is configured to acquire the virtualization instruction corresponding to each target subgraph in the at least one target subgraph, so that the virtual machine executes the virtualization instruction corresponding to each target subgraph in the at least one target subgraph on the central processing unit without starting the kernel function, thereby realizing the corresponding operation to be performed by the target subgraph for the tensor of the target type.

8. The apparatus according to claim 7, wherein, The plurality of subgraphs are arranged in order such that the indicated plurality of corresponding operations are executed in order, and wherein the at least one target subgraph is a plurality of subgraphs in which regions are connected, such that the indicated at least one corresponding operation is a plurality of operations that are executed consecutively among the plurality of corresponding operations.

9. The apparatus according to claim 8, wherein, The target subgraph acquisition unit includes: A preset subgraph template acquisition unit is configured to acquire a preset subgraph template, the subgraph template indicating the target operation to be performed on a tensor of the target type; and A traversal unit is configured to traverse the artificial intelligence graph framework based on the preset subgraph template to obtain the at least one target subgraph, wherein the corresponding operation performed by the at least one target subgraph corresponds to the target operation.

10. The apparatus according to claim 8, wherein, The target subgraph acquisition unit includes: A first acquisition subunit is configured to store the at least one target subgraph in the order of the at least one corresponding operation; and wherein the virtualization instruction acquisition unit includes: The instruction set acquisition unit is configured to acquire the instruction set corresponding to the at least one target subgraph, wherein multiple virtualization instructions in the instruction set are arranged according to the storage order of the at least one target subgraph, such that the virtual machine executes the virtualization instructions corresponding to each target subgraph in the at least one target subgraph according to the storage order of the multiple virtualization instructions.

11. The apparatus according to claim 8, wherein, The corresponding operation indicated by the first target subgraph in the at least one target subgraph corresponds to multiple algorithmic logics. The target subgraph acquisition unit includes: Obtaining virtualization instructions corresponding to each of a plurality of algorithmic logics corresponding to the first target subgraph; and wherein, the virtual machine executing the virtualization instructions corresponding to each target subgraph in the at least one target subgraph includes: For the corresponding operation indicated by the first target subgraph, obtain the input corresponding to that operation; and Execute the virtualization instructions corresponding to the algorithm logic corresponding to the input among the multiple algorithm logics corresponding to the first target subgraph.

12. The apparatus according to any one of claims 7-11, wherein, The first data is image data, and the related data is the shape data of the image data.

13. An electronic device, comprising: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-6.

15. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method of any one of claims 1-6.

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