Method for establishing equivalent circuit of ldmos tube

Abstract

A method for establishing an equivalent circuit of an LDMOS tube, the LDMOS tube comprising a first drain and a first source. The method for establishing the equivalent circuit of the LDMOS tube comprises: establishing a primary equivalent circuit, the primary equivalent circuit comprising an equivalent MOS tube, a drain parasitic resistance and a source parasitic resistance, the equivalent MOS tube comprising a second drain and a second source, a first end of the drain parasitic resistance being connected to the first drain, a second end of the drain parasitic resistance being connected to the second drain, a first end of the source parasitic resistance being connected to the second source, and a second end of the source parasitic resistance being connected to the first source; and correcting a resistance value of the drain parasitic resistance in relation to a first correction value and a second correction value, the first correction value being related to a voltage between the first drain and the first source, and the second correction value being related to a voltage between the second drain and the first source.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a method for constructing an equivalent circuit of an LDMOS transistor. Background Technology

[0002] Chinese patent document CN105160141B discloses a modeling method for ultra-high voltage field-effect transistor circuits, such as... Figure 1 As shown, the left side is the original equivalent circuit of an LDMOS (Laterally Diffused Metal-Oxide Semiconductor) transistor, which includes a first drain D and a first source S.

[0003] The original equivalent circuit includes: an equivalent MOSFET M1, a drain parasitic resistor R1, and a source parasitic resistor R2. The first end of the drain parasitic resistor R1 is connected to the first drain D, and the second end of the drain parasitic resistor R1 is connected to the drain of the equivalent MOSFET M1. The first end of the source parasitic resistor R2 is connected to the source of the equivalent MOSFET M1, and the second end of the source parasitic resistor R2 is connected to the first source S.

[0004] To facilitate understanding of the calculation process for the drain parasitic resistance R1, in Figure 1 The circuit model is shown within the dashed box on the right, including a series-connected voltage control source ec1f and a resistor Rnvd. One end of the resistor Rnvd is connected to the voltage control source ec1f, and the other end is grounded. The voltage value of the voltage control source ec1f varies with the voltage Vds between the first drain D and the first source S. Details are as follows:

[0005] r1=rds*(1.0+vr1*v(nvd,0)+vr2*v(nvd,0)*v(nvd,0))*(1+vv1*abs(v(d,s)))

[0006] v(nvd,0)='deltaV1-(deltaV2 / (ec1 / (abs(v(d,s)**a))+ec2*(abs(v(d,s))**b))**exp)'

[0007] Where v(d,s) is the voltage value of Vds, rds is the estimated resistance of the drain parasitic resistance R1, vr1 and vr2 are the correction coefficients for adjusting the amplitude of the current and voltage in the quasi-saturation region, vv1 is the artificial voltage correction coefficient, deltaV1, deltaV2, ec1, and ec2 are the mathematical correction coefficients, and a, b, and exp are the exponential correction coefficients.

[0008] The patent document introduces v(nvd,0) into the expression of the drain parasitic resistance R1 resistance r1, and adds vr1 and vr2 to adjust the IDVD (a conventional curve of LDMOS device test, which refers to applying a voltage to the first drain D and testing the current at the first drain D) correction coefficient, and through the adjustment of all coefficients, the continuity and physical extension of the LDMOS model under the condition of 500V can be well realized.

[0009] However, the equivalent circuit established according to the above patent document is difficult to fit the output characteristics in the transition region (between the linear region and the quasi-saturation region) with the actual data, that is, the simulated data does not match the actual physical data. SUMMARY

[0010] The problem solved by the present application is that the simulated data obtained according to the existing equivalent circuit of LDMOS tube does not match the actual physical data.

[0011] To solve the above problems, the present application provides a method for establishing an equivalent circuit of an LDMOS tube, the LDMOS tube comprising a first drain and a first source. The method for establishing an equivalent circuit of an LDMOS tube comprises: establishing a primary equivalent circuit, the primary equivalent circuit comprising an equivalent MOS tube, a drain parasitic resistance and a source parasitic resistance, the equivalent MOS tube comprising a second drain and a second source; a first end of the drain parasitic resistance is connected to the first drain, a second end of the drain parasitic resistance is connected to the second drain, a first end of the source parasitic resistance is connected to the second source, and a second end of the source parasitic resistance is connected to the first source; and modifying the resistance value of the drain parasitic resistance to be related to a first correction value and a second correction value, the first correction value being related to the voltage between the first drain and the first source, and the second correction value being related to the voltage between the second drain and the first source.

[0012] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0013] The second correction value is added in the calculation of the resistance value of the drain parasitic resistance, which can better fit the output characteristics of IDVD in the transition region with the actual data, so that when the voltage between the source and the drain of the LDMOS is extended to a larger value, the current between the source and the drain can still obtain a more physical characteristic, and the equivalent circuit of the LDMOS tube established accordingly can obtain a more physical simulation result. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a schematic diagram of a circuit model of an existing LDMOS tube;

[0015] Figure 2 is a schematic diagram of a current-voltage characteristic curve;

[0016] Figure 3 is a schematic diagram of an equivalent circuit of the LDMOS tube of the present application;

[0017] Figure 4 is a flow chart of a method for establishing an equivalent circuit of the LDMOS tube of the present application;

[0018] Figures 5 to 7 output characteristic curves under different parameter debugging;

[0019] Figure 8 is a schematic diagram of a current-voltage characteristic curve of the present application. DETAILED DESCRIPTION

[0020] In combination with Figure 2 the schematic diagram of the current-voltage characteristic curve, the present inventors have further researched the model shown in Figure 1 and the resistance formula of the drain parasitic resistance and found that the existing formula of the resistance of the drain parasitic resistance is mainly used to describe the quasi-saturation region characteristic and it is difficult to fit the output characteristic in the transition region with the actual data.

[0021] When the voltage between the source and the drain of the LDMOS tube increases, the drain parasitic resistance will increase, and in the actual situation, the depletion region in the drain drift region will tend to be saturated after the drain voltage of the LDMOS reaches a certain value, so the resistance of the drain parasitic resistance will not become infinitely large.

[0022] Based on the above research, the present inventors propose a new method for establishing an equivalent circuit of the LDMOS tube. In order to make the above-mentioned purposes, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below in combination with the drawings.

[0023] In combination with Figure 3 and Figure 4 , the embodiment of the present application provides a method for establishing an equivalent circuit of an LDMOS tube, the LDMOS tube comprising: a first drain D1 and a first source S1.

[0024] The method for establishing an equivalent circuit of the LDMOS tube comprises:

[0025] Step S1, an original equivalent circuit is established, the original equivalent circuit comprising: an equivalent MOS tube M, a drain parasitic resistance R11 and a source parasitic resistance R12, the equivalent MOS tube comprising: a second drain D2 and a second source S2; a first end of the drain parasitic resistance R11 is connected to the first drain D1, a second end of the drain parasitic resistance R11 is connected to the second drain D2; a first end of the source parasitic resistance R12 is connected to the second source S2, and a second end of the source parasitic resistance R12 is connected to the first source S1.

[0026] Step S2, the resistance r11 of the drain parasitic resistance R11 is corrected to be related to a first correction value v(nvd,0) and a second correction value v(nvd1,0), the first correction value v(nvd,0) is related to the voltage Vds between the first drain D1 and the first source S1, and the second correction value is related to the voltage Vd1s between the second drain D2 and the first source S1.

[0027] In the resistance r11 calculation of the drain parasitic resistance R11 of the embodiment, the first correction value v(nvd,0) is avoided to be completely described, the second correction value v(nvd1,0) related to the voltage Vd1s between the second drain D2 and the first source S1 is added, the output characteristics of IDVD in the transition region can be better fitted with the actual data, and when the voltage Vds extends to a larger value, the current Ids between the first drain D1 and the first source S1 of the LDMOS can still obtain a more physical characteristic. The equivalent circuit of the LDMOS tube established in this way can obtain a simulation result closer to the physical data.

[0028] In the embodiment, the resistance r11 of the drain parasitic resistance R11 is related to the difference between the first correction value v(nvd,0) and the second correction value v(nvd1,0). Specifically, the resistance r11 of the drain parasitic resistance is

[0029] r11=rds*(1+v(nvd,0)-v(nvd1,0)) Formula 1

[0030] In formula 1, rds is the estimated value of the drain parasitic resistance. The first correction value v(nvd,0) contains parameters for fitting the first region, and the first region includes the transition region and the saturation region. The first correction value v(nvd,0) also contains parameters for fitting the saturation region. The second correction value v(nvd1,0) contains parameters for fitting the transition region.

[0031] The first correction value v(nvd,0)=’ec1*abs(v(d,s)**exp)’ Formula 2

[0032] In formula 2, ec1 is a mathematical correction coefficient, which is used for the parameters of the first region including the transition region and the saturation region. v(d,s) is the voltage value of the voltage Vds between the first drain D1 and the first source S1; and exp is an exponential correction coefficient, which is used for the parameters of the saturation region.

[0033] As can be seen from formula 2, compared with the prior art described in the background art, the embodiment simplifies formula 2 about the first correction value v(nvd,0).

[0034] The second correction value v(nvdl,0) = 'ec2*abs(v(dl,s))' Formula 3

[0035] In Formula 3, ec2 is a mathematical correction coefficient for fitting the transition region parameter. v(dl,s) is the voltage value of the voltage VdlS between the second drain D2 and the first source S1.

[0036] As can be seen from Formula 3, the embodiment introduces the parameter ec2 for fitting the transition region in the second correction value v(nvdl,0), so the fitting of IDVD in the transition region can be adjusted by the parameter ec2.

[0037] In Figure 3 In the right virtual box, a model for calculating the resistance value r11 of the drain parasitic resistance R11 is drawn. However, it is worth noting that this model is for the convenience of understanding the calculation method of the resistance value r11, and does not have actual physical meaning.

[0038] In this model, an ideal resistance bypass NVD2 is added beside the original branch NVD1, so the NVD2 bypass with v(dl,s) as a variable is added in the calculation formula of the resistance value r11 of the drain parasitic resistance R11.

[0039] Specifically, the voltage value of the first voltage control voltage source ec1f is the same as the voltage value v(d,s) of the voltage Vds between the first drain D1 and the first source S1, and the voltage value of the second voltage control voltage source ec2f is the same as the voltage value v(dl,s) of the voltage VdlS between the second drain D2 and the first source S1.

[0040] The voltage values of the first voltage control voltage source ec1f and the second voltage control voltage source ec2f are subtracted and input to the resistance R13, and finally the resistance value r11 of the total drain parasitic resistance R11 is calculated as: the expression containing v(d,s) is subtracted from the expression containing v(dl,s).

[0041] For the above established LDMOS tube equivalent circuit, by comparing the measured data of the LDMOS tube and the simulation results of the LDMOS tube equivalent circuit, the parameters ec1, ec2 and exp can be adjusted to obtain the fitting results.

[0042] The improved sub-circuit and formula are put into the HSPICE simulation tool for simulation, and the simulation conditions are: N-type LDMOS, Width = 20u, L = 1.5u, temperature 25℃. By trying to adjust the parameters of ec1, exp, ec2, the output characteristic curve shown in the figure can be obtained. Figures 5 to 7 The horizontal axis VD represents the voltage value of the first drain D1, and the vertical axis ID represents the current value of the first drain D1.

[0043] From Figure 5 It can be seen that, in the exp, ec2 remains fixed default parameter value adjustment ec1 value, ID will be with different ec1 value presents the overall up and down amplitude of the transition zone to the quasi-saturation zone, and the greater the gate-source voltage VGS trend more obvious.

[0044] From Figure 6 It can be seen that, in the exp, ec1 remains fixed default parameter value adjustment ec2 value, ID will be with different ec1 value presents the transition zone curve curvature left and right amplitude, ec2 value greater, the curvature moves to the left, ec2 value smaller, the curvature moves to the right, and the greater the gate-source voltage VGS trend more obvious.

[0045] From Figure 7 It can be seen that, in the ec1, ec2 remains fixed default parameter value adjustment exp value, ID will be with different exp value presents the quasi-saturation zone curve up and down amplitude, exp value greater, the more obvious LDMOS quasi-saturation characteristics presented.

[0046] Based on the above parameter adjustment, ec1, ec2, exp parameters and actual measurement device fitting, such as Figure 8 As shown, it is found that the LDMOS tube equivalent circuit based on the present embodiment can have good fitting accuracy for LDMOS IDVD from linear region-transition region-quasi-saturation region, and is more practical.

[0047] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the scope of protection of the present application should be limited by the scope defined by the claims.

Claims

1. A method of building an equivalent circuit of an LDMOS transistor, the LDMOS transistor comprising: A first drain and a first source, characterized in that comprising: An original equivalent circuit is established, and the original equivalent circuit comprises an equivalent MOS tube, a drain parasitic resistance and a source parasitic resistance, the equivalent MOS tube comprises a second drain and a second source; A first end of the drain parasitic resistance is connected to the first drain, a second end of the drain parasitic resistance is connected to the second drain, a first end of the source parasitic resistance is connected to the second source, and a second end of the source parasitic resistance is connected to the first source; The resistance value of the drain parasitic resistance is corrected to be related to a first correction value and a second correction value, the first correction value is related to the voltage between the first drain and the first source, and the second correction value is related to the voltage between the second drain and the first source, wherein the second correction value contains parameters for fitting the transition region; a resistance value of the drain parasitic resistance ; wherein rds is an estimated value of the drain parasitic resistance, v(nvd,0) is the first correction value, and v(nvd1,0) is the second correction value. the second correction value ; wherein ec2 is a mathematical correction factor for fitting parameters of the transition region; v(d1,s) is a voltage value of the voltage between the second drain and the first source.

2. The method of claim 1, wherein the LDMOS equivalent circuit is established by, The resistance value of the drain parasitic resistance is related to the difference between the first correction value and the second correction value.

3. The method of claim 1, wherein the LDMOS equivalent circuit is established by, The first correction value contains parameters for fitting the first region, and the first region comprises the transition region and the quasi-saturation region.

4. The method of creating an equivalent circuit of an LDMOS transistor of claim 3, wherein, The first correction value also contains parameters for fitting the quasi-saturation region.

5. The method of creating an equivalent circuit of an LDMOS transistor of claim 1, wherein, the first correction value ; Wherein, ec1 is a mathematical correction coefficient, parameters for fitting the first region, the first region includes the transition region and the quasi-saturation region; v(d,s) is the voltage value of the voltage between the first drain and the first source; exp is an exponential correction coefficient, parameters for fitting the quasi-saturation region.

6. The method of creating an equivalent circuit of an LDMOS transistor of claim 5, wherein, Also comprising: The measured data of the LDMOS tube and the simulation results of the equivalent circuit of the LDMOS tube are compared to adjust the parameters ec1, ec2 and exp, so as to obtain the fitting results.

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