Memory cell, method of manufacturing memory device, and operating method thereof

Abstract

The present disclosure provides an integrated memory cell, a manufacturing method of a memory device, and an operating method thereof. The integrated memory cell includes a first memory cell and an embedded second memory cell connected in series to the first memory cell, wherein the embedded second memory cell is formed on either a first side or a second side of the first memory cell.

Description

Technical Field

[0001] This invention relates to a memory cell, a method for manufacturing a memory device and a method for operating the memory device, and particularly to a memory cell that integrates a flash memory cell and an embedded non-volatile memory cell, as well as a method for manufacturing a memory device and a method for operating the memory device. Background Technology

[0002] NOR flash memory cells have advantages such as random access, short read time and zero bit error rate (BER), making them suitable for storing data.

[0003] Embedded nonvolatile memory (NVM) offers advantages such as random access, low manufacturing cost, and low operating power consumption.

[0004] Flash memory cells can be single-level cells (SLC), multi-level cells (MLC), or higher-level cells. However, detecting flash memory cells with multiple states requires multiple read operations, resulting in long read times. For example, reading an MLC cell requires two read operations. Furthermore, NOR flash memory is typically implemented as SLC to improve data storage reliability.

[0005] Therefore, it would be even more beneficial if a multi-state memory cell could combine the advantages of both flash memory and embedded non-volatile memory cells, and whose storage state could be read in a single read operation.

[0006] Public content

[0007] According to one embodiment of this disclosure, an integrated memory cell is proposed, comprising: a first memory cell; and an embedded second memory cell connected in series with the first memory cell, wherein the embedded second memory cell is formed on either a first side or a second side of the first memory cell.

[0008] According to another embodiment of this disclosure, a method for manufacturing a memory device is proposed, comprising: forming a plurality of first memory cells; forming a plurality of contacts; and forming a plurality of embedded second memory cells on either a first side or a second side of the first memory cells.

[0009] According to a further embodiment of this disclosure, an operation method for a memory device is proposed. The memory device includes a plurality of integrated memory cells, each integrated memory cell including a first memory cell and an embedded second memory cell. The operation method includes: when performing a first programming operation on the first memory cell, applying a first programming voltage to a first terminal of the selected integrated memory cell; and when performing a second programming operation on the embedded second memory cell, applying a second programming voltage to the first terminal of the selected integrated memory cell and applying a third programming voltage to a second terminal of the integrated memory cell.

[0010] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0011] Figure 1 This illustrates an integrated memory cell having multiple storage states according to an embodiment of the present disclosure.

[0012] Figures 2A to 2C This shows a cross-sectional view of an integrated memory cell 100 according to several embodiments of the present disclosure.

[0013] Figure 3A and Figure 3B Two architectural diagrams of a memory array according to an embodiment of the present disclosure are shown.

[0014] Figure 4A and Figure 4B This invention illustrates two memory arrays according to an embodiment of the present disclosure.

[0015] Figure 5 A flowchart showing a method for manufacturing a memory device according to an embodiment of the present disclosure is displayed.

[0016] Figures 6A to 6D This illustrates a process flow for forming an embedded non-volatile memory cell according to an embodiment of the present disclosure.

[0017] Figures 7A to 7D This illustrates a process flow for forming an embedded non-volatile memory cell according to an embodiment of the present disclosure.

[0018] Figures 8A to 8D This invention illustrates a method of operating a memory device according to an embodiment of the present disclosure.

[0019] Figures 9A to 9D This invention illustrates a method of operating a memory device according to an embodiment of the present disclosure.

[0020] Figure 10 This diagram illustrates the reading of a memory device according to an embodiment of the present disclosure.

[0021] Figure 11A This diagram illustrates the execution logic and operations of an integrated memory cell according to an embodiment of the present disclosure. Figure 11B This diagram illustrates an integrated memory cell performing a logical NOR operation according to an embodiment of the present disclosure.

[0022] Figure 12 This illustrates a two-level integrated memory cell according to an embodiment of the present disclosure.

[0023] Figure 13 This illustrates a two-level integrated memory cell according to an embodiment of the present disclosure.

[0024] Explanation of reference numerals in the attached figures

[0025] 100: Integrated memory unit

[0026] 110: First memory unit

[0027] 120: Embedded Second Memory Unit

[0028] C: Contact

[0029] V: Perforation

[0030] D: Drain electrode

[0031] S: Source

[0032] G: Gate

[0033] B: Base

[0034] ML: Metal wire

[0035] 300A, 300B: Memory Array

[0036] WL1~WL3: Word lines

[0037] BL1~BL3: Bit lines

[0038] SL1~SL3: Source lines

[0039] SA1~SA3: Induction Amplifier

[0040] CSL: Common Source Line

[0041] 400A, 400B: Memory array

[0042] 410A, 420A: Memory subarray

[0043] 510-550: Steps

[0044] 610: Photoresist layer

[0045] 710: ReRAM thin film

[0046] 720: Top electrode layer

[0047] 730: Photoresist layer

[0048] 740: Protective layer

[0049] 1110~1140: Table Detailed Implementation

[0050] The technical terms used in this specification refer to those commonly used in the field. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each embodiment of this disclosure has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0051] Figure 1 This disclosure illustrates an integrated memory cell with multiple storage states according to an embodiment of the present disclosure. The integrated memory cell 100 with multiple storage states according to an embodiment of the present disclosure includes: a first memory cell 110 and an embedded second memory cell 120. The first memory cell 110 and the embedded second memory cell 120 are, for example, but not limited to, flash memory cells and embedded non-volatile memory cells. The flash memory cell 110 has a gate terminal, a drain terminal, a source terminal, and a body terminal. The embedded non-volatile memory cell 120 has a first terminal and a second terminal. The flash memory cell 110 and the embedded non-volatile memory cell 120 are connected in series. The integrated memory cell 100 has four terminals: a first terminal (the gate terminal of the flash memory cell 110), a second terminal (the first terminal of the embedded non-volatile memory cell 120), a third terminal (the source terminal of the flash memory cell 110), and a fourth terminal (the body terminal of the flash memory cell 110). Furthermore, the drain terminal of the flash memory cell 110 is coupled to the second terminal of the embedded non-volatile memory cell 120. The voltages applied to the first, second, third, and fourth terminals of the integrated memory cell 100 can be referred to as the first terminal voltage Vg (also known as the gate voltage), the second terminal voltage Vd (also known as the drain voltage), the third terminal voltage Vs (also known as the source voltage), and the fourth terminal voltage Vb (also known as the body voltage).

[0052] In one embodiment of this disclosure, the flash memory cell 110 may be, for example but not limited to, a charge storage memory (such as a floating gate flash memory), a charge trapping memory (such as a silicon-oxide-nitride-oxide-silicon (SONOS) memory), or a ferroelectric-gated field-effect transistor (FeFET) memory.

[0053] In one embodiment of this disclosure, the embedded non-volatile memory cell 120 may be, for example but not limited to, resistive random-access memory (RRAM or ReRAM), conductive-bridging random access memory (CBRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), ferroelectric tunnel junction (FTJ) memory, etc.

[0054] Figures 2A to 2C The diagram shows a cross-sectional view of an integrated memory cell 100 according to several embodiments of the present disclosure. In one embodiment of the present disclosure, an embedded non-volatile memory cell 120 may be formed on either the drain side (D) or the source side (S) of a flash memory cell 110. The following description uses the example of the embedded non-volatile memory cell 120 being formed on the drain side of the flash memory cell 110 as an example, from which it can be deduced how the embedded non-volatile memory cell 120 can be formed on the source side of the flash memory cell 110. The gate (G) of the flash memory cell 110 includes a control gate, an oxide layer, a floating gate, and a tunnel oxide layer. Herein, B represents the substrate, and ML represents a metal line.

[0055] like Figure 2AAs shown, the embedded non-volatile memory cell 120 is formed at the bottom of the contact C. As... Figure 2B As shown, the embedded non-volatile memory cell 120 is formed at the top of the contact C. Figure 2C As shown, the embedded non-volatile memory cell 120 is formed at the top of the through-hole V. In other embodiments, the embedded non-volatile memory cell 120 is formed at the bottom of the through-hole V, which is also within the spirit of this disclosure.

[0056] Figure 3A and Figure 3B Two architectural diagrams of a memory array according to an embodiment of the present disclosure are shown.

[0057] like Figure 3A As shown, the memory array 300A is an AND type array. The memory array 300A includes: multiple integrated memory cells 100 arranged in an array, multiple word lines (WL1~WL3…), multiple bit lines (BL1~BL3…), multiple source lines (SL1~SL3…), and multiple sense amplifiers (SA1~SA3…).

[0058] like Figure 3B As shown, the memory array 300B is a NOR array. The memory array 300B includes: multiple integrated memory cells 100 arranged in an array, multiple word lines (WL1~WL3…), multiple bit lines (BL1~BL3…), multiple source lines (SL1~SL3…), a common source line CSL, and multiple sense amplifiers (SA1~SA3…).

[0059] Figure 4A and Figure 4B Two memory arrays according to an embodiment of the present disclosure are shown. For example... Figure 4A As shown, memory array 400A includes memory subarray 410A and memory subarray 420A. Each memory cell of memory subarray 410A includes flash memory cell 110 and embedded non-volatile memory cell 120; and each memory cell of memory subarray 420A includes flash memory cell 110 (but does not include embedded non-volatile memory cell 120).

[0060] like Figure 4B As shown, each memory cell of the memory array 400B includes a flash memory cell 110 and an embedded non-volatile memory cell 120.

[0061] Figure 5This diagram shows a flowchart of a method for manufacturing a memory device according to an embodiment of the present disclosure. In step 510, a front-end of line (FEOL) process is performed to form a plurality of flash memory cells. In step 520, a plurality of contacts are formed. In step 530, a plurality of embedded non-volatile memory cells are formed on either the drain side or the source side of these flash memory cells. In step 540, at least one metal line is deposited. In step 550, a back-end of line (BEOL) process is performed.

[0062] The details of forming the embedded non-volatile memory cell according to embodiments of this disclosure (i.e., the details of step 530) will now be described. Please refer to Figures 6A to 6D and Figures 7A to 7D .

[0063] Figures 6A to 6D This illustration shows a process flow for forming an embedded non-volatile memory cell according to an embodiment of the present disclosure. The embedded non-volatile memory cell is described here as an example of ReRAM, but it should be understood that the present disclosure is not limited thereto.

[0064] At Figure 6A In the process, a photoresist (PR) layer 610 is deposited on the flash memory cell. Figure 6B In the process, the photoresist layer 610 is etched to expose the contact region on the drain side (or source side) of the flash memory cell. Figure 6C In this process, plasma oxidation is performed to form embedded non-volatile memory cells (ReRAM is used as an example in this case) on the drain side (or source side) of the flash memory cell. Figure 6D In the middle, the photoresist layer 610 is removed.

[0065] Figures 7A to 7D This illustration shows a process flow for forming an embedded non-volatile memory cell according to an embodiment of the present disclosure. The embedded non-volatile memory cell is described here as an example of ReRAM, but it should be understood that the present disclosure is not limited thereto.

[0066] At Figure 7A In this process, a ReRAM thin film 710 and a top electrode layer 720 are deposited on the flash memory cell. Figure 7B A photoresist layer 730 is deposited on top electrode layer 720, and the photoresist layer 730 is etched to expose the contact region on the drain side (or source side) of the flash memory cell. Figure 7C In the process, the photoresist layer 730 is removed and a protective layer 740 is deposited (e.g., but not limited to, silicon nitride (SiN) or silicon dioxide (SiO2)). Figure 7D In the middle, a protective layer 740 is etched to form a side wall protection.

[0067] Figures 8A to 8D This disclosure shows an operation method of a memory device according to an embodiment of the present disclosure, applicable to memory arrays of type A and B arrays. Figure 3A ). Figure 8A Displays programming operations on flash memory cells; Figure 8B Displays programming operations on the embedded non-volatile memory cell; Figure 8C This shows the block erase operation on the flash memory cell; and, Figure 8D This displays the erase operation performed on an embedded non-volatile memory cell. Figures 8A to 8D In this context, programming operations on flash memory cells are independent of programming operations on embedded non-volatile memory cells; and block erasure operations on flash memory cells are independent of erasure operations on embedded non-volatile memory cells.

[0068] At Figure 8A In the process of programming a flash memory cell, for the selected cell, the gate voltage Vg is the first programming voltage (e.g., but not limited to +18V), the drain voltage Vd and the source voltage Vs are 0V (grounded), and the body voltage Vb is floating; for the unselected cell, the gate voltage Vg is 0V, and the drain voltage Vd, the source voltage Vs and the body voltage Vb are floating.

[0069] At Figure 8B In the process of programming embedded non-volatile memory cells, for selected cells, the gate voltage Vg is the second programming voltage (e.g., but not limited to +6V), the drain voltage Vd is the third programming voltage (e.g., but not limited to +5V), and the source voltage Vs and the body voltage Vb are 0V; for unselected cells, the gate voltage Vg, drain voltage Vd, source voltage Vs and the body voltage Vb are 0V.

[0070] At Figure 8C In the process of performing a block erase operation on a flash memory cell, the gate voltage Vg is the first erase voltage (e.g., but not limited to -9V), the body voltage Vb is the second erase voltage (e.g., but not limited to +9V), and the drain voltage Vd and the source voltage Vs are floating.

[0071] At Figure 8DIn the process of erasing embedded non-volatile memory cells, for selected cells, the gate voltage Vg is the third erase voltage (e.g., but not limited to +6V), the source voltage Vs is the fourth erase voltage (e.g., but not limited to +5V), and the drain voltage Vd and the body voltage Vb are 0V; for unselected cells, the gate voltage Vg, drain voltage Vd, source voltage Vs and the body voltage Vb are 0V.

[0072] Figures 9A to 9D This disclosure shows an operation method of a memory device according to an embodiment of the present disclosure, applicable to memory arrays of NOR type arrays. Figure 3B ). Figure 9A Displays programming operations on flash memory cells; Figure 9B Displays programming operations on the embedded non-volatile memory cell; Figure 9C This shows the block erase operation on the flash memory cell; and, Figure 9D This displays the erase operation performed on an embedded non-volatile memory cell. Figures 9A to 9D In this context, programming operations on flash memory cells are independent of programming operations on embedded non-volatile memory cells; and block erasure operations on flash memory cells are independent of erasure operations on embedded non-volatile memory cells.

[0073] At Figure 9A In the process of programming a flash memory cell, for the selected cell, the gate voltage Vg is the first programming voltage (e.g., but not limited to +18V), the drain voltage Vd is 0V, and the source voltage Vs and the body voltage Vb are floating; for the unselected cell, the gate voltage Vg is 0V, and the drain voltage Vd, the source voltage Vs and the body voltage Vb are floating.

[0074] At Figure 9B In the process of programming embedded non-volatile memory cells, for selected cells, the gate voltage Vg is the second programming voltage (e.g., but not limited to +6V), the drain voltage Vd is the third programming voltage (e.g., but not limited to +5V), and the source voltage Vs and the body voltage Vb are 0V; for unselected cells, the gate voltage Vg, drain voltage Vd, source voltage Vs and the body voltage Vb are 0V.

[0075] At Figure 9C In the process of performing a block erase operation on a flash memory cell, the gate voltage Vg is the first erase voltage (e.g., but not limited to -9V), the body voltage Vb is the second erase voltage (e.g., but not limited to +9V), and the drain voltage Vd and the source voltage Vs are floating.

[0076] At Figure 9DIn the process of erasing embedded non-volatile memory cells, for selected cells, the gate voltage Vg is the third erase voltage (e.g., but not limited to +6V), the source voltage Vs is the fourth erase voltage (e.g., but not limited to +5V), and the drain voltage Vd and the body voltage Vb are 0V; for unselected cells, the gate voltage Vg and the body voltage Vb are 0V, the drain voltage Vd is floating, and the source voltage Vs is the fourth erase voltage.

[0077] Figure 10 This diagram illustrates the reading of a memory device according to an embodiment of the present disclosure, wherein both the flash memory cell and the embedded non-volatile memory cell (ReRAM is used as an example here) are SLC (single-level cell), but the integrated memory cell 100 can generate a third-order output current. Figure 10 In this context, "A" represents an SLC flash memory cell, "B" represents an SLC embedded non-volatile memory cell, and "C" represents a third-order output current.

[0078] Flash memory cell (A) has storage states of logic 1 and logic 0, wherein when flash memory cell (A) is programmed to a high threshold voltage, flash memory cell (A) stores logic 0; and when flash memory cell (A) is programmed to a low threshold voltage, flash memory cell (A) stores logic 1.

[0079] ReRAM(B) has storage states of logic 1 and logic 0. When ReRAM(B) is programmed to a high resistance state (HRS), ReRAM(B) stores logic 0; and when ReRAM(B) is programmed to a low resistance state (LRS), ReRAM(B) stores logic 1.

[0080] During reading, the gate voltage Vg is the reference voltage Vref (between the high and low threshold voltages of the flash memory cell (A), the source voltage Vs is 0V, the drain voltage Vd is the read voltage Vread, and the body voltage Vb is 0V. Depending on the storage state of the flash memory cell (A) and the ReRAM (B), the sensed output current has three orders: low current, high current, and no current.

[0081] When flash memory cell (A) is programmed to a low threshold voltage, since the gate voltage Vg is the reference voltage Vref (between the high and low threshold voltages of flash memory cell (A)), flash memory cell (A) is turned on, and the output current (C) depends on the resistance of ReRAM (B). When ReRAM (B) is in a high impedance state (ReRAM (B) stores logic 0), the output current (C) is low; and when ReRAM (B) is in a low impedance state (ReRAM (B) stores logic 1), the output current (C) is high.

[0082] Furthermore, when the flash memory cell (A) is programmed to a high threshold voltage, since the gate voltage Vg is the reference voltage Vref (between the high threshold voltage and the low threshold voltage of the flash memory cell (A)), the flash memory cell (A) is turned off and no current flows through it.

[0083] Therefore, from Figure 10 As can be seen, in one embodiment of this disclosure, integrating the SLC flash memory cell and the SLC embedded non-volatile memory cell can generate a third-order output current.

[0084] Furthermore, the integrated memory unit 100 of one embodiment of this disclosure can perform logical AND operations and logical NOR operations. Figure 11A This diagram illustrates the execution logic and operations of an integrated memory cell according to an embodiment of the present disclosure. Figure 11B This diagram illustrates an integrated memory cell performing a logical NOR operation according to an embodiment of the present disclosure.

[0085] Please refer to Figure 10 and Figure 11A For example, but not limited to, setting the output current reference value Iref to... Figure 10 The output state is logic 1 when the output current is higher than the output current reference value Iref, and logic 0 when the output current is lower than the output current reference value Iref. The logic 1 and logic 0 definitions of flash memory cell (A) and ReRAM (B) are shown in Table 1110, and the output state (C) is shown in Table 1120.

[0086] When the flash memory cell (A) is logic 1 (flash memory cell (A) is on) and the ReRAM (B) is logic 0 (ReRAM (B) is HRS), the output current is low (lower than the output current reference value Iref), so the output state C is logic 0.

[0087] When the flash memory cell (A) is logic 1 (flash memory cell (A) is on) and the ReRAM (B) is logic 1 (ReRAM (B) is LRS), the output current is high (higher than the output current reference value Iref), so the output state C is logic 1.

[0088] When flash memory cell (A) is logic 0 (flash memory cell (A) is off), regardless of whether ReRAM (B) is logic 1 or logic 0, the output current is zero (lower than the output current reference value Iref), so the output state C is logic 0.

[0089] Therefore, as can be seen from Table 1120, the output state C is the result of the logic and operation of A and B.

[0090] Please refer to Figure 10 and Figure 11B For example, but not limited to, setting the output current reference value Iref to... Figure 10 The output state is logic 1 when the output current is higher than the output current reference value Iref, and logic 0 when the output current is lower than the output current reference value Iref. The definitions of logic 1 and logic 0 for flash memory cell (A) and ReRAM (B) are shown in Table 1130, and the output state (C) is shown in Table 1140.

[0091] When the flash memory cell (A) is logic 0 (flash memory cell (A) is on) and the ReRAM (B) is logic 0 (ReRAM (B) is LRS), the output current is high (higher than the output current reference value Iref), so the output state C is logic 1.

[0092] When the flash memory cell (A) is logic 0 (flash memory cell (A) is on) and the ReRAM (B) is logic 1 (ReRAM (B) is HRS), the output current is low (lower than the output current reference value Iref), so the output state C is logic 0.

[0093] When flash memory cell (A) is logic 1 (flash memory cell (A) is off), regardless of whether ReRAM (B) is logic 1 or logic 0, the output current is zero (lower than the output current reference value Iref), so the output state C is logic 0.

[0094] Therefore, as shown in Table 1140, the output state C is the result of the logical NOR operation between A and B.

[0095] In one embodiment of this disclosure, the integrated memory cell may have a physically unclonable function (PUF).

[0096] To perform the PUF function, the embedded non-volatile memory unit 120 can be programmed to store random PUF codes; and the flash memory unit 110 can be programmed to determine whether to select the random PUF codes stored in the embedded non-volatile memory unit 120.

[0097] For example, to perform the PUF function, the logic 1 and logic 0 of the flash memory cell (A) and ReRAM (B) are defined as shown in the table below.

[0098]

[0099] The output status (or output current) (C) is shown in the table below.

[0100] A (Flash memory cell) B(ReRAM) C (Output status or output current) 1 0 0 (Low Current) 1 1 1 (High Current) 0 0 No current 0 1 No current

[0101] When the random PUF code stored in the embedded non-volatile memory cell 120 is not selected, the flash memory cell 110 is programmed to a high threshold state (off state, with high resistance). In this way, there will be no output current.

[0102] When the random PUF code stored in the embedded non-volatile memory cell 120 is selected, the flash memory cell 110 is programmed to a low threshold state (on state, with low resistance). In this way, the output current can be detected as high or low to determine whether the random PUF code stored in the embedded non-volatile memory cell 120 is logic 1 or logic 0.

[0103] In one embodiment of this disclosure, a combination of single-level or multi-level flash memory cells and single-level or multi-level embedded non-volatile memory cells can be used to realize a multi-level cell (MLC) integrated memory cell or a higher-level integrated memory cell.

[0104] Figure 12 This invention discloses a two-level integrated memory cell according to an embodiment of the present disclosure, wherein the two-level integrated memory cell is implemented by a combination of a single-level flash memory cell and a second-level embedded non-volatile memory cell.

[0105] At Figure 12In the context of single-level flash memory, when a single-level flash memory cell is programmed to high Vt and low Vt, the single-level flash memory cell has high resistance and low resistance, respectively. When a second-level embedded non-volatile memory cell is programmed to HRS, MRS (middle resistance state), and LRS, the second-level embedded non-volatile memory cell has high resistance, medium resistance, and low resistance, respectively.

[0106] During reading, the gate voltage Vg = Vref and the drain voltage Vd = Vread.

[0107] When a single-level flash memory cell is programmed to high Vt (a second-level flash memory cell has high resistance), regardless of whether the second-level embedded non-volatile memory cell is programmed to HRS, MRS, or LRS, the output state (output current) is no current (i.e., state 0 (S0)).

[0108] When a single-level flash memory cell is programmed to low Vt (the single-level flash memory cell has low resistance) and a second-level embedded non-volatile memory cell is programmed to HRS, the output state (output current) is state 1 (S1).

[0109] When a single-level flash memory cell is programmed to low Vt (the single-level flash memory cell has low resistance) and a second-level embedded non-volatile memory cell is programmed to MRS, the output state (output current) is state 2 (S2).

[0110] When a single-level flash memory cell is programmed to low Vt (the single-level flash memory cell has low resistance) and a second-level embedded non-volatile memory cell is programmed to LRS, the output state (output current) is state 3 (S3).

[0111] The output current is ordered from highest to lowest as follows: S3 > S2 > S1 > S0. That is, the output current in state 3 (S3) is higher than the output current in state 2 (S2), and so on.

[0112] As explained above, the output state has four states, and the integrated memory unit is of level 2. That is, the integrated memory unit can be used to store two bits.

[0113] Examples are given below. This disclosure is not limited thereto.

[0114] At Figure 12In the context of single-level flash memory, when a single-level flash memory cell is programmed to high Vt and low Vt, the single-level flash memory cell has a high resistance (100 GΩ) and a low resistance (5 kΩ), respectively. When a second-level embedded non-volatile memory cell is programmed to HRS, MRS, and LRS, the second-level embedded non-volatile memory cell has a high resistance (500 kΩ), a medium resistance (100 kΩ), and a low resistance (20 kΩ), respectively.

[0115] The relationship between flash memory cells, embedded non-volatile memory cells, and output states (equivalent resistance) is shown in the table below (output states and output current can be determined based on equivalent resistance).

[0116]

[0117]

[0118] When a single-level flash memory cell is programmed to high Vt (a single-level flash memory cell has a high resistance (100 GΩ)) and a second-level embedded non-volatile memory cell is programmed to HRS (500 kΩ), the equivalent resistance of the integrated memory cell is approximately 100 GΩ. Therefore, the output state is S0 (no output current). The rest can be deduced similarly.

[0119] Figure 13 This invention discloses a two-level integrated memory cell according to an embodiment of the present disclosure, wherein the two-level integrated memory cell is implemented by a combination of a two-level flash memory cell and a single-level embedded non-volatile memory cell.

[0120] At Figure 13 In the context of a second-order flash memory cell, when programmed with high Vt, medium Vt, and low Vt, the second-order flash memory cell has high resistance, medium resistance, and low resistance, respectively. Similarly, when a single-order embedded non-volatile memory cell is programmed with HRS and LRS, the single-order embedded non-volatile memory cell has high resistance and low resistance, respectively.

[0121] During reading, the gate voltage Vg = Vref and the drain voltage Vd = Vread.

[0122] When a second-order flash memory cell is programmed to high Vt (a second-order flash memory cell has a high resistance), regardless of whether a single-order embedded non-volatile memory cell is programmed to HRS or LRS, the output state (output current) is no current (i.e., state 0 (S0)).

[0123] When the second-order flash memory cell is programmed to medium Vt (the second-order flash memory cell has medium resistance) and the single-order embedded non-volatile memory cell is programmed to HRS, the output state (output current) is state 1 (S1).

[0124] When the second-order flash memory cell is programmed to medium Vt (the second-order flash memory cell has medium resistance) and the single-order embedded non-volatile memory cell is programmed to LRS, the output state (output current) is state 2 (S2).

[0125] When the second-order flash memory cell is programmed to low Vt (the second-order flash memory cell has low resistance) and the single-order embedded non-volatile memory cell is programmed to HRS, the output state (output current) is state 1 (S1).

[0126] When the second-order flash memory cell is programmed to low Vt (the second-order flash memory cell has low resistance) and the single-order embedded non-volatile memory cell is programmed to LRS, the output state (output current) is state 3 (S3).

[0127] As explained above, the output state has four states, and the integrated memory unit is of level 2. That is, the integrated memory unit can be used to store two bits.

[0128] Examples are given below. This disclosure is not limited thereto.

[0129] At Figure 13 In the above, when a second-order flash memory cell is programmed with high Vt, medium Vt, and low Vt, the second-order flash memory cell has a high resistance (100 GΩ), a medium resistance (50 kΩ), and a low resistance (5 kΩ), respectively. When a single-order embedded non-volatile memory cell is programmed with HRS and LRS, the single-order embedded non-volatile memory cell has a high resistance (200 kΩ) and a low resistance (20 kΩ), respectively.

[0130] The relationship between flash memory cells, embedded non-volatile memory cells, and equivalent resistance (output state, output current) is shown in the table below (output state and output current can be determined by equivalent resistance):

[0131]

[0132] When a second-order flash memory cell is programmed to high Vt (with high resistance (100 GΩ)) and a single-order embedded non-volatile memory cell is programmed to HRS (200 kΩ), the equivalent resistance of the integrated memory cell is approximately 100 GΩ, and the output state is S0 (no output current). The rest can be deduced similarly.

[0133] As described in the above embodiments, the present disclosure integrates flash memory cells and embedded non-volatile memory cells, resulting in a relatively simple manufacturing process. Furthermore, the integrated memory cell combines the advantages of both flash memory cells and embedded non-volatile memory cells. For example, but not limited to, NOR flash memory cells offer advantages such as random access, short read times, and zero-bit error rates; therefore, flash memory cells are suitable for storing data. Embedded non-volatile memory offers advantages such as random access, low manufacturing costs, and low operating power consumption.

[0134] As can be seen from the above embodiments, the integrated memory device can be a NOR type memory device or an AND type memory device.

[0135] As described in the above embodiments, the integrated memory cell can perform logical AND / OR logical NOR operations. Therefore, the integrated memory cell of this disclosure can be applied to in-memory computing.

[0136] As can be seen from the above embodiments, the integrated memory unit can perform PUF function, and therefore, it can be applied to random number generators (RNG) or used as a seed for random number generators.

[0137] As can be seen from the above embodiments, a single-level flash memory cell and a single-level embedded non-volatile memory cell can generate at least three output states.

[0138] As can be seen from the above embodiments, single-level or higher-level flash memory cells and single-level or higher-level embedded non-volatile memory cells can be combined to form integrated memory cells of level 2 or higher (SLC, MLC, TLC (triple-level cell), QLC (Quad-level cell) or higher).

[0139] Furthermore, when reading integrated memory cells of level 2 or higher, only one read operation is needed to obtain their output status, thus reducing the read time.

[0140] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention shall be determined by the appended claims.

Claims

1. An integrated memory cell, characterized in that, include: A first memory unit; as well as An embedded second memory cell is connected in series with the first memory cell. The embedded second memory cell is formed on either a first side or a second side of the first memory cell; The embedded second memory cell is formed on a bottom or top of a contact, or on a bottom or top of a through-hole; and The embedded second memory cell is embedded in the source / drain region of the first memory cell, with the top surface of the embedded second memory cell above the top surface of the source / drain region and the bottom surface of the embedded second memory cell below the top surface of the source / drain region.

2. The integrated memory cell according to claim 1, characterized in that, The first memory cell is a flash memory cell, and the embedded second memory cell is an embedded non-volatile memory cell.

3. The integrated memory cell according to claim 1, characterized in that, This integrated memory unit performs logical AND operations, and logical NOR operations; The integrated memory cell performs a physically unclonable function (PUF) to be used in a random number generator or as a sub-generator of that random number generator. When the first memory cell is a single-level flash memory cell and the embedded second memory cell is a single-level embedded non-volatile memory cell, the integrated memory cell generates at least three output states. as well as The first memory cell, which is of single or higher order, is combined with the embedded second memory cell, which is of single or higher order, to form the integrated memory cell, which is of 2nd or higher order.

4. A method for manufacturing a memory device, the memory device comprising a plurality of integrated memory cells as described in any one of claims 1 to 3, characterized in that, include: Multiple first memory units are formed; Multiple contacts are formed; as well as Multiple embedded second memory cells are formed on either a first side or a second side of these first memory cells.

5. The method for manufacturing a memory device according to claim 4, characterized in that, The memory device is a NOR type memory device or an AND type memory device; The step of forming these embedded second memory cells includes: A photoresist layer is deposited on these first memory cells; The photoresist layer is etched to expose a contact area; Plasma oxidation is performed to form these embedded second memory cells; and Remove the photoresist layer.

6. The method for manufacturing a memory device according to claim 4, characterized in that, The step of forming these embedded second memory cells includes: A memory cell thin film layer and a top electrode layer are deposited on these first memory cells; A photoresist layer is deposited on the top electrode layer, and the photoresist layer is etched to expose a contact area; Remove the photoresist layer and deposit a protective layer; and The protective layer is etched to form a sidewall protection.

7. A method of operating a memory device, the memory device comprising a plurality of integrated memory cells as described in any one of claims 1 to 3, each integrated memory cell comprising a first memory cell and an embedded second memory cell, the method comprising: When performing a first programming operation on the first memory cell, for a selected integrated memory cell, a first programming voltage is applied to a first terminal of the integrated memory cell; and When performing a second programming operation on the embedded second memory cell, a second programming voltage is applied to the first terminal of the selected integrated memory cell and a third programming voltage is applied to the second terminal of the integrated memory cell.

8. The method of operating the memory device according to claim 7, characterized in that, When performing the first programming operation on the first memory cell, for the selected integrated memory cell, the first programming voltage is applied to the first terminal of the integrated memory cell, 0V is applied to the second and a third terminal of the integrated memory cell, and a fourth terminal of the integrated memory cell is made floating; for an unselected integrated memory cell, 0V is applied to the first terminal, and the second, third, and fourth terminals are made floating. When performing the second programming operation on the embedded second memory cell, for the selected integrated memory cell, the second programming voltage is applied to the first terminal and the third programming voltage is applied to the second terminal, and 0V is applied to the third terminal and the fourth terminal; for the unselected integrated memory cell, 0V is applied to the first terminal, the second terminal, the third terminal and the fourth terminal. When performing a block erase operation on these first memory cells, a first erase voltage is applied to these first terminals, the second terminals and the third terminals are made to float, and a second erase voltage is applied to these fourth terminals. as well as When performing an erase operation on the embedded second memory cell, for the selected integrated memory cell, a third erase voltage is applied to the first terminal, a fourth erase voltage is applied to the third terminal, and 0V is applied to the second terminal and the fourth terminal; for the unselected integrated memory cell, 0V is applied to the first terminal, the second terminal, the third terminal and the fourth terminal.

9. The method of operating the memory device according to claim 7, characterized in that, When performing the first programming operation on the first memory cell, for the selected integrated memory cell, the first programming voltage is applied to the first terminal, 0V is applied to the second terminal, and a third terminal and a fourth terminal are floated; for an unselected integrated memory cell, 0V is applied to the first terminal, and the second terminal, the third terminal and the fourth terminal are floated. When performing the second programming operation on the embedded second memory cell, for the selected integrated memory cell, the second programming voltage is applied to the first terminal and the third programming voltage is applied to the second terminal, and 0V is applied to the third terminal and the fourth terminal; for the unselected integrated memory cell, 0V is applied to the first terminal, the second terminal, the third terminal and the fourth terminal. When performing a block erase operation on these first memory cells, a first erase voltage is applied to these first terminals, the second terminals and the third terminals are made to float, and a second erase voltage is applied to these fourth terminals. as well as When performing an erase operation on the embedded second memory cell, for the selected integrated memory cell, a third erase voltage is applied to the first terminal, a fourth erase voltage is applied to the third terminal, and 0V is applied to the second terminal and the fourth terminal; for the unselected integrated memory cell, 0V is applied to the first terminal and the fourth terminal, the second terminal is made to float, and the fourth erase voltage is applied to the third terminal.

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