Method of manufacturing a semiconductor structure
By using a patterned photoresist layer as a mask in semiconductor structure manufacturing, controlling the etch rate ratio, and integrating the manufacturing process of memory and logic element areas, the problems of high semiconductor process complexity and cost are solved, achieving process simplification and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNITED MICROELECTRONICS CORP
- Filing Date
- 2021-07-20
- Publication Date
- 2026-05-12
AI Technical Summary
The complexity and cost of semiconductor manufacturing processes are constantly increasing, especially when there are different component areas on the chip.
By using a patterned photoresist layer as a mask during the semiconductor structure manufacturing process, the hard mask layer and dielectric material layer in the first and second regions are removed respectively, the etch rate ratio is controlled, the device manufacturing process is integrated, and the number of manufacturing steps and photomasks is reduced.
It reduces the complexity of the manufacturing process and manufacturing costs, simplifies the process flow, reduces the use of photomasks, and improves production efficiency.
Smart Images
Figure CN115938917B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure that can reduce the complexity of the manufacturing process and the manufacturing cost. Background Technology
[0002] With advancements in semiconductor technology, semiconductor manufacturing processes are becoming increasingly complex, and production costs are constantly rising. Furthermore, the presence of different component regions on the chip further increases the complexity of the manufacturing process. Therefore, reducing manufacturing complexity and costs remains a continuous goal. Summary of the Invention
[0003] This invention provides a method for manufacturing a semiconductor structure, which can reduce the complexity of the manufacturing process and the manufacturing cost.
[0004] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductor layer, and a first hard mask layer. The first dielectric layer is located on the substrate. The charge storage layer is located on the first dielectric layer. The second dielectric layer is located on the charge storage layer. The first conductor layer is located on the second dielectric layer. The first hard mask layer is located on the first conductor layer. A dielectric material layer is formed on the substrate in the second region. A second conductor layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed, wherein the first patterned photoresist layer exposes the first hard mask layer in the first region and a portion of the dielectric material layer in the second region. Using the first patterned photoresist layer as a mask, the first hard mask layer and the portion of the dielectric material layer exposed by the first patterned photoresist layer are removed.
[0005] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the method for removing the first hard mask layer exposed by the first patterned photoresist layer and the portion of the dielectric material layer exposed by the first patterned photoresist layer may include performing an etching process.
[0006] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, in the above-described etching process, the ratio of the etching rate of the first hard mask layer to the etching rate of the dielectric material layer can be in the range of 1.5 to 1.
[0007] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, in the above-described etching process, the ratio of the etching rate of the first hard mask layer to the etching rate of the dielectric material layer can be in the range of 1.3 to 1.
[0008] According to one embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the etching process is, for example, a dry etching process.
[0009] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the first patterned photoresist layer may cover a portion of the first hard mask layer.
[0010] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, after removing the first hard mask layer exposed by the first patterned photoresist layer, a portion of the first hard mask layer covered by the first patterned photoresist layer may remain.
[0011] According to an embodiment of the present invention, in the above-described method for manufacturing the semiconductor structure, the stacked structure may further include a second hard mask layer. The second hard mask layer is located between the first hard mask layer and the first conductor layer. After removing the first hard mask layer exposed by the first patterned photoresist layer, the first patterned photoresist layer may expose the second hard mask layer.
[0012] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following step: using a first patterned photoresist layer as a mask, removing the second hard mask layer exposed by the first patterned photoresist layer.
[0013] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the first patterned photoresist layer may cover a portion of the second hard mask layer.
[0014] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, after removing the second hard mask layer exposed by the first patterned photoresist layer, a portion of the second hard mask layer covered by the first patterned photoresist layer may remain.
[0015] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following steps: After removing a portion of the dielectric material layer exposed by the first patterned photoresist layer, two doped regions are formed in the substrate on both sides of the second conductor layer using the first patterned photoresist layer as a mask.
[0016] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following step: After forming the doped region, the first patterned photoresist layer is removed.
[0017] According to an embodiment of the present invention, in the above-described method for manufacturing a semiconductor structure, the method for forming a second conductor layer may include the following steps: A conductor material layer is formed on a dielectric material layer in the second region. A hard mask material layer is conformally formed on the stacked structure and the conductor material layer. A second patterned photoresist layer is formed on the hard mask material layer in the second region. The second patterned photoresist layer is not located directly above the stacked structure in the first region. A portion of the hard mask material layer exposed by the second patterned photoresist layer is removed to form a second hard mask layer. A portion of the conductor material layer in the second region exposed by the second hard mask layer is removed.
[0018] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, during the process of removing a portion of the conductor material layer in the second region exposed by the second hard mask layer, the height of the first hard mask layer in the first region can be reduced simultaneously.
[0019] According to an embodiment of the present invention, in the above-described method for manufacturing a semiconductor structure, a first patterned photoresist layer may cover a second conductor layer.
[0020] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following step: forming a gap wall on the sidewall of the stacked structure.
[0021] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following step: forming an isolation structure in a substrate in a first region.
[0022] According to one embodiment of the present invention, in the above-described method for manufacturing the semiconductor structure, a portion of the stacked structure may be located directly above the isolation structure.
[0023] According to an embodiment of the present invention, in the above-described method for manufacturing the semiconductor structure, the first region is, for example, a memory region. The second region is, for example, a logic element region.
[0024] Based on the above, in a semiconductor structure manufacturing method according to an embodiment of the present invention, a first patterned photoresist layer is used as a mask to remove the first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer. This reduces the complexity of the manufacturing process and the manufacturing cost.
[0025] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0026] Figures 1A to 1F This is a cross-sectional view of the manufacturing process of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0027] Figures 1A to 1F This is a cross-sectional view of the manufacturing process of a semiconductor structure according to an embodiment of the present invention.
[0028] Please refer to Figure 1A A substrate 100 is provided. The substrate 100 has a first region R1 and a second region R2. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the first region R1 may be a memory region, and the second region R2 may be a logic element region. For example, the memory region may be a non-volatile memory region (e.g., a flash memory region), and the logic element region may be a high-voltage element region (e.g., a high-voltage transistor element region), but the invention is not limited thereto. Furthermore, an isolation structure 102 may be formed in the substrate 100 in the first region R1. Additionally, an isolation structure 104 may be formed in the substrate 100 in the second region R2. Isolation structures 102 and 104 are, for example, shallow trench isolation structures. The material of isolation structures 102 and 104 is, for example, silicon oxide. In some embodiments, isolation structures 102 and 104 may be formed simultaneously using the same fabrication process.
[0029] Next, a stacked structure 106 is formed on the substrate 100 in the first region R1. A portion of the stacked structure 106 may be located directly above the isolation structure 102. The stacked structure 106 includes a dielectric layer 108, a charge storage layer 110, a dielectric layer 112, a conductor layer 114, and a hard mask layer 116. The dielectric layer 108 is located on the substrate 100. The material of the dielectric layer 108 is, for example, silicon oxide. The charge storage layer 110 is located on the dielectric layer 108. The charge storage layer 110 is, for example, a floating gate. The material of the charge storage layer 110 is, for example, doped polysilicon, undoped polysilicon, or a combination thereof. The dielectric layer 112 is located on the charge storage layer 110. The dielectric layer 112 may be a single-layer structure or a multi-layer structure. The material of the dielectric layer 112 is, for example, silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the dielectric layer 112 may be a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO). Conductor layer 114 is located on dielectric layer 112. Conductor layer 114 can be used as a control gate. The material of conductor layer 114 is, for example, doped polysilicon. Hard mask layer 116 is located on conductor layer 114. The material of hard mask layer 116 is, for example, silicon nitride. In addition, stacked structure 106 may also include hard mask layer 118. Hard mask layer 118 is located between hard mask layer 116 and conductor layer 114. The material of hard mask layer 118 is, for example, silicon oxide.
[0030] Furthermore, spacer walls 120 may be formed on the sidewalls of the stacked structure 106. Spacer walls 120 may be a single-layer or multi-layer structure. The material of spacer walls 120 may be, for example, silicon oxide, silicon nitride, or a combination thereof. In this embodiment, spacer walls 120 are exemplified as a multi-layer structure. However, the invention is not limited thereto. For example, spacer walls 120 may include spacer walls 122 and 124. Spacer wall 122 is located on the sidewalls of the stacked structure 106. The material of spacer wall 122 is, for example, silicon oxide. Spacer wall 124 is located on spacer wall 122. The material of spacer wall 124 is, for example, silicon nitride.
[0031] In some embodiments, a dielectric layer 126 may be formed on a substrate 100 on one side of the spacer wall 120. The material of the dielectric layer 126 is, for example, silicon oxide. Furthermore, a conductor layer 128 may be formed on the dielectric layer 126. The conductor layer 128 may be a single-layer or multi-layer structure. The material of the conductor layer 128 is, for example, doped polysilicon. Additionally, a dielectric layer 130 may be formed between the spacer wall 120 and the conductor layer 128. The material of the dielectric layer 130 is, for example, silicon oxide.
[0032] On the other hand, a dielectric material layer 132 is formed on the substrate 100 in the second region R2. The material of the dielectric material layer 132 is, for example, silicon oxide. The method for forming the dielectric material layer 132 is, for example, thermal oxidation.
[0033] Next, a conductor material layer 134 can be formed on the dielectric material layer 132 in the second region R2. The material of the conductor material layer 134 is, for example, doped polysilicon. The method for forming the conductor material layer 134 is, for example, chemical vapor deposition.
[0034] Then, a hard mask material layer 136 can be conformally formed on the stacked structure 106 and the conductor material layer 134. The material of the hard mask material layer 136 is, for example, silicon oxide. The hard mask material layer 136 can be formed by, for example, chemical vapor deposition.
[0035] Next, a patterned photoresist layer 138 can be formed on the hard mask material layer 136 in the second region R2. In some embodiments, the patterned photoresist layer 138 is not located directly above the stacked structure 106 in the first region R1. The patterned photoresist layer 138 can be formed by a photolithography process.
[0036] Please refer to Figure 1B The hard mask material layer 136 exposed by the patterned photoresist layer 138 can be removed to form a hard mask layer 136a. That is, in the first region R1 and the second region R2, the hard mask material layer 136 not covered by the patterned photoresist layer 138 is removed. Furthermore, the method for removing the portion of the hard mask material layer 136 exposed by the patterned photoresist layer 138 is, for example, dry etching.
[0037] Next, the patterned photoresist layer 138 can be removed. The removal method for the patterned photoresist layer 138 is, for example, dry stripping or wet stripping.
[0038] Please refer to Figure 1C A portion of the conductive material layer 134 in the second region R2 exposed by the hard mask layer 136a can be removed, thereby forming a conductive layer 134a on the dielectric material layer 132 in the second region R2. The conductive layer 134a can be used as a gate. The method for removing the portion of the conductive material layer 134 exposed by the hard mask layer 136a is, for example, dry etching. In some embodiments, the height of the hard mask layer 116 in the first region R1 can be reduced simultaneously during the removal of the portion of the conductive material layer 134 exposed by the hard mask layer 136a. In some embodiments, the height of the spacer wall 120 in the first region R1 can be reduced simultaneously during the removal of the portion of the conductive material layer 134 exposed by the hard mask layer 136a. In some embodiments, the conductive layer 128 in the first region R1 can be removed simultaneously during the removal of the portion of the conductive material layer 134 exposed by the hard mask layer 136a.
[0039] In some embodiments, during the etching process that removes a portion of the conductor material layer 134 exposed by the hard mask layer 136a, the hard mask layer 136a may be gradually consumed and removed, but the invention is not limited to this. In other embodiments, the hard mask layer 136a may be removed by additional fabrication processes (e.g., etching processes). In some embodiments, a cleaning fabrication process may be performed after the conductor layer 134a is formed. Furthermore, the dielectric layer 126 and dielectric layer 130 may be removed during the aforementioned cleaning fabrication process.
[0040] Please refer to Figure 1D A patterned photoresist layer 140 is formed, wherein the patterned photoresist layer 140 exposes the hard mask layer 116 in the first region R1 and a portion of the dielectric material layer 132 in the second region R2. In some embodiments, the patterned photoresist layer 140 may cover the conductor layer 134a. In some embodiments, the patterned photoresist layer 140 may cover a portion of the hard mask layer 116 and a portion of the hard mask layer 118. The patterned photoresist layer 140 may be formed by a photolithography process.
[0041] Please refer to Figure 1EUsing a patterned photoresist layer 140 as a mask, the hard mask layer 116 exposed by the patterned photoresist layer 140 and a portion of the dielectric material layer 132 exposed by the patterned photoresist layer 140 are removed. This forms a dielectric layer 132a located between the conductor layer 134a and the substrate 100. The dielectric layer 132a can be used as a gate dielectric layer. In some embodiments, after removing the hard mask layer 116 exposed by the patterned photoresist layer 140, a portion of the hard mask layer 116 covered by the patterned photoresist layer 140 may remain, forming a hard mask layer 116a. Furthermore, after removing the hard mask layer 116 exposed by the patterned photoresist layer 140, the patterned photoresist layer 140 and the hard mask layer 116a may expose a hard mask layer 118.
[0042] Additionally, the method for removing the hard mask layer 116 exposed by the patterned photoresist layer 140 and the portion of the dielectric material layer 132 exposed by the patterned photoresist layer 140 may include performing an etching process. The etching process is, for example, a dry etching process. In some embodiments, in the above etching process, the ratio of the etching rate of the hard mask layer 116 to the etching rate of the dielectric material layer 132 may range from 1.5 to 1. In some embodiments, in the above etching process, the ratio of the etching rate of the hard mask layer 116 to the etching rate of the dielectric material layer 132 may range from 1.3 to 1.
[0043] Please refer to Figure 1F After removing a portion of the dielectric material layer 132 exposed by the patterned photoresist layer 140, two doped regions 142 can be formed in the substrate 100 on both sides of the conductor layer 134a using the patterned photoresist layer 140 as a mask. The doped regions 142 can be lightly doped drain regions (LDDs). The doped regions 142 can be formed, for example, by ion implantation.
[0044] In some embodiments, a patterned photoresist layer 140 can be used as a mask to remove the hard mask layer 118 exposed by the patterned photoresist layer 140. This exposes the conductor layer 114, facilitating the formation of contact windows (not shown) electrically connected to the conductor layer 114 in subsequent fabrication processes. Furthermore, the hard mask layer 118 exposed by the patterned photoresist layer 140 can be removed before or after the formation of the doped region 142. In some embodiments, after removing the hard mask layer 118 exposed by the patterned photoresist layer 140, a portion of the hard mask layer 118 covered by the patterned photoresist layer 140 can be left, forming a hard mask layer 118a. Additionally, the method for removing the hard mask layer 118 exposed by the patterned photoresist layer 140 can be, for example, a dry etching fabrication process.
[0045] In this embodiment, the hard mask layer 118 exposed by the patterned photoresist layer 140 is removed before the patterned photoresist layer 140 is removed to expose the conductor layer 114, but the present invention is not limited thereto. In other embodiments, the hard mask layer 118 exposed by the hard mask layer 116a may be removed by subsequent fabrication processes (such as etching processes) after the patterned photoresist layer 140 is removed to expose the conductor layer 114.
[0046] Furthermore, after forming the doped region 142, the patterned photoresist layer 140 can be removed. The removal method for the patterned photoresist layer 140 is, for example, dry stripping or wet stripping.
[0047] Furthermore, the subsequent fabrication processes used to form the elements in the first region R1 (e.g., memory elements) and the elements in the second region R2 (e.g., logic elements) are well known to those skilled in the art and will not be described here.
[0048] As can be seen from the above embodiments, in the manufacturing method of the semiconductor structure 10, a patterned photoresist layer 140 is used as a mask to remove the hard mask layer 116 exposed by the patterned photoresist layer 140 and a portion of the dielectric material layer 132 exposed by the patterned photoresist layer 140. This reduces the number of manufacturing steps and photomasks, thereby lowering the complexity of the manufacturing process and the manufacturing cost.
[0049] In summary, in the semiconductor structure manufacturing method of the above embodiments, since the manufacturing process of the components in the first region can be integrated with the manufacturing process of the components in the second region, the number of manufacturing process steps and photomasks can be reduced, thereby reducing the complexity of the manufacturing process and the manufacturing cost.
[0050] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, wherein the substrate has a first region and a second region; A stacked structure is formed on the substrate in the first region, wherein the stacked structure comprises: A first dielectric layer is located on the substrate; A charge storage layer is located on the first dielectric layer; The second dielectric layer is located on the charge storage layer; A first conductor layer is located on the second dielectric layer; and A first hard mask layer is located on the first conductor layer; A dielectric material layer is formed on the substrate in the second region; A second conductor layer is formed on the dielectric material layer in the second region; A first patterned photoresist layer is formed, wherein the first patterned photoresist layer exposes the first hard mask layer in the first region and a portion of the dielectric material layer in the second region; and Using the first patterned photoresist layer as a mask, the first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed, wherein the first patterned photoresist layer directly contacts the top surface of the second conductor layer.
2. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein the method of removing the first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer includes performing an etching process.
3. The method for manufacturing a semiconductor structure as claimed in claim 2, wherein in the etching process, the ratio of the etching rate of the first hard mask layer to the etching rate of the dielectric material layer ranges from 1.5 to 1.
4. The method for manufacturing a semiconductor structure as claimed in claim 2, wherein in the etching process, the ratio of the etching rate of the first hard mask layer to the etching rate of the dielectric material layer ranges from 1.3 to 1.
5. The method for manufacturing a semiconductor structure as described in claim 2, wherein the etching process includes a dry etching process.
6. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the first patterned photoresist layer covers a portion of the first hard mask layer.
7. The method of manufacturing a semiconductor structure as claimed in claim 6, wherein after removing the first hard mask layer exposed by the first patterned photoresist layer, a portion of the first hard mask layer covered by the first patterned photoresist layer remains.
8. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the stacked structure further comprises: A second hard mask layer is located between the first hard mask layer and the first conductor layer, wherein... After the first hard mask layer exposed by the first patterned photoresist layer is removed, the second hard mask layer is exposed by the first patterned photoresist layer.
9. The method for manufacturing a semiconductor structure as described in claim 8, further comprising: Using the first patterned photoresist layer as a mask, the second hard mask layer exposed by the first patterned photoresist layer is removed.
10. The method of manufacturing a semiconductor structure as claimed in claim 9, wherein the first patterned photoresist layer covers a portion of the second hard mask layer.
11. The method of manufacturing a semiconductor structure as claimed in claim 10, wherein after removing the second hard mask layer exposed by the first patterned photoresist layer, a portion of the second hard mask layer covered by the first patterned photoresist layer remains.
12. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: After removing a portion of the dielectric material layer exposed by the first patterned photoresist layer, two doped regions are formed in the substrate on both sides of the second conductor layer using the first patterned photoresist layer as a mask.
13. The method for manufacturing a semiconductor structure as described in claim 12, further comprising: After the two doped regions are formed, the first patterned photoresist layer is removed.
14. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method for forming the second conductor layer comprises: A conductor material layer is formed on the dielectric material layer in the second region; A hard mask material layer is conformally formed on the stacked structure and the conductor material layer; A second patterned photoresist layer is formed on the hard mask material layer in the second region, wherein the second patterned photoresist layer is not located directly above the stacked structure in the first region; Remove a portion of the hard mask material layer exposed by the second patterned photoresist layer to form a second hard mask layer; as well as Remove a portion of the conductor material layer in the second region exposed by the second hard mask layer.
15. The method of manufacturing a semiconductor structure as claimed in claim 14, wherein during the removal of a portion of the conductor material layer in the second region exposed by the second hard mask layer, the height of the first hard mask layer in the first region is simultaneously reduced.
16. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein the first patterned photoresist layer covers the second conductor layer.
17. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: A gap wall is formed on the sidewall of the stacked structure.
18. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: An isolation structure is formed in the substrate in the first region.
19. The method of manufacturing a semiconductor structure as claimed in claim 18, wherein a portion of the stacked structure is located directly above the isolation structure.
20. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the first region includes a memory region and the second region includes a logic element region.