Fabrication method of array substrate, array substrate and display panel

Abstract

This application provides a method for fabricating an array substrate, an array substrate, and a display panel. The method for fabricating the array substrate involves separately fabricating the active layer and the source and drain electrodes on the active layer. Specifically, a patterning process is first used to etch one of the source or drain electrodes to form one of the active layers, and a portion of the active layer is etched to form the main pattern of the active layer. A first insulating layer is deposited on the fabricated source or drain electrode, and the first insulating layer is used to cover the source or drain electrode through a patterning process. Subsequently, a compensation pattern of the active layer pattern is formed on the main pattern. A trench is formed between the main pattern and the compensation pattern, and a portion of the first insulating layer is filled in the trench. At this time, the length of the trench is the same as the width of the first insulating layer. After the active layer is fabricated, the other source or drain electrode is fabricated, so that the source and drain electrode are separated by the first insulating layer in the trench. Therefore, the width of the first insulating layer formed in the trench is controlled to reduce the width of the trench, thereby further reducing the length of the trench.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to a method for manufacturing an array substrate, the array substrate, and a display panel. Background Technology

[0002] TFT display panels use thin-film transistors (TFTs) as the driving switches for their corresponding pixel units, and they are widely used in display devices such as mobile phones and computers. Currently, TFT display panels are increasingly developing towards higher resolution and higher aperture ratios, therefore, narrow channel TFT technology has become one of the mainstream development trends for TFTs.

[0003] However, in the actual manufacturing process of TFTs, the metal lines on both sides of the TFT channel are affected by the side etching of the etching solution, which increases the channel length. At the same time, in order to prevent metal residue on the channel interface, over-etching is required. The over-etching process will allow the metal lines on both sides of the channel to be etched for a longer time, thereby further increasing the channel length. This is not conducive to realizing the narrow channel of TFTs and can easily lead to a decrease in the on-state current of TFTs. Summary of the Invention

[0004] This application provides a method for fabricating an array substrate, an array substrate, and a display panel to solve the problem that it is difficult to achieve narrow channel configuration for thin-film transistors in an array substrate.

[0005] On one hand, this application provides a method for fabricating an array substrate, the method comprising:

[0006] A gate, a gate insulating layer, and an active layer are sequentially formed on a substrate.

[0007] One of the source or drain electrodes is formed on the active layer, and a portion of the active layer is etched to form the main pattern of the active layer;

[0008] A patterned first insulating layer is formed on one of the source or drain electrodes, the first insulating layer covering one of the source or drain electrodes;

[0009] A compensation pattern of the active layer pattern is formed on the main pattern, and a channel is formed between the main pattern and the compensation pattern, and a portion of the first insulating layer is filled in the channel.

[0010] Another source or drain is formed on the compensation pattern of the active layer.

[0011] In one possible implementation of this application, the steps of forming one of the source or drain electrodes on the active layer and etching a portion of the active layer to form the main pattern of the active layer include:

[0012] A source / drain metal layer is deposited over the entire surface of the active layer;

[0013] A patterning process using wet etching is used to etch one of the source or drain electrodes in the source or drain metal layer;

[0014] A dry etching patterning process is used to etch part of the active layer pattern to form the main pattern of the active layer.

[0015] In one possible implementation of this application, the step of forming the active layer includes:

[0016] A semiconductor layer is deposited over the entire surface of the gate insulating layer;

[0017] An ohmic contact layer is prepared on the entire surface of the gate insulating layer;

[0018] The active layer is formed by etching the semiconductor layer and the ohmic contact layer using a single patterning process.

[0019] The steps of forming one of the source or drain electrodes on the active layer and etching a portion of the active layer to form the main pattern of the active layer include:

[0020] The source / drain metal layer is deposited over the entire surface of the ohmic contact layer;

[0021] One of the source or drain electrodes is formed in the source or drain metal layer using a single patterning process;

[0022] The ohmic contact layer is etched until the semiconductor layer is exposed to form the main pattern.

[0023] In one possible implementation of this application, a portion of the ohmic contact layer is etched until the semiconductor layer is exposed to form the main pattern of the active layer, followed by:

[0024] The exposed semiconductor layer is over-etched to completely etch the ohmic contact layer, so that the etched semiconductor layer and the ohmic contact layer form the main pattern of the active layer.

[0025] In one possible implementation of this application, the step of forming the compensation pattern of the active layer pattern on the main pattern includes:

[0026] The semiconductor layer is deposited again over the entire surface of the first insulating layer and the main pattern;

[0027] The ohmic contact layer is deposited again on the entire surface of the semiconductor layer;

[0028] The semiconductor layer and the ohmic contact layer are etched using a single patterning process to form the compensation pattern.

[0029] On the other hand, this application provides an array substrate, including a substrate and a gate, a gate insulating layer, an active layer, a source drain metal layer and a first insulating layer sequentially disposed on the substrate;

[0030] A trench is formed on the active layer, and the source and drain metal layers include a source and a drain located on both sides of the active layer, with the trench located between the source and the drain.

[0031] The first insulating layer is partially located within the channel trench and covers the active layer exposed on the surface of the channel trench, and the first insulating layer partially covers the source electrode or partially covers the drain electrode.

[0032] In one possible implementation of this application, the active layer includes:

[0033] An ohmic contact layer is disposed on the gate insulating layer;

[0034] A semiconductor layer is disposed on the ohmic contact layer, the trench penetrates the ohmic contact layer and a portion of the semiconductor layer, a portion of the semiconductor layer is exposed in the trench, and a first insulating layer is located within the trench and covers the surface of the semiconductor layer exposed in the trench.

[0035] In one possible implementation of this application, the array substrate further includes:

[0036] A first electrode layer is disposed on the gate insulating layer, and the first electrode layer and the active layer are disposed at a distance on the gate insulating layer. The drain portion overlaps the surface of the first electrode layer facing away from the substrate.

[0037] When the first insulating layer partially covers the drain electrode, the edge of the first insulating layer overlaps the surface of the first electrode layer facing away from the substrate.

[0038] In one possible implementation of this application, the array substrate further includes:

[0039] The second insulating layer is disposed on the entire surface of the first insulating layer;

[0040] When the first insulating layer partially covers the source electrode, the second insulating layer partially is disposed on the side of the first insulating layer facing away from the substrate, and the second insulating layer partially is located on the drain electrode;

[0041] When the first insulating layer partially covers the drain electrode, the second insulating layer partially is disposed on the side of the first insulating layer facing away from the substrate, and the second insulating layer partially is located on the source electrode.

[0042] On the other hand, this application also provides a display panel including the array substrate described above.

[0043] This application provides a method for fabricating an array substrate, an array substrate, and a display panel. The method involves sequentially forming a gate, a gate insulating layer, and an active layer on a substrate. The active layer, along with its source and drain electrodes, are fabricated separately. Specifically, one of the source or drain electrodes is first formed, and a portion of the active layer is etched to form a main pattern. A first insulating layer is then deposited on the fabricated source or drain electrode and patterned using a patterning process. This first insulating layer covers the source or drain electrode, providing protection in subsequent processes. Finally, the main pattern is then... A compensation pattern for the active layer is formed, creating a channel between the main pattern and the compensation pattern. The channel is partially filled with a first insulating layer, and the length of the channel is equal to the width of the first insulating layer. After the active layer pattern is fabricated, another source or drain is etched onto the compensation pattern of the active layer, separating the source and drain by the first insulating layer in the channel. Therefore, the length of the channel can be further reduced by controlling the width of the first insulating layer formed in the channel without the risk of short circuit between the source and drain. This is beneficial for the array substrate of this application to form a narrow-channel thin-film transistor, increasing the on-state current and improving the display effect. Attached Figure Description

[0044] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0045] Figure 1 This is a schematic diagram illustrating the fabrication process of the array substrate provided in the embodiments of this application.

[0046] Figure 2 This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0047] Figure 3 This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0048] Figure 4 This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0049] Figure 5This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0050] Figure 6 This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0051] Figure 7 This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0052] Figure 8 This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0053] Figure 9 This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0054] Figure 10 This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0055] Figure 11 This is a schematic diagram of the manufacturing process of step S110 in the manufacturing method of this application embodiment.

[0056] Figure 12 This is a schematic diagram of the array substrate structure provided in an embodiment of this application.

[0057] Figure 13 This is a schematic diagram of an array substrate structure provided in another embodiment of this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0059] In the description of this application, it should be understood that the features referred to by the terms "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. It should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly; for example, they may refer to a direct connection or an indirect connection through an intermediate medium, or they may refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0060] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0061] This application provides a method for manufacturing an array substrate, an array substrate, and a display panel, which will be described in detail below.

[0062] Please refer to Figure 1 This application also provides a method for manufacturing an array substrate, the method comprising the following steps S100-S500:

[0063] S100, a gate 20, a gate insulating layer 60 and an active layer 30 are sequentially formed on the substrate 10.

[0064] Specifically, in the embodiments of this application, step SS100, which involves sequentially forming a gate 20, a gate insulating layer 60, and an active layer 30 on the substrate 10, may include the following steps S101-S103:

[0065] S101, Provide a substrate 10.

[0066] S102. A full-surface gate metal layer (not shown) is deposited on the substrate 10, and a patterned gate 20 and gate scan line 21 are formed in the gate metal layer using a one-step patterning process. For example... Figure 2 or Figure 4 As shown, the gate 20 and the gate scan line 21 are disposed on the same layer and are made of the same material.

[0067] S103. A gate insulating layer 60 is deposited over the entire surface of the patterned gate 20 and gate scan line 21.

[0068] S104. An active layer 30 is deposited on the entire surface of the gate insulating layer 60, and a patterning process is used to form the main pattern 31 of the active layer 30.

[0069] S200, forming one of the source electrode 42 or the drain electrode 41 on the active layer 30 and etching a portion of the active layer 30 to form the main pattern 31 of the active layer 30.

[0070] In this embodiment, the gate 20, active layer 30, source 42, and drain 41 constitute a thin-film transistor. The source 42 or drain 41 is a metal film layer, and therefore, a photolithography process can be used to pattern the metal film layer to form a patterned source 42 or drain 41. The photolithography process further includes sequentially performing exposure, development, etching, and stripping processes on the metal film layer to complete the patterning. The etching of the metal film layer can be performed using wet etching, which has a fast etching rate, poor anisotropy, and low cost; other etching methods can also be used, and no specific limitation is made here.

[0071] Correspondingly, the active layer 30 in this embodiment can be partially etched using a dry etching process.

[0072] S300, a patterned first insulating layer 50 is formed on one of the source electrode 42 or the drain electrode 41, the first insulating layer 50 covering one of the source electrode 42 or the drain electrode 41.

[0073] In this embodiment, the first insulating layer 50 can act as an etching barrier. When the first insulating layer 50 covers the source 42 or the drain 41, the first insulating layer 50 simultaneously covers the surface of the source 42 or the drain 41 facing away from the substrate 10 and the side facing the channel trench 301, thereby acting as an etching barrier to prevent the width of the metal lines of the drain 41 and the source 42 from being excessively etched and reduced.

[0074] Specifically, the first insulating layer 50 can be made of at least one material selected from silicon oxide (SiOx) and silicon nitride (SiNx). The first insulating layer 50 can be a single-layer structure or a multi-layer structure, without any specific limitation.

[0075] S400, A compensation pattern 32 of an active layer 30 is formed on the main pattern 31, and a channel groove 301 is formed between the main pattern 31 and the compensation pattern 32, and a portion of the first insulating layer 50 is filled in the channel groove 301.

[0076] Specifically, the length of the prepared channel trench 301 can be in the range of 2.25um to 2.5um. For example, the length of the channel trench 301 can be 2.25um, 2.3752um, 2.5um, etc., which can further improve the charging rate of the thin film transistor device and optimize the product display quality.

[0077] S500, another source 42 or drain 41 is formed on the compensation pattern 32 of the active layer 30.

[0078] In the fabrication of the source electrode 42 and drain electrode 41 patterns, this application embodiment can either fabricate the drain electrode 41 first and then the source electrode 42, or it can fabricate the source electrode 42 first and then the drain electrode 41. This application does not impose a specific limitation on this. In addition, when fabricating the drain electrode 41, a patterned data line 43 can also be simultaneously fabricated, wherein the data line 43 is connected to the drain electrode 41.

[0079] Specifically, please combine Figure 2 and Figure 3 Taking the fabrication of drain 41 first and then source 42 as an example, the above steps S200-S500 may include the following steps S210-S510:

[0080] S110, A gate 20, a gate insulating layer 60 and an active layer 30 are sequentially formed on the substrate 10.

[0081] S210, forming a drain electrode 41 on the active layer 30 and etching a portion of the active layer 30 to form the main pattern 31 of the active layer 30.

[0082] S310, A patterned first insulating layer 50 is formed on the drain electrode 41, and the first insulating layer 50 covers the drain electrode 41.

[0083] S410. A compensation pattern 32 of the active layer 30 is formed on the main pattern 31. A channel groove 301 is formed between the main pattern 31 and the compensation pattern 32. A portion of the first insulating layer 50 is filled in the channel groove 301.

[0084] S510, A source electrode 42 is formed on the compensation pattern 32 of the active layer 30.

[0085] In this embodiment, by first fabricating the main pattern 31 of the drain 41 and the active layer 30, and then separating them with the first insulating layer 50 and fabricating the compensation pattern 32 of the source 42 and the active layer 30, it is beneficial to increase the width of the metal lines of the drain 41 and the source 42, reduce the length of the channel trench 301, and thus benefit to increase the on-state current of the thin film transistor in the array substrate.

[0086] In other embodiments, please refer to Figure 4 and Figure 5 Taking the fabrication of source 42 first and then drain 41 as an example, the above steps S200-S500 may also include the following steps S220-S520:

[0087] S120, a gate 20, a gate insulating layer 60 and an active layer 30 are sequentially formed on the substrate 10.

[0088] S220, forming a source electrode 42 on the active layer 30 and etching a portion of the active layer 30 to form the main pattern 31 of the active layer 30.

[0089] S320, A patterned first insulating layer 50 is formed on the source electrode 42, and the first insulating layer 50 covers the source electrode 42.

[0090] S420. A compensation pattern 32 of the active layer 30 is formed on the main pattern 31. A channel groove 301 is formed between the main pattern 31 and the compensation pattern 32. A portion of the first insulating layer 50 is filled in the channel groove 301.

[0091] S520, Drain 41 is formed on the compensation pattern 32 of the active layer 30.

[0092] In this embodiment, by first fabricating the main pattern 31 of the source 42 and the active layer 30, and then separating them with the first insulating layer 50 and fabricating the compensation pattern 32 of the drain 41 and the active layer 30, it is beneficial to increase the width of the metal lines of the drain 41 and the source 42, reduce the length of the channel trench 301, and thus increase the on-state current of the thin film transistor in the array substrate.

[0093] The array substrate fabrication method of this application involves sequentially forming a gate 20, a gate insulating layer 60, and an active layer 30 on a substrate 10. The active layer 30 and its source 42 and drain 41 are fabricated separately. Specifically, a patterning process is first used to etch one of the source 42 or drain 41, and a portion of the active layer 30 is etched to form the main pattern 31 of the active layer 30. A first insulating layer 50 is deposited on the fabricated source 42 or drain 41, and a patterning process is used to cover the source 42 or drain 41 with the first insulating layer 50, thereby providing protection in subsequent processes. Then, the active layer 30 is deposited again, and a patterning process is used to form a compensation pattern 32 of the active layer 30 pattern on the main pattern 31. A channel trench 301 is formed between the main pattern 31 and the compensation pattern 32. The channel trench 301 is filled with a portion of the first insulating layer 50. At this time, the length of the channel trench 301 is the width of the first insulating layer 50. After the active layer 30 pattern is completed, another source 42 or drain 41 is etched on the compensation pattern 32 of the active layer 30 using a patterning process. This separates the source 42 and drain 41 from each other by the first insulating layer 50 in the channel trench 301. Therefore, the length of the channel trench 301 can be further reduced by controlling the width of the first insulating layer 50 formed in the channel trench 301 without the risk of short circuit between the source 42 and drain 41. This is beneficial for the array substrate of this application to form a narrow-channel thin-film transistor, increase the on-state current, and improve the display effect.

[0094] In some embodiments, please refer to Figure 6 Step S200, forming one of the source electrode 42 or the drain electrode 41 on the active layer 30 and etching a portion of the active layer 30 to form the main pattern 31 of the active layer 30, specifically includes the following steps S201-S203:

[0095] S201. Deposit a source / drain metal layer 40 over the entire surface of the active layer 30.

[0096] The source / drain metal layer 40 can be deposited using physical vapor deposition. In other embodiments, other deposition methods can also be used, such as sputtering deposition, chemical vapor deposition, etc. The material of the source / drain metal layer 40 can be one or a combination of aluminum, molybdenum, and copper, and is not specifically limited here.

[0097] S202. A wet etching patterning process is used to etch one of the source electrode 42 or drain electrode 41 in the source / drain metal layer 40.

[0098] Because wet etching has the advantages of fast etching rate, poor anisotropy and low cost, the wet etching method used in this application to form patterned source electrode 42 or drain electrode 41 can improve the fabrication efficiency and reduce the manufacturing cost.

[0099] S203. A dry etching patterning process is used to etch part of the active layer 30 to form the main pattern 31 of the active layer 30.

[0100] Specifically, dry etching can be performed using an etching gas, which may include at least one of chlorine, nitrogen trifluoride, sulfur hexafluoride, etc.

[0101] In some embodiments, such as Figure 7 As shown, in step S100, which involves sequentially forming a gate 20, a gate insulating layer 60, and an active layer 30 on the substrate 10, the step of forming the active layer 30 specifically includes the following steps S104-S106:

[0102] S104. A semiconductor layer 33 is deposited over the entire surface of the gate insulating layer 60.

[0103] In this embodiment, the semiconductor layer 33 can be made of amorphous silicon (a-Si). Of course, in other embodiments, the semiconductor layer 33 can also be made of materials such as metal oxide semiconductor or low-temperature polycrystalline silicon, and no specific limitation is made here.

[0104] S105. An ohmic contact layer 34 is prepared on the entire surface of the gate insulating layer 60.

[0105] The ohmic contact layer 34 is used to form an ohmic contact between the gate layer 20 and the semiconductor layer 33 to reduce the potential difference at the interface. The ohmic contact layer 34 can be made of doped amorphous silicon material, specifically doped N-type ion amorphous silicon, such as doped nitrogen (N), phosphorus (P), arsenic (As) and other elements.

[0106] S106. The semiconductor layer 33 and the ohmic contact layer 34 are etched using a single patterning process to form the active layer 30 pattern.

[0107] Correspondingly, such as Figure 8 As shown, step S200, depositing a source / drain metal layer 40 on the active layer 30, and using a patterning process to etch one of the source electrode 42 or drain electrode 41 in the source / drain metal layer 40, as well as etching a portion of the active layer 30 pattern to form the main pattern 31 of the active layer 30, specifically includes steps S204-S206:

[0108] S204. A source / drain metal layer 40 is deposited over the entire surface of the ohmic contact layer 34.

[0109] S205. One of the source electrode 42 or drain electrode 41 is formed in the source / drain metal layer 40 using a single patterning process.

[0110] S206, etch part of the ohmic contact layer 34 until the semiconductor layer 33 is exposed, forming the main pattern 31 of the active layer 30.

[0111] In this application, the source electrode 42 or drain electrode 41 can act as an etching barrier for part of the ohmic contact layer 34. Specifically, the portion of the ohmic contact layer 34 below the source electrode 42 or drain electrode 41 formed in step S205 is exposed under the etching barrier of the source electrode 42 or drain electrode 41, while the portion exposed to the source electrode 42 or drain electrode 41 is etched away, so that the etched ohmic contact layer 34 is only formed on the surface of the source electrode 42 or drain electrode 41.

[0112] In some embodiments, such as Figure 9 As shown, in step S206, the ohmic contact layer 34 is etched until the semiconductor layer 33 is exposed to form the main pattern 31 of the active layer 30. This is followed by the next step S207:

[0113] S207. Over-etch the exposed semiconductor layer 33 so that the ohmic contact layer 34 is completely etched, so that the etched semiconductor layer 33 and the ohmic contact layer 34 form the main pattern 31 of the active layer 30.

[0114] The semiconductor layer 33 can be over-etched using a dry etching process. In this embodiment, the semiconductor layer 33 is over-etched to completely remove the ohmic contact layer 34 on its upper surface, preventing any residue of the ohmic contact layer 34 and ensuring that the semiconductor layer 33 is exposed, thus preventing the subsequent source 42 and drain 41 from conducting through the ohmic contact layer 34. Correspondingly, in this implementation, the channel trench 301 formed between the main pattern 31 and the compensation pattern 32 of the active layer 30 completely penetrates the ohmic contact layer 34 and partially penetrates the semiconductor layer 33 along the thickness direction of the array substrate 10. Furthermore, when the first insulating layer 50 is partially formed within the channel trench 301, the first insulating layer 50 covers the semiconductor layer 33 and is exposed on the surface of the channel trench 301.

[0115] In some embodiments, such as Figure 10 As shown, step S400, forming the compensation pattern 32 of the active layer 30 on the main pattern 31, specifically includes the following steps S401-S403:

[0116] S401, a semiconductor layer 33 is deposited again on the entire surface of the first insulating layer 50 and the main pattern 31.

[0117] S402. An ohmic contact layer 34 is deposited again on the entire surface of the semiconductor layer 33.

[0118] S403, The semiconductor layer 33 and the ohmic contact layer 34 are etched using a single patterning process to form a compensation pattern 32.

[0119] Since the main pattern 31 of the active layer 30 formed by the fabrication method of this application embodiment includes a patterned semiconductor layer 33 and a patterned ohmic contact layer 34, the semiconductor layer 33 and the ohmic contact layer 34 are fabricated correspondingly when forming the compensation pattern 32 of the active layer 30, thereby ensuring the structural integrity of the active layer 30. Furthermore, the fabrication method of this application embodiment deposits the semiconductor layer 33 and the ohmic contact layer 34 over the entire surface, and then forms the compensation pattern 32 of the active layer 30 through a single patterning process. Therefore, the semiconductor layer 33 and the ohmic contact layer 34 do not need to be etched separately, which helps to improve the fabrication efficiency of the array substrate.

[0120] Of course, in other embodiments, the semiconductor layer 33 and the ohmic contact layer 34 can also be etched separately, and this application does not limit this.

[0121] In some embodiments, combined with Figure 1 and Figure 11 As shown, step S100, which involves sequentially forming a gate 20, a gate insulating layer 60, and an active layer 30 on a substrate 10, may further include the step of fabricating a patterned first electrode layer 70, wherein the source electrode 42 is partially attached to the first electrode layer 70.

[0122] Correspondingly, after step S500, forming another source 42 or drain 41 on the compensation pattern 32 of the active layer 30, the following steps S600-S700 may be included:

[0123] S600, a second insulating layer 80 is formed on the first insulating layer 50 and the drain 41 or on the first insulating layer 50 and the source 42.

[0124] S700, a patterned second electrode layer 90 is formed on the second insulating layer 80.

[0125] In this embodiment, both the first electrode layer 70 and the second electrode layer 90 can be transparent electrode layers made of a transparent material. Specifically, the first electrode layer 70 and the second electrode layer 90 can be made of either indium tin oxide (ITO) or indium zinc oxide (IZO). The materials of the first electrode layer 70 and the second electrode layer 90 can be the same. In this embodiment, the first electrode layer 70 can be a pixel electrode layer, and correspondingly, the second electrode layer 90 can be a common electrode layer.

[0126] To better implement the array substrate fabrication method of this application, please refer to Figures 12-13 This application also provides an array substrate, including a substrate 10 and a gate 20, a gate insulating layer 60, an active layer 30, a source 42, a drain 41 and a first insulating layer 50 sequentially disposed on the substrate 10.

[0127] The substrate 10 can be a glass substrate or a flexible substrate, and no specific restrictions are imposed here.

[0128] The active layer 30 has a channel trench 301, and the source and drain metal layer 40 includes a source electrode 42 and a drain electrode 41 located on both sides of the active layer 30. The channel trench 301 is located between the source electrode 42 and the drain electrode 41.

[0129] The first insulating layer 50 is partially located within the channel groove 301 and covers the active layer 30, which is exposed on the surface of the channel groove 301. The first insulating layer 50 partially covers the source electrode 42 or partially covers the drain electrode 41.

[0130] In this embodiment, the first insulating layer 50 can act as an etching barrier. When the first insulating layer 50 covers the source 42 or the drain 41, the first insulating layer 50 simultaneously covers the surface of the source 42 or the drain 41 facing away from the substrate 10 and the side facing the channel trench 301, thereby acting as an etching barrier to prevent the width of the metal lines of the drain 41 and the source 42 from being excessively etched and reduced.

[0131] Specifically, the first insulating layer 50 can be made of at least one material selected from silicon oxide (SiOx) and silicon nitride (SiNx). The first insulating layer 50 can be a single-layer structure or a multi-layer structure, without any specific limitation.

[0132] The shape of the channel 301 applicable to the above-mentioned array substrate channel design may include a variety of different channel 301 shapes such as U-shape, double U-shape, L-shape, semi-circle or straight shape, and the embodiments of this application do not impose specific limitations on this.

[0133] The method for fabricating the array substrate of this application involves sequentially depositing a gate 20, a gate insulating layer 60, and an active layer 30 on a substrate 10. A channel trench 301 is formed on the active layer 30, and a portion of the first insulating layer 50 is filled in the channel trench 301. At this time, the length of the channel trench 301 is the same as the width of the first insulating layer 50. After the pattern of the active layer 30 is completed, a patterning process is used again to etch another source electrode 42 or drain electrode 41 in the source-drain metal layer 40 on the compensation pattern 32 of the active layer 30. This separates the source electrode 42 and the drain electrode 41 from each other by the first insulating layer 50 in the channel trench 301. Therefore, by controlling the reduction of the width of the first insulating layer 50 formed in the channel trench 301, the length of the channel trench 301 can be further reduced without the risk of short circuit between the source electrode 42 and the drain electrode 41. This is beneficial for the array substrate of this application to form a narrow-channel thin-film transistor, increase the on-state current, and improve the display effect.

[0134] In some embodiments, the active layer 30 includes an ohmic contact layer 34 and a semiconductor layer 33.

[0135] The ohmic contact layer 34 is disposed on the gate insulating layer 60. The semiconductor layer 33 is disposed on the ohmic contact layer 34. The channel trench 301 completely penetrates the ohmic contact layer 34 and the penetrating portion of the semiconductor layer 33. The semiconductor layer 33 is partially exposed in the channel trench 301. The first insulating layer 50 is partially located in the channel trench 301 and covers the surface of the semiconductor layer 33 exposed in the channel trench 301.

[0136] In this embodiment, the semiconductor layer 33 can be made of amorphous silicon (a-Si). Of course, in other embodiments, the semiconductor layer 33 can also be made of materials such as metal oxide semiconductors or low-temperature polycrystalline silicon; no specific limitations are made here. The ohmic contact layer 34 is used to form an ohmic contact between the gate layer 20 and the semiconductor layer 33, thereby reducing the potential difference at the interface. The ohmic contact layer 34 can be made of doped amorphous silicon, specifically N-type doped amorphous silicon, such as doped with nitrogen (N), phosphorus (P), arsenic (As), etc.

[0137] In some embodiments, the array substrate further includes a first electrode layer 70.

[0138] The first electrode layer 70 is a patterned film layer. For details, please refer to... Figure 12 The first electrode layer 70 is disposed on the insulating layer of the gate 20. The first electrode layer 70 and the active layer 30 are disposed at intervals on the insulating layer of the gate 20. The drain 41 is partially connected to the surface of the first electrode layer 70 facing away from the substrate 10.

[0139] When the first insulating layer 50 partially covers the drain electrode 41, the edge of the first insulating layer 50 overlaps with the surface of the first electrode layer 70 facing away from the substrate 10.

[0140] In this embodiment, both the first electrode layer 70 and the second electrode layer 90 can be transparent electrode layers made of a transparent material. Specifically, the first electrode layer 70 and the second electrode layer 90 can be made of either indium tin oxide (ITO) or indium zinc oxide (IZO). The materials of the first electrode layer 70 and the second electrode layer 90 can be the same. In this embodiment, the first electrode layer 70 can be a patterned pixel electrode layer, and correspondingly, the second electrode layer 90 can be a common electrode layer.

[0141] In some embodiments, the array substrate further includes a second insulating layer 80. The second insulating layer 80 is disposed over the entire surface of the first insulating layer 50. The second insulating layer 80 serves to insulate the layers of the source electrode 42 and drain electrode 41 from the layers of the second electrode layer 90. Specifically, the second insulating layer 80 can be made of at least one material selected from silicon oxide (SiOx) and silicon nitride (SiNx). In this embodiment, the material of the second insulating layer 80 can be the same as or different from that of the first insulating layer 50; no specific limitation is imposed.

[0142] For details, please refer to Figure 12 When the first insulating layer 50 partially covers the source electrode 42, the second insulating layer 80 is partially disposed on the side of the first insulating layer 50 facing away from the substrate 10, and the second insulating layer 80 is partially located on the drain electrode 41. Please refer to... Figure 13 When the first insulating layer 50 partially covers the drain electrode 41, the second insulating layer 80 is partially disposed on the side of the first insulating layer 50 facing away from the substrate 10, and the second insulating layer 80 is partially located on the source electrode 42.

[0143] On the other hand, in order to better implement the array substrate of this application, this application embodiment also provides a display panel including the array substrate described above. Since this display panel has the same beneficial effects as described above, it will not be described again here.

[0144] The aforementioned display panel can be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, or a liquid crystal display (LCD) display panel.

[0145] This application does not impose specific limitations on the application of the above-mentioned display panel. The display panel can be applied to any product or component with display function, such as handheld devices (smartphones, tablets, etc.), wearable devices (smart bracelets, wireless headphones, smartwatches, smart glasses, etc.), in-vehicle devices (navigation systems, reversing assistance systems, dashcams, in-vehicle refrigerators, etc.), virtual reality devices, augmented reality devices, and terminal devices.

[0146] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not detailed in a particular embodiment, please refer to the relevant descriptions in other embodiments. In specific implementation, each of the above units or structures can be implemented as an independent entity, or can be arbitrarily combined to be implemented as the same or several entities. For specific implementations of the above units or structures, please refer to the preceding method embodiments, which will not be repeated here.

[0147] The foregoing has provided a detailed description of a method for manufacturing an array substrate, the array substrate, and the display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of the embodiments of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the technical solutions and core ideas of the embodiments of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating an array substrate, characterized in that, The manufacturing method includes: A gate, a gate insulating layer, and an active layer are sequentially formed on a substrate. One of the source or drain electrodes is formed on the active layer, and a portion of the active layer is etched to form the main pattern of the active layer; A patterned first insulating layer is formed on one of the source or drain electrodes, the first insulating layer covering one of the source or drain electrodes; A compensation pattern of the active layer is formed on the main pattern, and a channel is formed between the main pattern and the compensation pattern. A portion of the first insulating layer is filled in the channel. Another source or drain is formed on the compensation pattern of the active layer.

2. The manufacturing method according to claim 1, characterized in that, The steps of forming one of the source or drain electrodes on the active layer and etching a portion of the active layer to form the main pattern of the active layer include: A source / drain metal layer is deposited over the entire surface of the active layer; A patterning process using wet etching is used to etch one of the source or drain electrodes in the source or drain metal layer; A dry etching patterning process is used to etch a portion of the active layer to form the main pattern of the active layer.

3. The manufacturing method according to claim 1 or 2, characterized in that, The steps for forming the active layer include: A semiconductor layer is deposited over the entire surface of the gate insulating layer; An ohmic contact layer is prepared on the entire surface of the gate insulating layer; The active layer is formed by etching the semiconductor layer and the ohmic contact layer using a single patterning process. The steps of forming one of the source or drain electrodes on the active layer and etching a portion of the active layer to form the main pattern of the active layer include: A source / drain metal layer is deposited across the entire surface of the ohmic contact layer; One of the source or drain electrodes is formed in the source or drain metal layer using a single patterning process; The ohmic contact layer is etched until the semiconductor layer is exposed to form the main pattern.

4. The manufacturing method according to claim 3, characterized in that, The ohmic connection described in the etched portion The contact layer is extended until the semiconductor layer is exposed, forming the main pattern of the active layer, followed by: The exposed semiconductor layer is over-etched to completely etch the ohmic contact layer. The etched semiconductor layer and the ohmic contact layer form the main pattern of the active layer.

5. The manufacturing method according to claim 3, characterized in that, The step of forming the compensation pattern of the active layer on the main pattern includes: The semiconductor layer is deposited again over the entire surface of the first insulating layer and the main pattern; The ohmic contact layer is deposited again on the entire surface of the semiconductor layer; The semiconductor layer and the ohmic contact layer are etched using a single patterning process to form the compensation pattern.

6. An array substrate, characterized in that, It includes a substrate and a gate, a gate insulating layer, an active layer, a source drain metal layer and a first insulating layer sequentially disposed on the substrate; A trench is formed on the active layer, and the source and drain metal layers include a source and a drain located on both sides of the active layer, with the trench located between the source and the drain. The first insulating layer is partially located within the channel trench and covers the active layer exposed on the surface of the channel trench, and the first insulating layer partially covers the source electrode or partially covers the drain electrode.

7. The array substrate according to claim 6, characterized in that, The active layer includes: An ohmic contact layer is disposed on the gate insulating layer; A semiconductor layer is disposed on the ohmic contact layer, the trench penetrates the ohmic contact layer and a portion of the semiconductor layer, a portion of the semiconductor layer is exposed in the trench, and a first insulating layer is located within the trench and covers the surface of the semiconductor layer exposed in the trench.

8. The array substrate according to claim 6, characterized in that, The array substrate further includes: A first electrode layer is disposed on the gate insulating layer, and the first electrode layer and the active layer are disposed at a distance on the gate insulating layer. The drain portion overlaps the surface of the first electrode layer facing away from the substrate. When the first insulating layer partially covers the drain electrode, the edge of the first insulating layer overlaps the surface of the first electrode layer facing away from the substrate.

9. The array substrate according to claim 6, characterized in that, The array substrate further includes: The second insulating layer is disposed on the entire surface of the first insulating layer; When the first insulating layer partially covers the source electrode, the second insulating layer partially is disposed on the side of the first insulating layer facing away from the substrate, and the second insulating layer partially is located on the drain electrode; When the first insulating layer partially covers the drain electrode, the second insulating layer partially is disposed on the side of the first insulating layer facing away from the substrate, and the second insulating layer partially is located on the source electrode.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 6-9.

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