Semiconductor structure and method of fabricating the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductor, and aims to solve the technical problem of poor reliability of the electrical performance of the semiconductor structure. The manufacturing method comprises the following steps: providing a substrate; the substrate comprises a first N region, a first P region, a second N region and a second P region which are sequentially arranged; a gate dielectric layer, a first barrier layer, a first work function layer and a second barrier layer are sequentially arranged on the substrate; a mask layer is formed on the second barrier layer of the first P region and the second P region; the second barrier layer of the first N region and the second N region is removed by using a first etching process with the mask layer as a mask, so that the first work function layer of the first N region and the second N region is exposed; the first work function layer and the first barrier layer of the first N region and the second N region are removed by using a second etching process, so that the gate dielectric layer of the first N region and the second N region is exposed, and the reliability of the electrical performance of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] The main semiconductor device of integrated circuits, especially very large scale integrated circuits, is metal-oxide-semiconductor field effect transistor (MOS transistor for short). With the continuous development of integrated circuit manufacturing technology, the technology node of semiconductor devices is continuously reduced, and the gate length of the transistor is continuously reduced, so that the thickness of the gate dielectric layer also needs to be reduced to improve the short channel effect. The traditional material of the gate dielectric layer is silicon dioxide, and when the thickness is reduced to a certain extent, obvious tunneling leakage problems will occur.

[0003] In the related art, high dielectric constant (high-k) gate dielectric material is used to replace the traditional silicon dioxide gate dielectric material, and metal is used as the gate electrode, so as to avoid the Fermi level pinning effect and boron penetration effect of the high-k material and the traditional gate electrode material, thereby reducing the leakage current of the semiconductor structure.

[0004] However, the reliability of the electrical performance of the semiconductor structure formed in the related art is poor. SUMMARY

[0005] In view of the above problems, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which can improve the reliability of the electrical performance of the semiconductor structure.

[0006] In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, the embodiments of the present application provide a manufacturing method of a semiconductor structure, which comprises: providing a substrate; the substrate comprises a first N region of a first N type device, a first P region of a first P type device, a second N region of a second N type device, and a second P region of a second P type device, wherein the first P region and the first N region and the second N region are adjacent, and the second N region and the first P region and the second P region are adjacent; sequentially forming a gate dielectric layer, a first barrier layer located on the gate dielectric layer, a first work function layer located on the first barrier layer, and a second barrier layer located on the first work function layer on the substrate; forming a mask layer on the second barrier layer of the first P region and the second P region; using the mask layer as a mask, using a first etching process to remove the second barrier layer of the first N region and the second N region to expose the first work function layer of the first N region and the second N region; using a second etching process to remove the first work function layer and the first barrier layer of the first N region and the second N region to expose the gate dielectric layer of the first N region and the second N region.

[0008] Compared with related technologies, the method for fabricating a semiconductor structure provided in this application has at least the following advantages:

[0009] In the semiconductor structure fabrication method provided in this application embodiment, a first etching process is used to remove the second barrier layer of the first N region and the second N region to expose the first work function layer of the first N region and the second N region; a second etching process is used to remove the first work function layer and the first barrier layer of the first N region and the second N region to expose the gate dielectric layer of the first N region and the second N region. In this way, the problem of long etching time of a single etching process can be avoided, thereby improving the problem of over-etching of the sidewall contours of the first P region and the second P region, and thus improving the reliability of the electrical performance of the semiconductor structure.

[0010] Secondly, embodiments of this application also provide a semiconductor structure formed using the semiconductor structure fabrication method of the first aspect. The semiconductor structure includes a substrate and a gate dielectric layer disposed on the substrate. The substrate includes a first N region of a first N-type device, a first P region of a first P-type device, a second N region of a second N-type device, and a second P region of a second P-type device, wherein the first P region is adjacent to the first N region and the second N region, and the second N region is adjacent to the first P region and the second P region. A first barrier layer, a first work function layer, and a second barrier layer are sequentially stacked on the gate dielectric layer of the first P region and the second P region.

[0011] The beneficial effects of the semiconductor structure provided in this application embodiment are the same as those of the semiconductor structure fabrication method provided in the first aspect, and will not be repeated here.

[0012] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its manufacturing method provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0015] Figures 2 to 8 This is a cross-sectional structural diagram illustrating the formation process of the semiconductor structure provided in this application embodiment.

[0016] Figure label:

[0017] 100 - Substrate; 101 - First N-region;

[0018] 102 - First P area; 103 - Second N area;

[0019] 104 - Second P-region; 110 - Gate dielectric layer;

[0020] 111 - Interface layer; 112 - High-k gate dielectric layer;

[0021] 120 - First barrier layer; 130 - First work function layer;

[0022] 140 - Second barrier layer; 150 - Mask layer;

[0023] 151 - Anti-reflective layer; 152 - Photoresist layer;

[0024] 160 - Second work function layer; 170 - Third blocking layer;

[0025] 180-Strain layer. Detailed Implementation

[0026] In related technologies, the substrate includes a first N region, a first P region, a second N region, and a second P region arranged sequentially adjacent to each other. A gate dielectric layer, a first barrier layer, a first work function layer, and a second barrier layer are sequentially stacked on the substrate. In order to remove the second barrier layer, the first work function layer, and the first barrier layer corresponding to the first N region and the second N region, a mask layer is formed on the second barrier layer corresponding to the first P region and the second P region. Using the mask layer as a mask, a wet etching process is used to remove the second barrier layer, the first work function layer, and the first barrier layer in the first N region and the second N region to expose the gate dielectric layer. However, in this related technology, since the wet etching process needs to remove a large number of film layers, the etching time required by the wet etching process is relatively long. The second barrier layer, the first work function layer, and the first barrier layer at the junction of the first P region and the second P region with the first N region and the second N region, respectively, are successively exposed to the wet etching environment, causing lateral etching of the second barrier layer, the first work function layer, and the second barrier layer at the junction. This results in over-etching of the edge contour of the semiconductor structure in the first P region and the second P region relative to the substrate surface, thus leading to the technical problem of poor reliability of the electrical performance of the semiconductor structure.

[0027] In view of this, embodiments of this application provide a semiconductor structure and a method for fabricating the same. In the method for fabricating the semiconductor structure, a first etching process is used to remove the second barrier layer of the first N region and the second N region to expose the first work function layer of the first N region and the second N region; a second etching process is used to remove the first work function layer and the first barrier layer of the first N region and the second N region to expose the gate dielectric layer of the first N region and the second N region. This avoids the problem of long etching time for a single etching process and can improve the problem of over-etching of the sidewall contours of the first P region and the second P region, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0028] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application; Figures 2 to 8 This is a cross-sectional structural diagram illustrating the formation process of the semiconductor structure provided in this application embodiment.

[0030] like Figure 1 As shown in the embodiments of this application, the method for fabricating a semiconductor structure includes the following steps:

[0031] Step S101: Provide a substrate; the substrate includes a first N region of a first N-type device, a first P region of a first P-type device, a second N region of a second N-type device, and a second P region of a second P-type device, wherein the first P region is adjacent to the first N region and the second N region, and the second N region is adjacent to the first P region and the second P region.

[0032] The substrate 100 can be made of a crystalline semiconductor material, such as a silicon (Si) substrate. The substrate 100 can also be a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a silicon carbide (SiC) substrate, or a gallium nitride (GaN) substrate, etc. The embodiments of this application do not impose specific limitations on this.

[0033] It is understood that the substrate 100 includes a first N region 101 and a second N region 103, the first N region 101 being used to form a first N-type device and the second N region 103 being used to form a second N-type device; the substrate 100 also includes a first P region 102 and a second P region 104, the first P region 102 being used to form a first P-type device and the second P region 104 being used to form a second P-type device.

[0034] For example, the first N-type device can be a first NMOS transistor, the second N-type device can be a second NMOS transistor, the first P-type device can be a first PMOS transistor, and the second P-type device can be a second PMOS transistor.

[0035] The first N region 101, the first P region 102, the second N region 103, and the second P region 104 are isolated by an isolation structure. The isolation structure can be a shallow trench isolation structure, which includes a shallow trench located in the substrate 100 and an insulating material, such as silicon oxide, filling the shallow trench.

[0036] Step S102: A gate dielectric layer, a first barrier layer on the gate dielectric layer, a first work function layer on the first barrier layer, and a second barrier layer on the first work function layer are sequentially formed on the substrate.

[0037] like Figure 2 As shown, a gate dielectric layer 110, a first barrier layer 120 located on the gate dielectric layer 110, a first work function layer 130 located on the first barrier layer 120, and a second barrier layer 140 located on the first work function layer 130 are formed on the substrate 100.

[0038] The gate dielectric layer 110 can be a gate dielectric material with a high dielectric constant (high k) to maintain a certain physical thickness and excellent leakage current performance, so as to adapt to nanometer-width integrated circuits and maintain a good interface and high thermal stability with the silicon substrate.

[0039] For example, the material of the high-k gate dielectric layer 112 includes at least one of the following materials with high dielectric constant: aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium silicate oxide, hafnium dioxide, lanthanum oxide, niobium dioxide, strontium titanate, and niobium silicate oxide.

[0040] In addition, the first barrier layer 120 may include titanium nitride (TiN), the material of the first work function layer 130 may include aluminum oxide (AlO), and the material of the second barrier layer 140 may also include titanium nitride (TiN).

[0041] The first work function layer 130 can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0042] Step S103: Form a mask layer on the second barrier layer of the first P region and the second P region.

[0043] like Figure 3 As shown, a mask layer 150 is formed on the second barrier layer 140 of the first P region 102 and the second P region 104 using a spin coating process or the like.

[0044] It is understood that an initial mask layer is formed on the second barrier layer of the first N region 101, the first P region 102, the second N region 103, and the second P region 104. Then, the initial mask layer is patterned by exposure and development, the initial mask layer located on the first N region 101 and the second N region 103 is removed, and the initial mask layer located on the second barrier layer of the first P region and the second P region is retained to form mask layer 150.

[0045] Step S104: Using the mask layer as a mask, the second barrier layer of the first N region and the second N region is removed by the first etching process to expose the first work function layer of the first N region and the second N region.

[0046] The first etching process can be a dry etching process, and the etching gas for dry etching can be chlorine or the like.

[0047] like Figure 4 As shown, using mask layer 150 as a mask, a dry etching process is employed to remove the second barrier layer 140 of the first N region 101 and the second N region 103, thereby exposing the first work function layer 130 of the first N region 101 and the second N region 103.

[0048] It is understood that in this embodiment, the etching gas used in the dry etching process is chlorine. Thus, during etching, the first work function layer 130 acts as an etching barrier layer, and the chlorine does not etch the first work function layer 130. Furthermore, the dry etching process used is anisotropic etching, thereby ensuring the integrity of the contours at the boundaries between the first P region 102 and the second P region 104 and the first N region 101, respectively, thereby improving the reliability of the electrical performance of the semiconductor structure.

[0049] Step S105: Using a second etching process, remove the first work function layer and the first barrier layer of the first N region and the second N region to expose the gate dielectric layer of the first N region and the second N region.

[0050] Understandably, the second etching process can be a wet etching process.

[0051] like Figure 5 As shown, a wet etching process is used to etch the first work function layer 130 and the first barrier layer 120 of the first N region 101 and the second N region 103, thereby exposing the gate dielectric layer 110 of the first N region 101 and the second N region 103, while retaining the first work function layer 130 of the first P region 102 and the second P region 104. The first work function layer 130 serves as part of the corresponding work function layer of the first P-type device and the second P-type device, and is used to adjust the threshold voltage of the first P-type device and the second P-type device.

[0052] In this embodiment, a first etching process is used to remove the second barrier layer 140 of the first N region 101 and the second N region 103 to expose the first work function layer 130 of the first N region 101 and the second N region 103; a second etching process is used to remove the first work function layer 130 and the first barrier layer 120 of the first N region 101 and the second N region 103 to expose the gate dielectric layer 110 of the first N region 101 and the second N region 103. In this way, the problem of long etching time of a single etching process can be avoided, thereby improving the problem of over-etching of the sidewall contours of the first P region 102 and the second P region 104, and thus improving the reliability of the electrical performance of the semiconductor structure.

[0053] Understandably, when the first etching process uses dry etching and the second etching process uses wet etching, the number of film layers that need to be etched by the wet etching process can be reduced, and the etching time required by the wet etching process can be reduced. This shortens the time that the second barrier layer 140, the first work function layer 130, and the first barrier layer 120 at the junction of the first P region 102 and the second P region 104 with the first N region 101 and the second N region 103, respectively, are successively exposed to the wet etching environment. This improves the phenomenon of lateral etching of the second barrier layer 140, the first work function layer 130, and the first barrier layer 120 at the junction of the first P region 102 and the second P region 104.

[0054] As an alternative implementation, the etching rate of the etching gas on the second barrier layer 140 in the dry etching process is greater than the etching rate of the etching gas on the first work function layer 130. In this way, when etching the second barrier layer 140, the first work function layer 130 is equivalent to the etching barrier layer, which can avoid etching the first work function layer 130.

[0055] For example, the etching rate of the etching gas (e.g., chlorine) on the first work function layer 130 can be 0 to avoid the first work function layer 130 being etched when the second barrier layer 140 is etched.

[0056] When chlorine is used as the etching gas in dry etching, the flow rate of the etching gas in the etching process is 25 to 50 sccm per minute, preferably 35 sccm per minute.

[0057] Understandably, the etching rate of dry etching is controlled by adjusting the flow rate of the etching gas per minute.

[0058] As an optional implementation, the etching solution used to etch the first work function layer 130 and the first barrier layer 120 of the first N region 101 and the second N region 103 using a wet etching process can be an SC1 solution. The SC1 solution can be a mixed aqueous solution of ammonia, hydrogen peroxide and water, wherein the volume fraction ratio of ammonia, hydrogen peroxide and water can be 1:1.5:10 to 1:3:100.

[0059] In addition, the process parameters for wet etching include: etching temperature of 32℃~58℃ and etching time of 65s~185s.

[0060] By setting the etching temperature to 32℃~58℃, the etching rate is avoided from being too low due to the temperature of the etching solution; it also avoids the lateral etching rate of the second barrier layer 140, the first work function layer 130 and the first barrier layer 120 at the junction of the first P region 102 and the second P region 104 being too fast, which would cause severe etching damage to the second barrier layer 140, the first work function layer 130 and the first barrier layer 120 at the junction of the first P region 102 and the second P region 104.

[0061] Based on the above embodiment, before sequentially forming a gate dielectric layer 110, a first barrier layer 120 on the gate dielectric layer 110, a first work function layer 130 on the first barrier layer 120, and a second barrier layer 140 on the first work function layer 130 on the substrate 100, the method further includes forming a strain layer 180 on the substrate 100 of the first P region 102, wherein the material of the first strain layer 180 includes silicon germanide (SiGe).

[0062] Furthermore, after forming the strain layer 180 on the substrate 100 of the first P region 102, the method further includes:

[0063] An interface layer 111 is formed on the substrate 100 of the first N region 101, the second N region 103, the second P region 104, and the strain layer 180 of the first P region 102.

[0064] The interface layer 111 serves as a transition and barrier, preventing the high-k gate dielectric layer 112 from reacting with the material of the substrate 100 and preventing the diffusion of the first work function layer 130. The material of the interface layer 111 includes silicon oxide and silicon oxynitride. The surface of the substrate 100 can be oxidized by thermal oxidation or in-situ water vapor generation process to form the interface layer 111.

[0065] A high-k gate dielectric layer 112 is formed on the interface layer 111. The interface layer 111 and the high-k gate dielectric layer 112 together constitute the gate dielectric layer 110. The dielectric constant of the high-k gate dielectric layer 112 is greater than that of silicon dioxide (SiO2).

[0066] The thickness of the interface layer 111 of the second N region 103 is greater than the thickness of the interface layer 111 of the first N region 101, and the thickness of the interface layer 111 of the second P region 104 is greater than the thickness of the interface layer 111 of the first P region 102, which can improve the problem of tunneling leakage.

[0067] A mask layer 150 is formed on the second barrier layer 140 of the first P region 102 and the second P region 104, specifically including: forming an anti-reflection layer 151 on the second barrier layer 140. The anti-reflection layer 151 may include at least one layer of organic or inorganic anti-reflection material to increase the window of the photolithography process and improve the control of the photolithography stripe width.

[0068] A photoresist layer 152 is formed on the anti-reflection layer 151, and the anti-reflection layer 151 and the photoresist layer 152 together form a mask layer 150.

[0069] like Figure 6 As shown, the mask layer 150 of the first N region 101 and the second N region 103 is removed, the mask layer 150 of the first P region 102 and the second P region 104 is retained, and the mask layer 150 is patterned. Using the patterned mask layer 150 as a mask, the second barrier layer 140 in the first N region 101 and the second N region 103 is etched.

[0070] A second etching process is used to remove the first work function layer 130 and the first barrier layer 120 of the first N region 101 and the second N region 103 to expose the gate dielectric layer 110 of the first N region 101 and the second N region 103.

[0071] After the second etching process is completed, as Figure 7 and Figure 8 As shown, the mask layer 150 of the first P region 102 and the second P region 104 is removed. A second work function layer 160 is formed on the gate dielectric layer 110 corresponding to the first N region 101 and the second N region 103 and on the second barrier layer 140 of the first P region 102 and the second P region 104.

[0072] The second work function layer 160 can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The second work function layer 160 serves as part of the corresponding work function layer of the first N-type device and the second N-type device. The second work function layer 160 is used to adjust the threshold voltage of the first N-type device and the second N-type device.

[0073] It is understandable that since the second work function layer 160 and the first work function layer 130 are made of different materials, the threshold voltages of the first N-type device and the second N-type device are different from those of the first P-type device and the second P-type device, respectively, thereby satisfying the different threshold voltage requirements of the N-type device and the P-type device.

[0074] For example, the material of the second work function layer 160 includes a lanthanum oxide layer.

[0075] Furthermore, after forming a second work function layer 160 on the gate dielectric layer 110 corresponding to the first N region 101 and the second N region 103, and on the second barrier layer 140 of the first P region 102 and the second P region 104, the method further includes forming a third barrier layer 170 on the second work function layer 160. The material of the third barrier layer 170 includes titanium nitride (TiN).

[0076] This application embodiment also provides a semiconductor structure, which is formed using the semiconductor structure fabrication method described in the above embodiment. The semiconductor structure includes a substrate 100 and a gate dielectric layer 110 disposed on the substrate 100. The substrate 100 includes a first N-region 101 of a first N-type device, a first P-region 102 of a first P-type device, a second N-region 103 of a second N-type device, and a second P-region 104 of a second P-type device. The first P-region 102 and the first N-region 101, and the second N-region 103 and the first P-region 102 and the second P-region 104 are adjacent to each other. A first barrier layer 120, a first work function layer 130, and a second barrier layer 140 are sequentially stacked on the gate dielectric layer 110 of the first P-region 102 and the second P-region 104.

[0077] The structure and principle of the semiconductor structure provided in this application embodiment are the same as those of the semiconductor structure formed by the fabrication method provided in the above embodiments, and the beneficial effects of the semiconductor structure provided in this application embodiment are the same as those of the fabrication method of the semiconductor structure provided in the above embodiments, which will not be repeated here.

[0078] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0079] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; The substrate includes a first N region of a first N-type device, a first P region of a first P-type device, a second N region of a second N-type device, and a second P region of a second P-type device, wherein the first P region is adjacent to the first N region and the second N region, and the second N region is adjacent to the first P region and the second P region. A gate dielectric layer, a first barrier layer on the gate dielectric layer, a first work function layer on the first barrier layer, and a second barrier layer on the first work function layer are sequentially formed on the substrate. A mask layer is formed on the second barrier layer of the first P region and the second P region; Using the mask layer as a mask, a first etching process is used to remove the second barrier layer of the first N region and the second N region to expose the first work function layer of the first N region and the second N region; A second etching process is used to remove the first work function layer and the first barrier layer in the first N region and the second N region to expose the gate dielectric layer in the first N region and the second N region.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first etching process includes a dry etching process, and the second etching process includes a wet etching process.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The etching rate of the etching gas in the dry etching process on the second barrier layer is greater than the etching rate of the etching gas on the first work function layer.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The etching rate of the etching gas on the first work function layer is equal to 0.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The material of the second barrier layer includes titanium nitride, the material of the first work function layer includes aluminum oxide, and the etching gas includes chlorine.

6. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The flow rate of the etching gas is 25–50 sccm per minute.

7. The method for fabricating a semiconductor structure according to any one of claims 2, characterized in that, The etching solution in the wet etching process includes an SC1 solution, wherein the volume fraction ratio of ammonia, hydrogen peroxide and water in the SC1 solution is 1:1.5:10 to 1:3:

100.

8. The method for fabricating a semiconductor structure according to claim 6, characterized in that, The process parameters of the wet etching process include: etching temperature of 32℃~58℃ and etching time of 65s~185s.

9. The method for fabricating a semiconductor structure according to any one of claims 1, characterized in that, Before the gate dielectric layer, the first barrier layer on the gate dielectric layer, the first work function layer on the first barrier layer, and the second barrier layer on the first work function layer are sequentially formed on the substrate, the method further includes: A strain layer is formed on the substrate in the first P region.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, After forming a strain layer on the substrate in the first P region, the method further includes: An interface layer is formed on the substrate in the first N region, the second N region, the second P region, and on the strain layer in the first P region; A high-k gate dielectric layer is formed on the interface layer, and the interface layer and the high-k gate dielectric layer together constitute the gate dielectric layer, wherein the dielectric constant of the high-k gate dielectric layer is greater than the dielectric constant of SiO2.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, The thickness of the interface layer in the second N region is greater than the thickness of the interface layer in the first N region, and the thickness of the interface layer in the second P region is greater than the thickness of the interface layer in the first P region.

12. The method for fabricating a semiconductor structure according to claim 1, characterized in that, A mask layer is formed on the second barrier layer of the first P region and the second P region, specifically including: An anti-reflective layer is formed on the second barrier layer; A photoresist layer is formed on the anti-reflection layer, and the anti-reflection layer and the photoresist layer together constitute the mask layer; Remove the mask layers from the first N region and the second N region, and retain the mask layers from the first P region and the second P region.

13. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After employing a second etching process to remove the first work function layer and the first barrier layer in the first N region and the second N region to expose the gate dielectric layer in the first N region and the second N region, the process further includes: Remove the mask layer from the first P region and the second P region; A second work function layer is formed on the gate dielectric layer corresponding to the first N region and the second N region, and on the second barrier layer of the first P region and the second P region.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The material of the second work function layer is different from that of the first work function layer.

15. The method for fabricating a semiconductor structure according to claim 14, characterized in that, The second work function layer is a lanthanum oxide layer.

16. The method for fabricating a semiconductor structure according to claim 13, characterized in that, After forming a second work function layer on the gate dielectric layer corresponding to the first N region and the second N region, and on the second barrier layer of the first P region and the second P region, the method further includes: A third barrier layer is formed on the second work function layer.

17. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method of fabricating a semiconductor structure according to any one of claims 1-16, the semiconductor structure comprising a substrate and a gate dielectric layer disposed on the substrate; the substrate comprising a first N region of a first N-type device, a first P region of a first P-type device, a second N region of a second N-type device, and a second P region of a second P-type device, wherein the first P region is adjacent to the first N region and the second N region, and the second N region is adjacent to the first P region and the second P region; A first barrier layer, a first work function layer, and a second barrier layer are sequentially stacked on the gate dielectric layer of the first P region and the second P region.

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