Interconnect structures and methods of making the same

Abstract

The present disclosure provides an interconnect structure and a method of fabricating the same. The interconnect structure includes a first dielectric layer, a first conductive via in the first dielectric layer, and a first metal line disposed on the first dielectric layer and electrically connected to the first conductive via. At least a portion of the first metal line is exposed to a first air gap.

Description

[0001] This invention claims priority and benefits to U.S. Patent Application No. 17 / 491,716, filed October 1, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to an interconnect structure and a method for fabricating the same, and more particularly to an interconnect structure with gaps and a method for fabricating the same. Background Technology

[0003] In the back-end (BEOL) process of a semiconductor device, various metallization layers, including interconnect structures, are formed on a substrate. The interconnect structures can include lateral interconnect structures, such as metal lines, and vertical interconnect structures, such as conductive vias and / or plugs.

[0004] To prevent interference such as capacitive coupling between two adjacent metal lines from affecting the overall performance of semiconductor devices, a low-k dielectric material with a dielectric constant approximately equal to or less than 4.0 can be filled between adjacent metal lines. This is expected to further reduce capacitive coupling and improve the overall performance characteristics of semiconductor devices.

[0005] The above description of "prior art" is merely a background description and does not acknowledge that the subject matter of this disclosure is disclosed. It does not constitute prior art in this disclosure, and no description of the above "prior art" should be considered part of this invention. Summary of the Invention

[0006] One embodiment of this disclosure provides an interconnect structure, including: a first dielectric layer, a first conductive via, and a first metal line. The first conductive via is disposed in the first dielectric layer. The first metal line is disposed on the first dielectric layer and electrically connected to the first conductive via. At least a portion of the first metal line is exposed in a first air gap.

[0007] In some embodiments, a portion of the top surface of the first dielectric layer is exposed in the first air gap.

[0008] In some embodiments, the first metal wire includes a first lateral surface exposed to the first air gap and a second lateral surface in contact with the first dielectric layer.

[0009] In some embodiments, the interconnect structure includes a second metal line disposed on the first dielectric layer and physically spaced apart from the first metal line. At least a portion of the second metal line is exposed in the first air gap.

[0010] In some embodiments, the interconnect structure includes a second dielectric layer disposed on the first metal line and a second air gap defined above the first air gap.

[0011] In some embodiments, the width of the second air gap is smaller than the width of the first air gap.

[0012] In some embodiments, the interconnect structure includes a second conductive via that penetrates the second dielectric layer and is electrically connected to the first metal wire.

[0013] In some embodiments, the interconnect structure further includes a third dielectric layer disposed on the second dielectric layer and covering the second air gap.

[0014] In some embodiments, the interconnect structure includes a third metal line disposed on the third dielectric layer and electrically connected to the second conductive via. At least a portion of the third metal line is exposed in a third air gap.

[0015] In some embodiments, the third air gap is physically isolated from the second air gap through the third dielectric layer.

[0016] Another embodiment of this disclosure provides an interconnect structure, including: a first dielectric layer, a second dielectric layer, a first conductive structure, and a second conductive structure. The second dielectric layer is disposed above the first dielectric layer. The first conductive structure is disposed between the first dielectric layer and the second dielectric layer. The second conductive structure is disposed between the first dielectric layer and the second dielectric layer. The second conductive structure is isolated from the first conductive structure by a first air gap.

[0017] In some embodiments, the first conductive structure includes a first lateral surface exposed to the first air gap and a second lateral surface in contact with the first dielectric layer.

[0018] In some embodiments, the second dielectric layer defines a second air gap above the first air gap, and the width of the second air gap is smaller than the width of the first air gap.

[0019] In some embodiments, the interconnect structure includes a third dielectric layer and a third conductive structure. The third dielectric layer is disposed on the second dielectric layer and covers the second air gap. The third conductive structure is disposed on the third dielectric layer and is electrically connected to the first conductive structure. The third conductive structure is exposed in the third air gap, and the third air gap is physically isolated from the second air gap through the third dielectric layer.

[0020] Another embodiment of this disclosure provides a method for fabricating an interconnect structure, comprising: depositing a sacrificial layer on a first dielectric layer, the sacrificial layer having etch characteristics different from those of the first dielectric layer; forming a trench in the first dielectric layer and the sacrificial layer; forming a first metal line in the trench; and removing the sacrificial layer from the first dielectric layer.

[0021] In some embodiments, the fabrication method includes forming a second metal line on the first dielectric layer. A portion of the top surface of the first dielectric layer between the first metal line and the second metal line is exposed to air after the sacrificial layer is removed.

[0022] In some embodiments, the fabrication method includes forming an opening in the second dielectric layer and removing a portion of the sacrificial layer through the opening.

[0023] In some embodiments, the fabrication method includes depositing a third dielectric layer on the second dielectric layer to cover the opening.

[0024] In some embodiments, the third dielectric layer is disposed on the second dielectric layer after the sacrificial layer is removed.

[0025] The air in the air gap exhibits a dielectric constant of approximately 1. This low dielectric constant helps reduce capacitive coupling between adjacent metal lines. Therefore, the overall performance characteristics of semiconductor devices, including interconnect structures, can be improved.

[0026] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages that constitute the subject matter of the disclosed patent scope will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended patent claims. Attached Figure Description

[0027] A more comprehensive understanding of the disclosure can be obtained by referring to the accompanying drawings in conjunction with the embodiments and the scope of the disclosed patent, wherein the same element symbols in the drawings refer to the same elements.

[0028] Figure 1 This is a cross-sectional view illustrating the interconnection structure of some embodiments of this disclosure.

[0029] Figure 2A This is a top view illustrating a portion of the interconnection structure of some embodiments of this disclosure.

[0030] Figure 2B This is a top view illustrating a portion of the interconnection structure of some embodiments of this disclosure.

[0031] Figure 2C This is a top view illustrating a portion of the interconnection structure of some embodiments of this disclosure.

[0032] Figure 2DThis is a top view illustrating a portion of the interconnection structure of some embodiments of this disclosure.

[0033] Figure 2E This is a top view illustrating a portion of the interconnection structure of some embodiments of this disclosure.

[0034] Figure 2F This is a top view illustrating a portion of the interconnection structure of some embodiments of this disclosure.

[0035] Figure 2G This is a top view illustrating a portion of the interconnection structure of some embodiments of this disclosure.

[0036] Figure 3A This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0037] Figure 3B This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0038] Figure 3C This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0039] Figure 3D This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0040] Figure 3E This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0041] Figure 3F This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0042] Figure 3G This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0043] Figure 3H This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0044] Figure 3I This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0045] Figure 3J This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0046] Figure 3K This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0047] Figure 3L This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0048] Figure 3M This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0049] Figure 3N This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0050] Figure 3O This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0051] Figure 3P This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0052] Figure 3Q This disclosure illustrates one or more preparation stages of a method for preparing interconnect structures according to some embodiments of the present disclosure.

[0053] Figure 4 This is a flowchart illustrating a method for fabricating interconnect structures according to some embodiments of this disclosure.

[0054] The attached figures are labeled as follows:

[0055] 1: Interconnection Structure

[0056] 10: Dielectric layer

[0057] 11: Conductive via

[0058] 11h: Through hole

[0059] 12: Metal wire

[0060] 12h: trench

[0061] 13: Metal wire

[0062] 13h: Trench

[0063] 14: Dielectric layer

[0064] 15: Conductive via

[0065] 15h: Through hole

[0066] 16: Dielectric layer

[0067] 17: Metal wire

[0068] 17h: Trench

[0069] 18: Metal wire

[0070] 18h: trench

[0071] 19: Dielectric layer

[0072] 20: Dielectric layer

[0073] 21: Metal wire

[0074] 21V: Conductive via

[0075] 22: Metal wire

[0076] 23: Metal wire

[0077] 30: Sacrifice Layer

[0078] 31: Photoresist layer

[0079] 32: Photoresist layer

[0080] 33: Photoresist layer

[0081] 34: Sacrifice Layer

[0082] 35: Photoresist layer

[0083] 40: Preparation method

[0084] 101: Surface

[0085] 101a: Part

[0086] 101b: Part

[0087] 121: Surface

[0088] 121a: Part

[0089] 121b: Part

[0090] 122: Surface

[0091] 123: Surface

[0092] 131: Surface

[0093] 131a: Part

[0094] 131b: Part

[0095] 141: Suspended section

[0096] 161: Surface

[0097] 171: Surface

[0098] 171a: Part

[0099] 171b: Partial

[0100] 191: Suspended section

[0101] 211: Surface

[0102] 211: Long side (or short side)

[0103] 212: Short side (or long side)

[0104] 221: Surface

[0105] 222: Short side (or long side)

[0106] AG1: Air gap

[0107] AG2: Air gap

[0108] AG3: Air gap

[0109] AG4: Air gap

[0110] AG5: Air gap

[0111] AG6: Air gap

[0112] AG7: Air gap

[0113] AG8: Air gap

[0114] AG9: Air gap

[0115] AG10: Air gap

[0116] AG11: Air gap

[0117] AG12: Air gap

[0118] AG13: Air gap

[0119] AG14: Air gap

[0120] AG15: Air gap

[0121] AG16: Air gap

[0122] s1: Shortest distance

[0123] s2: farthest distance

[0124] S41: Steps

[0125] S42: Steps

[0126] S43: Steps

[0127] S44: Steps

[0128] S45: Steps

[0129] S46: Steps

[0130] S47: Steps

[0131] w1: Size

[0132] w2: Size

[0133] w3: Size

[0134] w4: Size Detailed Implementation

[0135] The following description of this disclosure, accompanied by the accompanying drawings which are incorporated in and form part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0136] Terms such as “an embodiment,” “an embodiment,” “an exemplary embodiment,” “another embodiment,” and “another embodiment” indicate that the embodiments described in this disclosure may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase “in an embodiment” does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0137] The following disclosure provides numerous different embodiments or examples of various features as implementations of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, the various descriptions are merely examples and are not intended to impose limitations. For example, the dimensions of an element are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the element. Furthermore, the description of a first feature being formed "above" or "on" a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features may be formed within the range of the first and second features, thereby potentially preventing the first and second features from being in direct contact. For simplicity and clarity, various features can be drawn at any scale. In the drawings, some layers / features may be omitted for simplicity.

[0138] Figure 1 This is a cross-sectional view illustrating an interconnect structure 1 according to some embodiments of the present disclosure. The interconnect structure 1 may include dielectric layers 10, 14, 16 and 19, conductive vias 11 and 15, and metal lines 12, 13, 17 and 18.

[0139] In some embodiments, interconnect structure 1 may be disposed on a substrate (not shown). In some embodiments, interconnect structure 1 may be part of one or more metallization layers on the substrate of a semiconductor device. Although Figure 1Two metallization layers are illustrated (e.g., a metallization layer including metal lines 12 and 13 and a metallization layer including metal lines 17 and 18), but more intermetallic dielectric layers and associated metal lines and conductive vias may be formed on interconnect structure 1.

[0140] In some embodiments, dielectric layer 14 may be disposed above and spaced apart from dielectric layer 10. In some embodiments, dielectric layer 16 may be disposed above and in contact with dielectric layer 14. For example, dielectric layer 16 may be in direct contact with dielectric layer 14. In some embodiments, dielectric layer 19 may be disposed above and spaced apart from dielectric layer 16. Dielectric layers 10, 14, 16, and 19 may be stacked on top of each other along a stacking direction. In some embodiments, the stacking direction may be substantially perpendicular to surface 101 (e.g., top surface) of dielectric layer 10 and / or surface 161 of dielectric layer 16.

[0141] In some embodiments, dielectric layers 10, 14, 16, and 19 may each comprise a suitable dielectric material. For example, dielectric layers 10, 14, 16, and 19 may each comprise silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), strontium bismuth tantalate (SrBi2Ta2O9, SBT), barium strontium titanate (BaSrTiO3, BST), or combinations thereof. In some embodiments, dielectric layers 10, 14, 16, and 19 may each comprise a dielectric material having a dielectric constant higher than that of silicon dioxide (SiO2), or a dielectric material having a dielectric constant of about 4.0 or greater. In some embodiments, the dielectric material of dielectric layers 10, 14, 16, and 19 may be selected based on one or more selective etching processes, as will be discussed below. Figure 3I and Figure 3P Further description.

[0142] In some embodiments, dielectric layer 10 may define vias 11h and trenches 12h (also in...). Figure 3D (As shown in the image). The trench 12h may be located above the via 11h. For example, the trench 12h may be closer to the surface 101 of the dielectric layer 10 than the via 11h. In some embodiments, the dimension w2 (e.g., width or diameter) of the trench 12h may be larger than the dimension w1 (e.g., width or diameter) of the via 11h. Dimensions w2 and w1 may be measured in a direction substantially parallel to the surface 101 of the dielectric layer 10. In other words, dimensions w2 and w1 may be measured in a direction substantially perpendicular to the stacking direction of the interconnect structure 1.

[0143] In some embodiments, a conductive via 11 may be disposed in the dielectric layer 10. For example, the conductive via 11 may be surrounded by the dielectric layer 10. For example, the conductive via 11 may be in contact with the dielectric layer 10. For example, the conductive via 11 may be disposed in a via 11h. In some embodiments, one end of the conductive via 11 may not be coplanar with the surface 101 of the dielectric layer 10. For example, one end of the conductive via 11 may be located at a height between two opposite sides of the dielectric layer 10. In some embodiments, a portion of the conductive via 11 may be exposed from the dielectric layer 10 to contact the metal wire 12.

[0144] In some embodiments, a conductive via 15 may be disposed in dielectric layers 14 and 16. For example, the conductive via 15 may be surrounded by dielectric layers 14 and 16. For example, the conductive via 15 may contact dielectric layers 14 and 16. In some embodiments, one end of the conductive via 15 may not be coplanar with the surface 161 of the dielectric layer 16. For example, one end of the conductive via 15 may be located at a height between two opposing surfaces of the dielectric layer 16. In some embodiments, a portion of the conductive via 15 may be exposed from the dielectric layer 14 to contact the metal wire 12.

[0145] In some embodiments, conductive vias 11 and 15 may each comprise a suitable conductive material. For example, conductive vias 11 and 15 may each comprise tungsten (W), copper (Cu), aluminum (Al), silver (Ag), alloys thereof, or combinations thereof.

[0146] In some embodiments, the metal wire 12 may be disposed on the dielectric layer 10. In some embodiments, the metal wire 12 may be disposed between the dielectric layers 10 and 14 and electrically connected to conductive vias 11 and 15. In some embodiments, the metal wire 12 may be disposed on the conductive via 11. In some embodiments, the metal wire 12 may be partially disposed in the trench 12h. For example, the metal wire 12 may be partially surrounded by the dielectric layer 10. For example, the metal wire 12 may partially penetrate the dielectric layer 10. For example, the metal wire 12 may partially extend into the dielectric layer 10.

[0147] In some embodiments, the size w2 (e.g., width or diameter) of the metal wire 12 may be larger than the size w1 (e.g., width or diameter) of the conductive via 11.

[0148] In some embodiments, metal wire 13 may be disposed on dielectric layer 10 and adjacent to metal wire 12. In some embodiments, metal wire 13 may be physically spaced from metal wire 12. In some embodiments, metal wire 13 may be disposed between dielectric layers 10 and 14 and electrically connected to conductive vias (not shown) in dielectric layers 10 and 14. In some embodiments, metal wire 13 may be partially surrounded by dielectric layer 10. For example, metal wire 13 may partially penetrate dielectric layer 10. For example, metal wire 13 may partially extend into dielectric layer 10.

[0149] In some embodiments, the metal wire 17 may be disposed on the dielectric layer 16. In some embodiments, the metal wire 17 may be disposed between the dielectric layers 16 and 19 and electrically connected to the conductive via 15 and a conductive via (not shown) in the dielectric layer 19. In some embodiments, the metal wire 17 may be partially surrounded by the dielectric layer 16. For example, the metal wire 17 may partially penetrate the dielectric layer 16. For example, the metal wire 17 may partially extend into the dielectric layer 16.

[0150] In some embodiments, metal wire 18 may be disposed on dielectric layer 16 and adjacent to metal wire 17. In some embodiments, metal wire 18 may be disposed between dielectric layers 16 and 19 and electrically connected to conductive vias (not shown) in dielectric layers 16 and 19. In some embodiments, metal wire 18 may be partially surrounded by dielectric layer 16. For example, metal wire 18 may partially penetrate dielectric layer 16. For example, metal wire 18 may partially extend into dielectric layer 16.

[0151] In some embodiments, metal wires 12, 13, 17, and 18 may each comprise a suitable conductive material. For example, metal wires 12, 13, 17, and 18 may each comprise tungsten (W), copper (Cu), aluminum (Al), silver (Ag), alloys thereof, or combinations thereof.

[0152] In some embodiments, an interface between one of the metal lines 12, 13, 17, and 18 and one of the conductive vias 11 and 15 can be observed. In some embodiments, the material used to fabricate one of the metal lines 12, 13, 17, and 18 may be different from the material used to fabricate one of the conductive vias 11 and 15. For example, the material used to fabricate metal line 12 may be different from the material used to fabricate conductive via 11, and an interface between metal line 12 and conductive via 11 can be observed.

[0153] However, in some other embodiments, the interface between the metal wire 12 and the conductive via 11 may not be observed. In some other embodiments, the metal wire 12 and the conductive via 11 may be made of the same material. The metal wire 12 and the conductive via 11 may alternatively be referred to as the upper part (having a larger dimension w2) and the lower part (having a smaller dimension w1) of the conductive structure, respectively.

[0154] Similarly, the interface between the metal line 17 and the conductive via 15 may not be observed. The metal line 17 and the conductive via 15 can alternatively be referred to as the upper (larger) and lower (smaller) portion of the conductive structure, respectively.

[0155] In some embodiments, a barrier layer (not shown) may surround one or more conductive vias 11 and 15, and metal lines 12, 13, 17, and 18. The barrier layer prevents conductive material from diffusing into adjacent dielectric layers (e.g., dielectric layers 10, 14, and 16). In some embodiments, the barrier layer may include a suitable conductive material, such as titanium (Ti), titanium nitride (TiN), manganese (Mn), alloys thereof, or combinations thereof.

[0156] Furthermore, according to various embodiments, a seed layer (not shown in the figures) can be formed on the barrier layer. The seed layer may include suitable conductive materials such as copper (Cu), nickel (Ni), gold (Au), alloys thereof, or combinations thereof. Additionally, the seed layer may be alloyed with a material that improves the adhesion of the seed layer to serve as an adhesive layer. For example, the seed layer may be alloyed with suitable materials such as manganese (Mn), aluminum (Al), etc., which will migrate to the interface between the seed layer and the barrier layer and enhance the adhesion between the two layers.

[0157] In some embodiments, a portion of the metal wire 12 may be exposed in the air gap AG1. For example, a portion of the metal wire 12 may be exposed to air through the air gap AG1. For example, the metal wire 12 may have a surface 123 contacting the conductive via 15 and the dielectric layer 14, and a surface 122 contacting the conductive via 11 and the dielectric layer 10. Surface 121 of the metal wire 12 between the dielectric layers 10 and 14 may be exposed in the air gap AG1. For example, the metal wire 12 may include opposing surfaces contacting the conductive vias 11 and 15, and surface 121 of the metal wire 12 may extend between the opposing surfaces.

[0158] For example, the surface 121 of the metal line 12 may have a portion 121a and a portion 121b connected to the portion 121a. The portion 121a may be exposed from the dielectric layer 10. The portion 121a may be exposed in the air gap AG1. The portion 121b may be surrounded or covered by the dielectric layer 10. For example, the air gap AG1 may be adjacent to the surface 121 of the metal line 12. For example, the lower portion of the surface 121 of the metal line 12 may be surrounded or covered by the dielectric layer 10, and the upper portion of the surface 121 of the metal line 12 may be exposed from the dielectric layer 10.

[0159] Similarly, in some embodiments, a portion of the metal line 13 may be exposed to the air gap AG1. For example, a portion of the metal line 13 may be exposed to air through the air gap AG1. For example, the surface 131 of the metal line 13 between the dielectric layer 14 and the dielectric layer 10 may be exposed to the air gap AG1.

[0160] For example, the surface 131 of the metal line 13 may have a portion 131a and a portion 131b connected to the portion 131a. The portion 131a may be exposed from the dielectric layer 10. The portion 131a may be exposed in the air gap AG1. The partial surface 131b may be surrounded or covered by the dielectric layer 10. For example, the air gap AG1 may be adjacent to the surface 131 of the metal line 13. For example, the lower portion of the surface 131 of the metal line 13 may be surrounded or covered by the dielectric layer 10, and the upper portion of the surface 131 of the metal line 13 may be exposed from the dielectric layer 10.

[0161] In some embodiments, an air gap AG1 may be defined between metal wires 12 and 13. For example, an air gap AG1 may be defined between surface 121 of metal wire 12 and surface 131 of metal wire 13.

[0162] In some embodiments, metal line 12 may be isolated from metal line 13 by an air gap AG1. For example, metal line 12 may be spaced apart from metal line 13 by an air gap AG1. In some embodiments, surface 101 of dielectric layer 10 may also be exposed in air gap AG1. For example, surface 101 of dielectric layer 10 may have a portion 101a and a portion 101b connected to portion 101a. Portion 101a may be exposed from metal line 12. Portion 101a may be exposed in air gap AG1. Portion 101b may be covered by metal line 12.

[0163] In some embodiments, the dielectric layer 14 may define an air gap AG2 above the air gap AG1. For example, the air gap AG2 may be formed within the dielectric layer 14. For example, the air gap AG2 may penetrate the dielectric layer 14. In some embodiments, air may be conducted between the air gap AG2 and the air gap AG1.

[0164] In some embodiments, the dimension w3 of the air gap AG1 (e.g., the shortest distance between the surfaces 121 of metal line 12 and 131 of metal line 13) may be larger than the dimension w4 (e.g., width or diameter) of the air gap AG2 defined by the dielectric layer 14. In other words, the dimension w4 may be smaller than the dimension w3. For example, the air gap AG2 may be smaller than the air gap AG1. For example, the dielectric layer 14 may include a suspended portion 141 above the air gap AG1. The suspended portion 141 may protrude or extend from the surfaces 121 of metal line 12 and 131 of metal line 13 to be located above the air gap AG1. In some embodiments, the dimensions w3 and w4 may be measured in a direction substantially parallel to the surface 101 of the dielectric layer 10. In other words, the dimensions w3 and w4 may be measured in a direction substantially perpendicular to the stacking direction of the interconnect structure 1.

[0165] In some embodiments, the top (or end) of air gap AG2 may be covered by dielectric layer 16. In some embodiments, air gap AG3 may be physically separated from air gaps AG1 and AG2 by dielectric layer 16. In some embodiments, air gaps AG1 and AG2 may be collectively referred to as the gaps defined between metal lines 12 and 13 and between dielectric layers 10 and 16. In some embodiments, the gaps may be filled with air. In some embodiments, the gaps may be a vacuum. In some embodiments, metal line 12 may be isolated from metal line 13 by the gaps.

[0166] In some embodiments, dielectric layer 14 can be used to establish another metallization layer (including metal lines 17 and 18) over metal lines 12 and 13. The air gap AG2 defined by dielectric layer 14 can help remove the dielectric layer between metal lines 12 and 13 (e.g., ...). Figure 3I The process shown is used to form the air gap AG1. The dielectric layer 16 can be used to prevent the conductive material of the metal lines 17 and 18 from filling the air gap AG1.

[0167] Similarly, an air gap AG3 can be defined between metal lines 17 and 18. A dielectric layer 19 can define an air gap AG4 above the air gap AG3. The air gap AG4 can be smaller than the air gap AG3. For example, the dielectric layer 19 can include a suspended portion 191 on the air gap AG3. The suspended portion 191 can protrude or extend from the surfaces of metal lines 17 and 18 to be located above the air gap AG3. For example, the surface 171 of metal line 17 can have a portion 171a and a portion 171b connected to the portion 171a. The portion 171a can be exposed from the dielectric layer 16. The portion 171a can be exposed in the air gap AG3. The portion 171b can be surrounded or covered by the dielectric layer 16.

[0168] To form more inter-metal dielectric layers and associated metal lines and conductive vias on interconnect structure 1, another dielectric layer can be disposed on dielectric layer 19 and cover the air gap AG4. It should be understood that, although Figure 1 Four air gaps (e.g., air gaps AG1, AG2, AG3, and AG4) are illustrated in interconnect structure 1, but interconnect structure 1 can accommodate any number of air gaps. For simplicity, four air gaps are illustrated.

[0169] In some embodiments, an anti-oxidation layer may be provided at the boundary between the metal lines 12, 13, 17 and 18 and the air gaps (such as air gaps AG1 and AG3) to protect the metal lines 12, 13, 17 and 18 from oxidation.

[0170] According to some embodiments of this disclosure, by isolating adjacent metal lines 12 and 13 through an air gap AG1, the parasitic capacitance between metal lines 12 and 13 can be reduced by approximately 2.5 times or more compared to filling the space between metal lines 12 and 13 with a low-k dielectric material. For example, the air in the air gap AG1 exhibits a dielectric constant of approximately 1. This low dielectric constant helps to reduce capacitive coupling between adjacent metal lines 12 and 13. Therefore, the overall performance characteristics of the semiconductor device including the interconnect structure 1 can be improved.

[0171] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G These are top views, each illustrating a portion of the interconnection structure of some embodiments of this disclosure. In some embodiments, Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G The interconnect structure can be similar to Figure 1 Interconnection structure 1. In some embodiments, for a better understanding of the various embodiments of this disclosure, Figure 1 Some elements in Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G The text has been simplified or is not displayed.

[0172] Dielectric layer 20 can be with Figure 1 Similar to dielectric layer 14. Metal lines 21, 22, and 23 can be similar to... Figure 1 Metal wires 12 and 13 in the example. Figure 2A As shown, air gaps AG5 and AG6 defined by dielectric layer 20 can be spaced apart from metal lines 21, 22 and 23 to prevent metal lines 21, 22 and 23 from being damaged or destroyed. For example, the projected areas of air gaps AG5 and AG6 may not overlap with the projected areas of metal lines 21, 22 and 23 on dielectric layer 20.

[0173] Reference Figure 2A The surfaces 211 and 221 of metal wire 21 and metal wire 22 can be exposed to an air gap below air gap AG5 (e.g., Figure 1 Air gap AG1). Air gap AG5 is smaller than the air gap below and is located between surface 211 of metal wire 21 and surface 221 of metal wire 22. In some embodiments, air gap AG5 may be substantially located in the middle of the gap or spacing between surface 211 of metal wire 21 and surface 221 of metal wire 22. For example, the distance between air gap AG5 and surface 211 of metal wire 21 (e.g., the shortest distance) may be substantially equal to the distance between air gap AG5 and surface 221 of metal wire 22 (e.g., the shortest distance). Similarly, air gap AG6 may be substantially located in the middle of the gap or spacing between metal wire 22 and metal wire 23.

[0174] Reference Figure 2B In some embodiments, the metal wire 21 may have a short side 212 shorter than the surface 211 (also referred to as the long side of the metal wire 21). In some embodiments, the air gap AG7 may be disposed adjacent to the short side 212 of the metal wire 21. The short side 212 of the metal wire 21 may be exposed to the air gap below the air gap AG7 (not shown in the figure). The air gap AG7 is smaller than the air gap below. Similarly, the air gap AG8 may be disposed near the short side 222 of the metal wire 22, and the air gap AG9 may be disposed near the short side of the metal wire 23.

[0175] Reference Figure 2C In some embodiments, metal wires 22 and 23 may have corners or turning points.

[0176] In some embodiments, air gap AG10 may be adjacent to one corner of metal wire 22, and air gap AG11 may be adjacent to one corner of metal wire 23. For example, from a top view, air gap AG10 may be partially surrounded by metal wire 22, and air gap AG11 may be partially surrounded by metal wire 23.

[0177] Reference Figure 2D In some embodiments, the air gap AG12 may be adjacent to the conductive via 21v electrically connected to the metal wire 21. The conductive via 21v may be similar to... Figure 1 Conductive vias 11 and 15 are shown in the image.

[0178] Reference Figure 2EIn some embodiments, the spacing between metal lines 21 and 22 may not be constant. For example, the shortest distance s1 between metal lines 21 and 22 may be approximately 112 nanometers (nm). The farthest distance s2 between metal lines 21 and 22 may be greater than 112 nm. An air gap AG13 may be located in the gap between metal lines 21 and 22 having a longer or greater spacing or distance (such as the longest distance s2). An air gap AG14 may be located in the gap between metal lines 22 and 23, provided that the spacing or distance of the gap is longer than or greater than approximately 112 nanometers. In some embodiments, the spacing or distance of the gaps may be adjusted based on design requirements, such as the spacing and interval of the metal lines.

[0179] According to some embodiments of this disclosure, the air gaps of different positions, sizes, shapes, and forms described above can be combined or exist in conjunction with... Figure 1 In interconnect structures similar to interconnect structure 1. For example, refer to Figure 2F In some embodiments, the air gap AG7 (also) Figure 2B (As shown in the diagram) can be positioned near the short side 212 of the metal wire 21, while the air gap AG5 (also shown in the diagram) can be positioned near the short side 212 of the metal wire 21. Figure 2A (As shown in the diagram) can be positioned near the long side 211 of the metal wire 21. Therefore, the short side 212 and the long side 211 of the metal wire 21 can be exposed to an air gap (as shown in the diagram) below the air gap AG7. Figure 1 In the air gap AG1) and the air gap AG5 below (such as Figure 1 (Air gap AG1 in the middle).

[0180] Furthermore, in some embodiments, air gaps AG15 and AG5 may be aligned. For example, the spacing between the surface 211 of metal wire 21 and the surface 221 of metal wire 22 may be constant, and air gaps AG15 and AG5 may be aligned, for example, arranged in a straight line. (See also...) Figure 2G In some embodiments, the air gap AG16 may be located in the gap between metal wires 21 and 22, with a short or small spacing or distance, while the air gap AG13 (also shown) Figure 2E The middle part can be located in the gap between metal wire 21 and metal wire 22, and the spacing or distance between them can be relatively long or large.

[0181] To prevent damage or breakage of metal lines 21 and 22, air gap AG16 can be smaller than air gap AG13. For example, the projected area of ​​air gap AG16 can be smaller than the projected area of ​​air gap AG13 on dielectric layer 20. However, in some other embodiments, the air gaps can be substantially the same size to facilitate better process control.

[0182] Furthermore, in some embodiments, the air gap AG14 (also) Figure 2E(as shown in the image) may be closer to metal wire 23 than metal wire 22. In some embodiments, air gap AG11 (also shown in the image) may be closer to metal wire 23 than metal wire 22. Figure 2C (As shown in the image) can be adjacent to the corner of metal line 23, while other air gaps may not be adjacent to the corner.

[0183] According to some embodiments of this disclosure, the location, size, shape, and form of the air gap can be adjusted based on design requirements and are not limited to the specific embodiments illustrated in the figures.

[0184] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K , Figure 3L , Figure 3M , Figure 3N , Figure 3O , Figure 3P and Figure 3Q The figures illustrate the fabrication stages of a method for fabricating interconnect structures according to some embodiments of this disclosure. To better understand the various embodiments of this disclosure, at least some of these figures have been simplified. In some embodiments, Figure 1 The interconnection structure 1 in the middle can be described by the following about Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 3I , Figure 3J , Figure 3K , Figure 3L , Figure 3M , Figure 3N , Figure 3O , Figure 3P and Figure 3Q It is prepared using a specific process.

[0185] Reference Figure 3A The dielectric layer 10 can be disposed on a substrate (not shown in the figure). A sacrificial layer 30 can be disposed on the dielectric layer 10. The sacrificial layer 30 can have or exhibit different etch characteristics than the dielectric layer 10. For example, in... Figure 3IIn a selective etching process, the etching rate of the sacrificial layer 30 can be greater than that of the dielectric layer 10. In some embodiments, the sacrificial layer 30 may comprise a low dielectric constant dielectric material, such as silicon dioxide (SiO2), fluorosilicate glass (FSG), or flowable oxide (FOx). In some embodiments, the sacrificial layer 30 may be fabricated using a suitable deposition process, such as chemical vapor deposition (CVD).

[0186] Reference Figure 3B A photoresist layer 31 and a mask film (not shown) can be formed on the sacrificial layer 30. The photoresist layer 31 can be formed according to the location and shape of the conductive vias to be formed in the sacrificial layer 30 and the dielectric layer 10 (e.g., Figure 1 The conductive vias 11 shown are patterned. More specifically, the photoresist layer 31 can be exposed and developed as part of a suitable photolithography process. After the photolithography process is completed, as shown... Figure 3B As shown, a via 11h of size w1 can be formed in the sacrificial layer 30 and the dielectric layer 10.

[0187] Reference Figure 3C ,like Figure 3B The remaining photoresist layer 31 shown can be removed using suitable photoresist stripping techniques, such as chemical solvent cleaning, plasma ashing, or dry stripping.

[0188] Reference Figure 3D A photoresist layer 32 and a mask film (not shown) can be formed on the sacrificial layer 30. The photoresist layer 32 can be formed according to the metal lines (e.g., those formed in the sacrificial layer 30 and dielectric layer 10) to be formed in the sacrificial layer 30 and dielectric layer 10. Figure 1 The positions and shapes of the metal lines 12 and 13 shown are patterned. More specifically, the photoresist layer 32 can be exposed and developed as part of a suitable photolithography process. After the photolithography process is completed, trenches 12h and 13h of size w2 can be formed in the sacrificial layer 30 and the dielectric layer 10, as shown. Figure 3D As shown. Trench 12h may be above via 11h. The size w2 of trench 12h may be larger than the size w1 of via 11h. In some embodiments, trench 12h may be fabricated by an etching process to etch a portion of sacrificial layer 30 and a portion of dielectric layer 10.

[0189] Reference Figure 3E ,like Figure 3D The remaining photoresist layer 32 shown can be removed using a suitable photoresist stripping technique, such as chemical solvent cleaning, plasma ashing, or dry stripping.

[0190] Reference Figure 3F The conductive material of the conductive via 11 can be formed in Figure 3D In the through-hole 11h shown, the conductive material of metal wires 12 and 13 can be formed in... Figure 3D In the trenches 12h and 13h shown. The conductive material can be fabricated using techniques such as electroplating, electroless plating, CVD, physical vapor deposition (PVD), etc. In some embodiments, the metal line 12 and the conductive via 11 can be formed from the same material. In this embodiment, the interface between the metal line 12 and the conductive via 11 may not be observed. In some embodiments, the conductive via 11, the metal line 12, and the metal line 13 can be fabricated using a dual damascene technique. In some embodiments, the conductive via 11, the metal line 12, and the metal line 13 can be formed in the same process.

[0191] In some embodiments, a barrier layer and / or a seed layer (not shown) may be provided in the via 11h and trenches 12h and 13h. Therefore, a barrier layer and / or a seed layer may be formed around the conductive via 11, the metal line 12 and / or the metal line 13.

[0192] In some embodiments, a planarization process can be performed to remove excess conductive material. The planarization process can be achieved using appropriate techniques such as grinding, polishing, chemical etching, etc.

[0193] Reference Figure 3G Dielectric layer 14 can be disposed on sacrificial layer 30 and metal lines 12 and 13. Dielectric layer 14 can have or exhibit etch characteristics different from those of sacrificial layer 30. For example, in Figure 3I In a selective etching process, the etching rate of the sacrificial layer 30 may be greater than the etching rate of the dielectric layer 14. In some embodiments, the dielectric layer 14 can be fabricated using a suitable deposition process, such as CVD.

[0194] Reference Figure 3H A photoresist layer 33 and a mask film (not shown) can be formed above the dielectric layer 14. The photoresist layer 33 can be patterned, exposed, and developed as part of a suitable photolithography process. After the photolithography process is completed, as... Figure 3H As shown, an air gap AG2 of size w4 can be formed in the dielectric layer 14. The air gap AG2 defined by the dielectric layer 14 can be spaced apart from the metal lines 12 and 13 to prevent the metal lines 12 and 13 from being damaged or destroyed.

[0195] In some embodiments, a portion of the sacrificial layer 30 may be exposed through the air gap AG2. In some embodiments, a portion 30a of the sacrificial layer 30 may be removed through the air gap AG2.

[0196] In some embodiments, the air gap AG2 can help remove the sacrificial layer 30 in subsequent processes. It should be understood that... Figure 3H The shape of the air gap AG2 shown is for illustrative purposes only and does not limit the various embodiments of this disclosure. For example, the air gap AG2 includes other shapes, such as, but not limited to, trapezoidal, elliptical, square, triangular, etc., all of which are within the scope and spirit of this disclosure.

[0197] Reference Figure 3I A selective etching process can be performed to remove the sacrificial layer 30. The etching rate of the sacrificial layer 30 can be greater than the etching rate of the dielectric layer 10, so the substrate (not shown in the figure) under the dielectric layer 10 can be protected from erosion.

[0198] After removing the sacrificial layer 30, an air gap AG1 can be formed between metal lines 12 and 13. Air gap AG1 can be located below air gap AG2. The surfaces 121 of metal line 12, 131 of metal line 13, and 101 of dielectric layer 10 can be exposed to air through air gaps AG1 and AG2. For example, surface 101 of dielectric layer 10 can have a portion 101a and a portion 101b connected to portion 101a. Portion 101a can be exposed from metal line 12. Portion 101a can be exposed in air gap AG1. Portion 101b can be covered by metal line 12.

[0199] Reference Figure 3J ,like Figure 3I The remaining photoresist layer 33 shown can be removed using suitable photoresist stripping techniques, such as chemical solvent cleaning, plasma ashing, dry stripping, etc.

[0200] Reference Figure 3K Dielectric layer 16 can be disposed on dielectric layer 14 to cover air gap AG2. Dielectric layer 16 can be used to prevent conductive materials (e.g., Figure 3M In the process shown, the conductive material of metal wires 17 and 18 is filled into air gaps AG1 and AG2. Figure 3A Similar to the process described above, sacrificial layer 34 can be disposed on dielectric layer 16. Sacrificial layer 34 can have or exhibit etch characteristics different from those of dielectric layer 16. For example, in... Figure 3P In the selective etching process, the etching rate of the sacrificial layer 34 can be greater than the etching rate of the dielectric layer 16.

[0201] Reference Figure 3L Similar to Figure 3B , Figure 3C , Figure 3D and Figure 3EThe process can be repeated. Specifically, via 15h can be formed in the sacrificial layer 34 and the dielectric layer 16. Trench 17h and 18h ​​can then be formed by etching a portion of the sacrificial layer 34 and a portion of the dielectric layer 16. Via 15h can be exposed from trench 17h.

[0202] Reference Figure 3M ,and Figure 3F Similar to the process described above, the conductive material of the conductive via 15 can be formed in... Figure 3L In the through-hole 15h shown, the conductive material of metal wires 17 and 18 can be formed. Figure 3L The trenches 17h and 18h ​​are shown in the diagram. The conductive material can be fabricated using suitable processes such as electroplating, electroless plating, CVD, PVD, etc. In some embodiments, the metal lines 17 and 18 and the conductive via 15 can be fabricated using the same material. In this embodiment, the interface between the metal line 17 and the conductive via 15 may not be observed. In some embodiments, the conductive via 15, the metal lines 17 and 18 can be fabricated using a dual damascene structure technique. In some embodiments, the conductive via 15, the metal lines 17 and 18 can be formed in the same process.

[0203] Reference Figure 3N ,and Figure 3G Similar to the process described above, dielectric layer 19 can be disposed on sacrificial layer 34 and metal lines 17 and 18. Dielectric layer 19 may have or exhibit different etching characteristics than sacrificial layer 34.

[0204] Reference Figure 3O ,and Figure 3H Similar to the process described above, a photoresist layer 35 and a mask film (not shown) can be formed on the dielectric layer 19. The photoresist layer 35 can be patterned, exposed, and developed as part of a suitable photolithography process. After the photolithography process is completed, as... Figure 3O As shown, an air gap AG4 can be formed in the dielectric layer 19. The air gap AG4 defined by the dielectric layer 19 can be spaced apart from the metal lines 17 and 18 to prevent the metal lines 17 and 18 from being damaged or destroyed.

[0205] Reference Figure 3P A selective etching process can be performed to remove the sacrificial layer 34. The etching rate of the sacrificial layer 34 can be greater than the etching rate of the dielectric layer 16, so the components under the dielectric layer 16 can be protected from corrosion.

[0206] After removing the sacrificial layer 34, an air gap AG3 can be formed between metal lines 17 and 18. The air gap AG3 can be located below the air gap AG4. A portion of metal line 17, a portion of metal line 18, and the surface 161 of dielectric layer 16 can be exposed to air through air gaps AG3 and AG4.

[0207] Reference Figure 3Q ,like Figure 3P The remaining photoresist layer 35 shown can be removed using suitable photoresist stripping techniques, such as chemical solvent cleaning, plasma ashing, or dry stripping.

[0208] Figure 4 This is a flowchart illustrating a method 40 for fabricating an interconnect structure according to some embodiments of this disclosure.

[0209] In some embodiments, the fabrication method 40 may include step S41, which involves forming a sacrificial layer on a first dielectric layer. For example, such as... Figure 3A As shown, the sacrificial layer 30 can be disposed on the dielectric layer 10.

[0210] In some embodiments, fabrication method 40 may include step S42, forming a trench in the first dielectric layer and the sacrificial layer. For example, as... Figure 3D As shown, trenches 12h and 13h with size w2 can be formed in the sacrificial layer 30 and the dielectric layer 10.

[0211] In some embodiments, the preparation method 40 may include step S43, forming a metal wire in the trench. For example, metal wires 12 and 13 may be formed in trenches 12h and 13h, such as... Figure 3F As shown.

[0212] In some embodiments, the fabrication method 40 may include step S44, which involves depositing a second dielectric layer on the sacrificial layer. For example, such as... Figure 3G As shown, dielectric layer 14 can be disposed on sacrificial layer 30.

[0213] In some embodiments, fabrication method 40 may include step S45, forming an opening in the second dielectric layer. For example, as... Figure 3H As shown, an air gap AG2 with a size of w4 can be formed in the dielectric layer 14.

[0214] In some embodiments, the fabrication method 40 may include step S46, removing the sacrificial layer from the first dielectric layer. For example, after removing the sacrificial layer 30, an air gap AG1 may be formed between the metal line 12 and the metal line 13, such as... Figure 3I As shown.

[0215] In some embodiments, the fabrication method 40 may include step S47, which involves forming a third dielectric layer on the second dielectric layer to cover the opening. For example, as... Figure 3K As shown, dielectric layer 16 can be disposed on dielectric layer 14 to cover air gap AG2.

[0216] To better understand the various embodiments of this disclosure, at least some of these steps have been simplified. In some embodiments, Figure 1 The interconnection structure 1 in the middle can be related to Figure 4 The preparation is carried out using the following steps.

[0217] One embodiment of this disclosure provides an interconnect structure, including: a first dielectric layer, a first conductive via, and a first metal line. The first conductive via is disposed in the first dielectric layer. The first metal line is disposed on the first dielectric layer and electrically connected to the first conductive via. At least a portion of the first metal line is exposed in a first air gap.

[0218] Another embodiment of this disclosure provides an interconnect structure, including: a first dielectric layer, a second dielectric layer, a first conductive structure, and a second conductive structure. The second dielectric layer is disposed above the first dielectric layer. The first conductive structure is disposed between the first dielectric layer and the second dielectric layer. The second conductive structure is disposed between the first dielectric layer and the second dielectric layer. The second conductive structure is isolated from the first conductive structure by a first air gap.

[0219] Another embodiment of this disclosure provides a method for fabricating an interconnect structure, comprising: depositing a sacrificial layer on a first dielectric layer, the sacrificial layer having etch characteristics different from those of the first dielectric layer; forming a trench in the first dielectric layer and the sacrificial layer; forming a first metal line in the trench; and removing the sacrificial layer from the first dielectric layer.

[0220] The air in the air gap exhibits a dielectric constant of approximately 1. This low dielectric constant helps reduce capacitive coupling between adjacent metal lines. Therefore, the overall performance characteristics of semiconductor devices, including interconnect structures, can be improved.

[0221] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined by the scope of the disclosed patent. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0222] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the content of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described in this invention can be used in accordance with this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of this patent disclosure.

Claims

1. An interconnect structure, comprising: a first dielectric layer; a first conductive via disposed in the first dielectric layer; and a first metal line disposed on the first dielectric layer and electrically connected to the first conductive via; wherein at least a portion of a sidewall of the first metal line is exposed to a first air gap; a second dielectric layer disposed on the first metal line and defining a second air gap above the first air gap; a second conductive via penetrating the second dielectric layer and electrically connected to the first metal line; a third dielectric layer disposed on the second dielectric layer and covering the second air gap; a third metal line disposed on the third dielectric layer and electrically connected to the second conductive via, wherein at least a portion of a sidewall of the third metal line is exposed to a third air gap.

2. The interconnect structure of claim 1, wherein a portion of a top surface of the first dielectric layer is exposed to the first air gap.

3. The interconnect structure of claim 1, wherein the first metal line includes a first lateral surface exposed to the first air gap and a second lateral surface in contact with the first dielectric layer.

4. The interconnect structure of claim 1, further comprising: a second metal line disposed on the first dielectric layer and physically spaced apart from the first metal line, wherein at least a portion of the second metal line is exposed to the first air gap.

5. The interconnect structure of claim 1, wherein a width of the second air gap is less than a width of the first air gap.

6. The interconnect structure of claim 1, wherein the third air gap is physically isolated from the second air gap by the third dielectric layer.

7. An interconnect structure, comprising: a first dielectric layer; a second dielectric layer disposed above the first dielectric layer; a first conductive structure disposed between the first dielectric layer and the second dielectric layer; and a second conductive structure disposed between the first dielectric layer and the second dielectric layer, wherein the second conductive structure is laterally isolated from the first conductive structure by a first air gap; wherein the second dielectric layer defines a second air gap above the first air gap, and a width of the second air gap is less than a width of the first air gap; a third dielectric layer disposed on the second dielectric layer and covering the second air gap; and a third conductive structure disposed on the third dielectric layer and electrically connected to the first conductive structure, wherein a sidewall of the third conductive structure is exposed to a third air gap, and the third air gap is physically isolated from the second air gap by the third dielectric layer.

8. The interconnect structure of claim 7, wherein the first conductive structure includes a first lateral surface exposed to the first air gap and a second lateral surface in contact with the first dielectric layer. ​ ​

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