A transient voltage suppressor

Abstract

This invention discloses a transient voltage suppressor, comprising a unit component. The unit component includes a substrate, a first deep well region, a second deep well region, a Zener coupling region, a first injection region, and a second injection region. The first and second deep well regions are disposed on the substrate, alternating along the surface direction of the substrate. The first and second deep well regions have opposite conductivity types. A Zener coupling region is disposed within the second deep well region. The first and second injection regions are spaced apart within the Zener coupling region. All first injection regions are electrically connected to form a first working terminal, and all second injection regions are electrically connected to form a second working terminal. This invention employs a multi-parallel structure to release large currents, clamping the voltage to a safe level. It can integrate more transistor structures within the same area, effectively increasing current capability and making it suitable for high-power surge protection.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit protection device technology, and in particular to a transient voltage suppressor. Background Technology

[0002] A transient voltage suppressor (TVS) is a commonly used circuit protection component. When a TVS is subjected to a high-energy reverse surge, it can reduce the voltage by 10%. －12 At speeds up to s, the impedance between its two poles decreases from high to low, absorbing surge power of up to several kW, clamping the potential between the two poles to a predetermined value, and effectively protecting the components in the circuit from damage by surge pulses.

[0003] In high-power protection applications, traditional transient voltage suppressors often employ vertical diodes, transistors, and other structures in their design, achieving high voltage through multi-chip series stacking. For example, in 90V applications, three 30V high-power devices are often stacked in series, while in 60V applications, two devices are often stacked in series. The advantage of this approach is that different voltages can be achieved with the same current capability through stacking. However, traditional transient voltage suppressors have limited current-carrying capacity and low power density. If a device with higher current is required, the area of ​​a single vertical device needs to be increased, thus increasing cost and impacting circuit board layout. Summary of the Invention

[0004] The technical problem to be solved and the technical task proposed by the present invention is to improve the existing technology and provide a transient voltage suppressor that solves the problems of limited current carrying capacity and low power density of the current transient voltage suppressor, which adopts a multi-chip vertical device series stacked structure.

[0005] To solve the above technical problems, the technical solution of the present invention is as follows:

[0006] A transient voltage suppressor includes a unit component, the unit component comprising a substrate, a first deep well region, a second deep well region, a Zener coupling region, a first injection region, and a second injection region;

[0007] A first deep well region and a second deep well region are disposed on the substrate, and the first deep well region and the second deep well region are alternately distributed along the surface direction of the substrate. The first deep well region and the second deep well region have opposite conductivity types, and a Zener coupling region is disposed in the second deep well region.

[0008] The first injection region and the second injection region are alternately disposed in the Zener coupling region;

[0009] All first injection regions are electrically connected to form a first working terminal, and all second injection regions are electrically connected to form a second working terminal.

[0010] Furthermore, during ion implantation, the Zener coupling region is subjected to an ion implantation energy of 60–140 keV and is separated by a sacrificial oxide layer with a thickness of 360–420 angstroms.

[0011] Furthermore, the ion implantation tilt angle of the Zener coupling region is 8 to 12 degrees.

[0012] Furthermore, the first deep well region and the second deep well region are grown on the substrate.

[0013] Furthermore, the Zener coupling region and the second deep well region have opposite conductivity types.

[0014] Furthermore, the first injection region and the second injection region are respectively one of the P+ injection region and the N+ injection region.

[0015] Furthermore, the first injection region and the second injection region are injection regions of the same type.

[0016] Furthermore, the first and second injection regions have the opposite conductivity type to the Zener coupling region.

[0017] Furthermore, all the first injection regions are connected to all the second injection regions via different metal interconnects.

[0018] Furthermore, the conductivity type includes P-type and N-type, with the first deep well region being a P-type deep well region and the second deep well region being an N-type deep well region; or the first deep well region being an N-type deep well region and the second deep well region being a P-type deep well region.

[0019] Furthermore, it includes several unit components connected in series. The first working terminal of the first unit component forms the first working electrode of the transient voltage suppressor. The second working terminal of the preceding unit component is electrically connected to the first working terminal of the following unit component. The second working terminal of the last unit component forms the second working electrode of the transient voltage suppressor.

[0020] Compared with the prior art, the advantages of this invention are:

[0021] The transient voltage suppressor described in this invention adopts a multi-parallel structure, which can release large current. The transistor structure composed of the first injection region, Zener coupling region and the second injection region will start to work when it encounters external static electricity or surge, thereby clamping the voltage to a safe level. More transistor structures can be integrated in the same area, effectively increasing the current capability. Furthermore, the unit components are stacked in series, which can realize the function of single-chip high voltage, and is suitable for high-power surge protection. Attached Figure Description

[0022] Figure 1 This is a schematic cross-sectional view of a unit component of the transient voltage suppressor of the present invention;

[0023] Figure 2 This is a schematic diagram of multiple unit components of the transient voltage suppressor of the present invention stacked in series.

[0024] In the picture:

[0025] Substrate 1, First deep well region 2, Second deep well region 3, Zener coupling region 4, First implantation region 5, Second implantation region 6, First working terminal 7, Second working terminal 8. Detailed Implementation

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0027] This invention discloses a transient voltage suppressor with a compact structure and a parallel packaging structure, which can effectively increase current capability and realize the function of single-chip high voltage, making it suitable for high-power surge protection.

[0028] Example 1

[0029] like Figure 1 As shown, a transient voltage suppressor includes a unit component. The transient voltage suppressor may contain only one unit component or multiple unit components. The unit component includes a substrate 1, a first deep well region 2, a second deep well region 3, a Zener coupling region 4, a first implantation region 5, and a second implantation region 6.

[0030] The substrate 1 has a first deep well region 2 and a second deep well region 3 disposed on it. The substrate 1 is flat. The first deep well region 2 and the second deep well region 3 are disposed along the upper surface of the substrate 1, and the first deep well region 2 and the second deep well region 3 are alternately distributed along the surface direction of the substrate 1. The first deep well region 2 and the second deep well region 3 are both grown on the substrate 1 and are in direct contact with the substrate 1. That is, along a certain direction on the upper surface of the substrate 1, there are first deep well region 2, second deep well region 3, first deep well region 2, second deep well region 3, and first deep well region 2, etc. Specifically, the first deep well region 2 and the second deep well region 3 are alternately distributed along a straight line, curve or circle on the upper surface of the substrate 1. The first deep well region 2 and the second deep well region 3 have opposite conductivity types, including P-type and N-type. In this embodiment, the first deep well region 2 is a P-type deep well and the second deep well region 3 is an N-type deep well. The substrate 1 is a P-type substrate.

[0031] A Zener coupling region 4 is provided in the second deep well region 3. The Zener coupling region 4 has the opposite conductivity type to the second deep well region 3. In this embodiment, the Zener coupling region 4 is a P-type Zener coupling region. The Zener coupling region 4 is fabricated by a special process. The Zener coupling region 4 is different from the traditional high-energy Zener ion implantation method. First, it avoids wafer surface defects caused by high-energy ion implantation by using low-energy ion implantation (traditional high-energy ion implantation energy is at least greater than 200 keV, while the ion implantation energy to form the Zener coupling region 4 is only 60-140 keV, preferably 100 keV). It is separated by a sacrificial oxide layer with a thickness of 360-420 angstroms (preferably a sacrificial oxide layer of 400 angstroms). On the other hand, the ion implantation tilt angle when forming the Zener coupling region 4 is controlled at 8-12 degrees, preferably 10 degrees. Precise control of ion implantation energy and ion implantation tilt angle can make the implanted ion concentration distribution compatible with the conventional P-well or N-well annealing process. After subsequent P-well or N-well annealing, the Zener coupling region 4 has the advantages of low leakage current, current equalization, and uniform triggering. The Zener coupling region 4 is embedded in the second deep well region 3, and the upper surface of the Zener coupling region 4 is flush with the upper surface of the second deep well region 3.

[0032] The first injection region 5 and the second injection region 6 are disposed at intervals in the Zener coupling region 4. Specifically, the first injection region 5 and the second injection region 6 are embedded in the Zener coupling region 4 and are flush with the top surface of the Zener coupling region 4. In this embodiment, the first injection region 5 and the second injection region 6 have opposite conductivity types to the Zener coupling region 4. Therefore, the first injection region 5 and the second injection region 6 are both N+ injection regions. The first injection region 5, the Zener coupling region 4 and the second injection region 6 together constitute an NPN transistor structure.

[0033] All first injection regions 5 in the unit component are electrically connected to form a first working terminal 7, that is, the first injection regions 5 are electrically connected to the same potential. All second injection regions 6 in the unit component are electrically connected to form a second working terminal 8, that is, the second injection regions 6 are electrically connected to the same potential. Specifically, all first injection regions 5 are electrically connected through metal interconnects, and all second injection regions 6 are electrically connected through another set of metal interconnects. A dielectric layer (not shown in the figure) covers the upper surfaces of the first injection regions 5 and the second injection regions 6. The material of the dielectric layer can be silicon dioxide, doped or undoped silicon glass, etc., and its formation method can be chemical vapor deposition. Contact holes are formed on the dielectric layer through photolithography, etching, and other processes. Each contact hole exposes the first injection region 5 and the second injection region 6 respectively. Metal material is deposited on the layer, and the contact holes are filled with metal material. Then, metal interconnects are obtained by photolithography and etching. The metal material can include one or more of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W and Al. The metal interconnects are electrically connected to the first injection region 5 and the second injection region 6 through the contact holes. When the transient voltage suppressor contains only one unit component, the first working terminal 7 leads out to form the working electrode of the transient voltage suppressor, and the second working terminal 8 leads out to form the other working electrode of the transient voltage suppressor. In use, the first working terminal 7 can be the anode and the second working terminal 8 can be the cathode, or the first working terminal 7 can be the cathode and the second working terminal 8 can be the anode. That is, the anode and cathode of the transient voltage suppressor are interchangeable.

[0034] In this embodiment, since all the first injection regions 5 are electrically connected to form the first working terminal 7, and all the second injection regions 6 are electrically connected to form the second working terminal 8, that is, the NPN transistor structure composed of the first injection region 5, the Zener coupling region 4, and the second injection region 6 is connected in multiple parallel configurations. Taking the first working terminal 7 as the anode and the second working terminal 8 as the cathode, when an external electrostatic discharge (ESD) or surge signal enters the anode of the transient voltage suppressor, the first injection region 5 and the Zener coupling region 4 will break down. When the junction voltage between the Zener coupling region 4 and the second injection region 6 reaches 0.7V, the NPN transistor structure will start working, releasing a large current and clamping the voltage. The smaller the process linewidth, the more NPN transistor structures can be integrated in the same area, effectively increasing the current capability. With the same number of chips, it can exceed the current capability of vertical products of the same level, and has a higher current capability than traditional devices, thereby improving the overall power density.

[0035] Example 2

[0036] like Figure 1As shown, the difference from Embodiment 1 is that the substrate 1 in the unit component is an N-type substrate, the first deep well region 2 is an N-type deep well, the second deep well region 3 is a P-type deep well, the Zener coupling region 4 is an N-type Zener coupling region, and the first injection region 5 and the second injection region 6 are both P+ injection regions. In this embodiment, the first working end 7 and the second working end 8 of the unit component respectively constitute the anode and cathode of the transient voltage suppressor. In use, the anode and cathode of the transient voltage suppressor can be interchanged.

[0037] Example 3

[0038] like Figure 1 As shown, the difference from Embodiment 1 is that the substrate 1 in the unit component is a P-type substrate, the first deep well region 2 is a P-type deep well, the second deep well region 3 is an N-type deep well, the Zener coupling region 4 is a P-type Zener coupling region, the first injection region 5 is an N+ injection region, and the second injection region 6 is a P+ injection region. In this embodiment, the first working end 7 of the unit component constitutes the anode of the transient voltage suppressor, and the second working end 8 of the unit component constitutes the cathode of the transient voltage suppressor. The anode and cathode of the transient voltage suppressor are not interchangeable during use, and the transient voltage suppressor is only a unidirectional device.

[0039] Example 4

[0040] like Figure 2 As shown, the transient voltage suppressor comprises multiple unit components connected in series. The first working terminal 7 of the first unit component constitutes the first working electrode of the transient voltage suppressor. The second working terminal 8 of the preceding unit component is electrically connected to the first working terminal 7 of the following unit component. The second working terminal 8 of the last unit component constitutes the second working electrode of the transient voltage suppressor. The first and second working electrodes are the anode and cathode, respectively. When using the unit components in Embodiment 1 and Embodiment 2, the anode and cathode of the transient voltage suppressor can be interchanged during use. When using the unit components in Embodiment 3, the anode and cathode of the transient voltage suppressor cannot be interchanged during use, and it is only a unidirectional device.

[0041] The electrical connection between the second working terminal 8 of the preceding unit component and the first working terminal 7 of the following unit component means that all the second injection regions 6 in the preceding unit component and all the first injection regions 5 in the following unit component are electrically connected together. The second working terminal 8 of the preceding unit component and the first working terminal 7 of the following unit component are connected to the same potential, so that the transistor structures in each unit group are first connected in parallel and then connected in series with the next unit group. The definition of the second working terminal 8 of the preceding unit component and the first working terminal 7 of the following unit component is for ease of description. Specifically, all the second injection regions 6 in the preceding unit component and all the first injection regions 5 in the following unit component are connected through metal interconnects.

[0042] Different unit components are integrated together using the same substrate. The first deep well region 2 and the second deep well region 3 in each unit component are alternately distributed along a straight line on the upper surface of the substrate 1, and the different unit components are then distributed in parallel intervals.

[0043] The transient voltage suppressor described in this embodiment is composed of multiple transistor structures connected in series through a high-voltage isolation structure. It is suitable for high-power surge protection. The unit component has multiple transistor structures connected in parallel, which can release large current and clamp the voltage. Then the unit components are stacked in series to provide sufficient withstand voltage and can realize the function of single-chip high voltage.

[0044] The above are merely preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be considered as limitations on the present invention, and the scope of protection of the present invention should be determined by the scope defined in the claims. For those skilled in the art, several improvements and modifications can be made without departing from the spirit and scope of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A transient voltage suppressor, characterized in that, The unit includes a substrate (1), a first deep well region (2), a second deep well region (3), a Zener coupling region (4), a first implantation region (5), and a second implantation region (6). A first deep well region (2) and a second deep well region (3) are provided on the substrate (1), and the first deep well region (2) and the second deep well region (3) are alternately distributed along the surface direction of the substrate (1). The first deep well region (2) and the second deep well region (3) have opposite conductivity types. A Zener coupling region (4) is provided in the second deep well region (3). The first injection region (5) and the second injection region (6) are spaced apart in the Zener coupling region (4); All the first injection regions (5) are electrically connected to form a first working end (7), and all the second injection regions (6) are electrically connected to form a second working end (8). The Zener coupling region (4) and the second deep well region (3) have opposite conductivity types; The first injection region (5) and the second injection region (6) are respectively one of the P+ injection region and the N+ injection region, and the first injection region (5) and the second injection region (6) are injection regions of the same type; The first injection region (5) and the second injection region (6) are of opposite conductivity type to the Zener coupling region (4).

2. The transient voltage suppressor according to claim 1, characterized in that, The Zener coupling region (4) is implanted with an ion implantation energy of 60~140keV and is separated by a sacrificial oxide layer with a thickness of 360~420 angstroms.

3. The transient voltage suppressor according to claim 2, characterized in that, The ion implantation tilt angle of the Zener coupling region (4) is 8 to 12 degrees.

4. The transient voltage suppressor according to claim 1, characterized in that, The first deep well region (2) and the second deep well region (3) are grown on the substrate (1).

5. The transient voltage suppressor according to claim 1, characterized in that, All the first injection regions (5) and all the second injection regions (6) are connected by different metal interconnects.

6. The transient voltage suppressor according to claim 1, characterized in that, The conductivity type includes P-type and N-type, the first deep well region (2) is a P-type deep well region and the second deep well region (3) is an N-type deep well region; or the first deep well region (2) is an N-type deep well region and the second deep well region (3) is a P-type deep well region.

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