A multi-channel bidirectional electrostatic surge protection circuit suitable for communication chips

Abstract

A kind of multi-channel bidirectional electrostatic surge protection circuit suitable for communication chip.The multi-channel bidirectional electrostatic surge protection circuit includes voltage stabilizing clamping circuit, electrostatic surge main discharge circuit.The present application utilizes four diodes and a voltage stabilizing diode to form a voltage stabilizing clamping circuit, which provides continuous good voltage clamping protection for the electrostatic surge main discharge circuit, to avoid latch-up effect and enhance system reliability;At the same time, the electrostatic surge main discharge circuit provides a large current discharge path to enhance the robustness of the chip and related circuit interface.The present application has the advantages of high system integration, high chip area efficiency, fast chip protection circuit response speed, strong protection port expansion, high electrostatic or surge robustness level and bidirectional electrostatic or surge protection, and can be applied to communication chips and related Type-C and HDMI2.0 interfaces, and can also be used for power supply ports, signal interfaces or plug-in interfaces of electronic devices powered by forward and reverse power supplies with a working voltage of 5V or below.

Description

Technical Field

[0001] This invention belongs to the field of electrostatic discharge (ESD) and surge protection, i.e., electrical overstress (EOS) transient pulse protection for integrated circuits. It relates to an ESD / EOS protection circuit structure, specifically a multi-channel bidirectional electrostatic surge protection circuit suitable for communication chips, which can be used to improve the reliability of different signal interfaces of communication chips with ultra-low voltage, such as Type-C and HDMI 2.0. Background Technology

[0002] Electrostatic discharge (ESD), also known as surge or electrical overstress (EOS), are two transient pulses that are the main causes of equipment failure. As next-generation computers and other high-end electronic devices become smaller, thinner, and more integrated, communication interfaces such as USB, HDMI, and Type-C are experiencing increasingly faster transmission speeds and lower operating voltages, making communication chips increasingly sensitive to noise and related signal interference. Especially during production, transportation, and application, communication chips are inevitably subject to ESD or EOS threats. Enhancing the ESD / EOS protection capabilities of different interfaces within communication chips is a crucial measure to improve chip stability and reliability.

[0003] Furthermore, due to the uncertainty of ESD or EOS discharge direction, it is usually necessary to design circuit protection units with forward and reverse ESD / EOS suppression functions for the corresponding ports of the IC or board-level circuit. With the increasing portability and miniaturization of electronic products, the demand for multi-channel full-chip ESD / EOS protection circuits will continue to grow, especially multi-channel bidirectional ESD / EOS protection circuits with high efficiency, low parasitics, and operating voltage of 5V and below.

[0004] Common basic units for ESD or EOS protection in communication interface circuits include diodes, bipolar junction transistors (BJTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and silicon controlled rectifiers (SCRs). Unidirectional diodes offer advantages such as simple structure, low turn-on voltage, small parasitic capacitance, and fast turn-on speed. However, when diodes are used for ESD or EOS protection at a circuit port, their ESD / EOS protection robustness per unit area is weak, their on-resistance is relatively high, and their ESD / EOS protection efficiency is low. While typical SCR structures offer strong current discharge capability, small parasitic capacitance, and strong robustness for ESD or EOS protection, their trigger voltage is usually too high, exhibiting diode forward conduction characteristics under reverse ESD, making them unsuitable for the bidirectional ESD or EOS protection requirements of fast charging and high-speed data transmission interfaces in communication chips.

[0005] This invention utilizes the forward conduction characteristics of diodes and the voltage clamping characteristics of Zener diodes, along with the design of composite NPN and PNP transistors (BJTs), to construct a novel multi-channel SCR structure for ESD / EOS protection circuitry. This circuit enhances the ESD or EOS protection capabilities of different interfaces on communication chips. The ESD / EOS protection circuit of this invention not only features low-voltage triggering but also enhances ESD or EOS current discharge capability through its embedded SCR structure. Furthermore, this technology allows for flexible expansion of ESD or EOS protection ports based on the number of communication interfaces, enhancing the portability and reusability of the technology while saving design and manufacturing costs. Summary of the Invention

[0006] To address the issues of low area efficiency and numerous parasitic effects in unidirectional ESD / EOS protection solutions, and considering the high-frequency, high-speed operating characteristics of communication chips and the ESD / EOS protection requirements of multi-channel data transmission and conversion circuits at 5V and below in Type-C and HDMI 2.0 interfaces, this invention designs a full-chip multi-channel bidirectional electrostatic surge protection circuit for communication chips and Type-C and HDMI 2.0 interfaces. This invention can reduce the number of integrated circuit process masks, decrease chip area, reduce parasitic effects and manufacturing costs, and improve the reliability of communication chips and their related Type-C and HDMI interfaces.

[0007] The technical solution of this invention: a multi-channel bidirectional electrostatic surge protection circuit suitable for communication chips, including a voltage stabilizing clamping circuit and a surge current discharge circuit;

[0008] The voltage regulation clamping circuit is used to activate the surge current discharge circuit. When a positive electrostatic discharge or surge transient pulse occurs between I / O_1 and GND port, or between I / O_2 and GND port, the first diode D2 or the fourth Zener diode D4 and Zener diode Z in the voltage regulation clamping circuit are activated, thereby activating the surge current discharge circuit and forming a current discharge circuit formed by the first PNP transistor T. p1 Or the second PNP transistor T p2 and the third NPN transistor T n3 The surge current discharge path is formed, and the clamping voltage on the surge current discharge path is equal to the sum of the voltages of the second diode D2 or the fourth diode D4 and the Zener diode Z in the voltage stabilizing clamping circuit, which can avoid the latch-up effect.

[0009] When a forward electrostatic discharge or surge transient pulse occurs at I / O_1 port and I / O_2 port, the second diode D2, the Zener diode Z, and the third diode D3 in the voltage regulation clamping circuit turn on, pushing the surge current discharge path, thereby forming a path for the first PNP transistor T. p1 Second NPN transistor Tn2 This constitutes the main surge current discharge path. The voltage clamping effect of the Zener diode Z can prevent latch-up.

[0010] When negative electrostatic discharge or surge transient pulse occurs at I / O_1 port and I / O_2 port, the fourth diode D4, Zener diode Z, and first diode D1 in the voltage regulation clamping circuit turn on, pushing the surge current discharge path, thereby forming a path for the second PNP transistor T. p2 and the first NPN transistor T n1 This constitutes the main current discharge path for the electrical surge. The voltage clamping function of the Zener diode Z can prevent latch-up.

[0011] The voltage regulation clamping circuit includes a first voltage regulation clamping circuit, a second voltage regulation clamping circuit, a third voltage regulation clamping circuit, and a fourth voltage regulation clamping circuit. The first voltage regulation clamping circuit includes a second diode D2 and a Zener diode Z, with the cathode of the second diode D2 connected to the cathode of the Zener diode Z. The second voltage regulation clamping circuit includes a fourth diode D4 and a Zener diode Z, with the cathode of the fourth diode D4 connected to the cathode of the Zener diode Z. The third voltage regulation clamping circuit includes a second diode D2, a Zener diode Z, and a third diode D3, with the cathode of the second diode D2 connected to the cathode of the Zener diode Z, and the anode of the Zener diode Z connected to the anode of the third diode D3. The fourth voltage regulation clamping circuit includes a fourth diode D4, a Zener diode Z, and a first diode D1, with the cathode of the fourth diode D4 connected to the cathode of the Zener diode Z, and the anode of the Zener diode Z connected to the anode of the first diode D1, used to drive the surge current discharge circuit.

[0012] The surge current discharge circuit includes a first main current discharge path, a second main current discharge path, a third main current discharge path, and a fourth main current discharge path. The first main current discharge path includes the first PNP transistor T. p1 The third NPN transistor T n3 and resistance R psub The first PNP transistor T p1 The emitter of the transistor is connected to the I / O_1 port of the circuit, and the first PNP transistor T... p1 The base of the third NPN transistor T n3 The collector is connected to the resistor R. psub One end is connected to the first PNP transistor T p1 The collector and the third NPN transistor T n3 The base of the resistor R is connected to the resistor R. psub The other end is connected to the third NPN transistor T n3The emitter is connected to the GND port of the circuit to enhance the robustness of the circuit.

[0013] The second main current discharge path includes the second PNP transistor T p2 The third NPN transistor T n3 and resistance R psub The second PNP transistor T p2 The emitter of the second PNP transistor T is connected to the I / O_2 port of the circuit. p2 The base of the third NPN transistor T n3 The collector is connected to the resistor R. psub One end is connected to the second PNP transistor T p2 The collector and the third NPN transistor T n3 The base of the resistor R is connected to the resistor R. psub The other end is connected to the third NPN transistor T n3 The emitter is connected to the GND port of the circuit to enhance the robustness of the circuit.

[0014] The third main current discharge path includes the first PNP transistor T p1 and the second NPN transistor T n2 The first PNP transistor T p1 The emitter of the transistor is connected to the I / O_1 port of the circuit, and the second NPN transistor T... n2 The emitter of the first PNP transistor T is connected to the I / O_2 port of the circuit. p1 The base of the second NPN transistor T n2 The collector of the first PNP transistor T is connected to the collector of the first PNP transistor T. p1 The collector of the second NPN transistor T n2 The base is connected to enhance the robustness of the circuit.

[0015] The fourth main current discharge path includes the second PNP transistor T p2 and the first NPN transistor T n1 The second PNP transistor T p2 The emitter of the transistor is connected to the I / O_2 port of the circuit, and the first NPN transistor T... n1 The emitter of the transistor is connected to the I / O_1 port of the circuit, and the second PNP transistor T... p2 The base of the first NPN transistor T n1 The collector of the second PNP transistor T is connected to the collector of the second PNP transistor T. p2 The collector of the first NPN transistor T n1The base is connected to enhance the robustness of the circuit.

[0016] The beneficial technical effects of this invention are as follows:

[0017] (1) In the embodiment of the present invention, the first voltage regulation clamping circuit composed of the second diode D2 and the Zener diode Z, when a positive electrostatic discharge or surge transient pulse occurs between the I / O_1 port and the GND port, the second diode D2 is forward biased, and the Zener diode Z is used to clamp the port voltage of the circuit of the embodiment of the present invention to avoid latch-up effect; when a negative electrostatic discharge or surge transient pulse occurs between the I / O_1 port and the GND port, the first diode D1 is forward biased to discharge current. The second voltage regulation clamping circuit composed of the fourth diode D4 and the Zener diode Z, when a positive electrostatic discharge or surge transient pulse occurs between the I / O_2 port and the GND port, the fourth diode D4 is forward biased, and the Zener diode Z is used to clamp the port voltage of the circuit of the embodiment of the present invention to avoid latch-up effect; when a negative electrostatic discharge or surge transient pulse occurs between the I / O_2 port and the GND port, the third diode D3 is forward biased to discharge current.

[0018] (2) In the example of the present invention, the third voltage regulation clamping circuit composed of the second diode D2, the Zener diode Z and the third diode D3 is forward biased when a positive electrostatic discharge or surge transient pulse occurs between the I / O_1 port and the I / O_2 port, and the Zener diode Z is used to clamp the port voltage of the circuit of the example of the present invention to avoid latch-up effect; the fourth voltage regulation clamping circuit composed of the fourth diode D4, the Zener diode Z and the first diode D1 is forward biased when a negative electrostatic discharge or surge transient pulse occurs between the I / O_1 port and the I / O_2 port, and the Zener diode Z is used to clamp the port voltage of the circuit of the example of the present invention to avoid latch-up effect.

[0019] (3) In the example of the present invention, the ESD / EOS protection circuit has a full-chip multi-channel protection function. There is a voltage clamping circuit between the I / O_1 terminal, the I / O_2 terminal and the GND terminal to trigger the parasitic SCR main discharge path to open and discharge current. In addition, the number of I / O ports in the full-chip multi-channel bidirectional electrostatic surge protection circuit can be increased to any number as needed. In actual product applications, stress ports can be added to the ESD / EOS protection structure according to the number of low-voltage data transmission ports of the protected chip to achieve the goal of multi-channel bidirectional ESD / EOS protection. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a circuit diagram of a full-chip multi-channel bidirectional electrostatic surge protection circuit in an example of the present invention;

[0022] Figure 2 These are the first and second voltage regulation clamping circuit diagrams of the example circuit of this invention;

[0023] Figure 3 These are the third and fourth voltage regulation clamping circuit diagrams of the example circuit of this invention;

[0024] Figure 4 This is a circuit diagram of the first and second main current discharge paths of the example circuit of the present invention;

[0025] Figure 5 This is a circuit diagram of the third and fourth main current discharge paths in the example circuit of this invention;

[0026] Figure 6 This is a circuit diagram of a full-chip multi-channel bidirectional electrostatic surge protection circuit when the number of I / O ports is flexibly increased to 4 in an example of the present invention; Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] Example 1:

[0029] To address the issues of low area efficiency and significant parasitic effects in unidirectional ESD / EOS protection solutions, and considering the ESD / EOS protection requirements of multi-channel data transmission and conversion circuits in communication chips and their related Type-C and HDMI 2.0 interfaces, this invention designs a full-chip multi-channel bidirectional electrostatic surge protection circuit for communication chips, Type-C, and HDMI 2.0 interfaces. The circuit includes a voltage stabilizing clamping circuit and a surge current discharge circuit, as shown in the circuit diagram below. Figure 1 As shown;

[0030] The voltage regulation clamping circuit includes a first voltage regulation clamping circuit, a second voltage regulation clamping circuit, a third voltage regulation clamping circuit, and a fourth voltage regulation clamping circuit. The first voltage regulation clamping circuit includes a second diode D2 and a Zener diode Z, with the cathode of the second diode D2 connected to the cathode of the Zener diode Z. The second voltage regulation clamping circuit includes a fourth diode D4 and a Zener diode Z, with the cathode of the fourth diode D4 connected to the cathode of the Zener diode Z. The third voltage regulation clamping circuit includes a second diode D2, a Zener diode Z, and a third diode D3, with the cathode of the second diode D2 connected to the cathode of the Zener diode Z, and the anode of the Zener diode Z connected to the anode of the third diode D3. The fourth voltage regulation clamping circuit includes a fourth diode D4, a Zener diode Z, and a first diode D1, with the cathode of the fourth diode D4 connected to the cathode of the Zener diode Z, and the anode of the Zener diode Z connected to the anode of the first diode D1, used to drive the surge current discharge circuit.

[0031] The surge current discharge circuit includes a first main current discharge path, a second main current discharge path, a third main current discharge path, and a fourth main current discharge path. The first main current discharge path includes the first PNP transistor T. p1 The third NPN transistor T n3 and resistance R psub The first PNP transistor T p1 The emitter of the transistor is connected to the I / O_1 port of the circuit, and the first PNP transistor T... p1 The base of the third NPN transistor T n3 The collector is connected to the resistor R. psub One end is connected to the first PNP transistor T p1 The collector and the third NPN transistor T n3 The base of the resistor R is connected to the resistor R. psub The other end is connected to the third NPN transistor T n3 The emitter is connected to the GND port of the circuit to enhance the robustness of the circuit.

[0032] The second main current discharge path includes the second PNP transistor T p2 The third NPN transistor T n3 and resistance R psub The second PNP transistor T p2 The emitter of the second PNP transistor T is connected to the I / O_2 port of the circuit. p2 The base of the third NPN transistor T n3 The collector is connected to the resistor R. psub One end is connected to the second PNP transistor T p2The collector and the third NPN transistor T n3 The base of the resistor R is connected to the resistor R. psub The other end is connected to the third NPN transistor T n3 The emitter is connected to the GND port of the circuit to enhance the robustness of the circuit.

[0033] The third main current discharge path includes the first PNP transistor T p1 and the second NPN transistor T n2 The first PNP transistor T p1 The emitter of the transistor is connected to the I / O_1 port of the circuit, and the second NPN transistor T... n2 The emitter of the first PNP transistor T is connected to the I / O_2 port of the circuit. p1 The base of the second NPN transistor T n2 The collector of the first PNP transistor T is connected to the collector of the first PNP transistor T. p1 The collector of the second NPN transistor T n2 The base is connected to enhance the robustness of the circuit.

[0034] The fourth main current discharge path includes the second PNP transistor T p2 and the first NPN transistor T n1 The second PNP transistor T p2 The emitter of the transistor is connected to the I / O_2 port of the circuit, and the first NPN transistor T... n1 The emitter of the transistor is connected to the I / O_1 port of the circuit, and the second PNP transistor T... p2 The base of the first NPN transistor T n1 The collector of the second PNP transistor T is connected to the collector of the second PNP transistor T. p2 The collector of the first NPN transistor T n1 The base is connected to enhance the robustness of the circuit.

[0035] Example 2:

[0036] The first and second voltage-regulating clamping circuits are used to activate the main current discharge path. When a forward electrostatic discharge or surge transient pulse occurs between the I / O_1 (I / O_2) port and the GND port, the second diode D2 (fourth Zener diode D4) and Zener diode Z in the voltage-regulating clamping circuit open, thereby activating the surge main current discharge circuit, thus forming a current discharge path through the first PNP transistor T. p1 (Second PNP transistor T) p2 ) and the third NPN transistor T n3The main current discharge path is constructed such that the potential on the main current discharge path is equal to the sum of the potentials of the second diode D2 (fourth diode D4) and the Zener diode Z in the voltage regulator clamping circuit, thereby avoiding latch-up effect. Its current path diagram is shown below. Figure 2 As shown.

[0037] Example 3:

[0038] The third voltage-regulating clamping circuit, composed of the second diode D2, the Zener diode Z, and the third diode D3, clamps the port voltage of the circuit in this invention example when a positive electrostatic discharge or surge transient pulse occurs between I / O_1 and I / O_2 ports. The second diode D2 and the third diode D3 are forward biased, and the Zener diode Z is used to clamp the port voltage of the circuit in this invention example to prevent latch-up. The fourth voltage-regulating clamping circuit, composed of the fourth diode D4, the Zener diode Z, and the first diode D1, clamps the port voltage of the circuit in this invention example to prevent latch-up when a negative electrostatic discharge or surge transient pulse occurs between I / O_1 and I / O_2 ports. Its current path diagram is shown below. Figure 3 As shown.

[0039] Example 4:

[0040] The described ESD / EOS protection circuit features full-chip multi-channel protection. A voltage-regulating clamping circuit triggers the parasitic SCR main current discharge path between I / O_1, I / O_2, and GND terminals, discharging the current. Furthermore, the number of I / O ports in this full-chip multi-channel bidirectional electrostatic surge protection circuit can be increased to any number as needed. In practical product applications, stress ports can be added to the ESD / EOS protection structure according to the number of low-voltage data transmission ports of the protected chip, achieving multi-channel bidirectional ESD / EOS protection. The current path is as follows: Figure 4 , Figure 5 , Figure 6 As shown.

Claims

1. A multi-channel bidirectional electrostatic surge protection circuit suitable for communication chips, characterized in that, Includes voltage stabilization clamping circuit and surge current discharge circuit; The voltage regulation clamping circuit includes a first voltage regulation clamping circuit, a second voltage regulation clamping circuit, a third voltage regulation clamping circuit, and a fourth voltage regulation clamping circuit. The first voltage regulation clamping circuit includes a second diode D2 and a Zener diode Z, with the cathode of the second diode D2 connected to the cathode of the Zener diode Z. The second voltage regulation clamping circuit includes a fourth diode D4 and a Zener diode Z, with the cathode of the fourth diode D4 connected to the cathode of the Zener diode Z. The third voltage regulation clamping circuit includes a second diode D2, a Zener diode Z, and a third diode D3, with the cathode of the second diode D2 connected to the cathode of the Zener diode Z and the anode of the Zener diode Z connected to the anode of the third diode D3. The fourth voltage regulation clamping circuit includes a fourth diode D4, a Zener diode Z, and a first diode D1, with the cathode of the fourth diode D4 connected to the cathode of the Zener diode Z and the anode of the Zener diode Z connected to the anode of the first diode D1. These circuits are used to drive the surge current discharge circuit. The surge current discharge circuit includes a first main current discharge path, a second main current discharge path, a third main current discharge path, and a fourth main current discharge path; the first main current discharge path includes a first PNP transistor T. p1 The third NPN transistor T n3 and resistance R psub The first PNP transistor T p1 The emitter of the transistor is connected to the I / O_1 port of the circuit, and the first PNP transistor T... p1 The base of the third NPN transistor T n3 The collector is connected to the resistor R. psub One end is connected to the first PNP transistor T p1 The collector and the third NPN transistor T n3 The base of the resistor R is connected to the resistor R. psub The other end is connected to the third NPN transistor T n3 The emitter is connected to the GND port of the circuit to enhance the robustness of the circuit. The second main current discharge path includes the second PNP transistor T p2 The third NPN transistor T n3 and resistance R psub The second PNP transistor T p2 The emitter of the second PNP transistor T is connected to the I / O_2 port of the circuit. p2 The base of the third NPN transistor T n3 The collector is connected to the resistor R. psub One end is connected to the second PNP transistor T p2 The collector and the third NPN transistor T n3 The base of the resistor R is connected to the resistor R. psub The other end is connected to the third NPN transistor T n3 The emitter is connected to the GND port of the circuit to enhance the robustness of the circuit. The third main current discharge path includes the first PNP transistor T p1 Second NPN transistor T n2 The first PNP transistor T p1 The emitter of the transistor is connected to the I / O_1 port of the circuit, and the second NPN transistor T... n2 The emitter of the first PNP transistor T is connected to the I / O_2 port of the circuit. p1 The base of the second NPN transistor T n2 The collector of the first PNP transistor T is connected to the collector of the first PNP transistor T. p1 The collector of the second NPN transistor T n2 The base is connected to enhance the robustness of the circuit; The fourth main current discharge path includes the second PNP transistor T p2 and the first NPN transistor T n1 The second PNP transistor T p2 The emitter of the transistor is connected to the I / O_2 port of the circuit, and the first NPN transistor T... n1 The emitter of the transistor is connected to the I / O_1 port of the circuit, and the second PNP transistor T... p2 The base of the first NPN transistor T n1 The collector of the second PNP transistor T is connected to the collector of the second PNP transistor T. p2 The collector of the first NPN transistor T n1 The base is connected to enhance the robustness of the circuit.

2. The electrostatic surge protection circuit for multi-channel bidirectional communication chips according to claim 1, characterized in that, The voltage regulation clamping circuit is used to activate the surge current discharge circuit. When a positive electrostatic discharge or surge transient pulse occurs between I / O_1 and GND port, or between I / O_2 and GND port, the first diode D2 or the fourth Zener diode D4 and Zener diode Z in the voltage regulation clamping circuit are activated, thereby activating the surge current discharge circuit and forming a current discharge circuit formed by the first PNP transistor T. p1 Or the second PNP transistor T p2 and the third NPN transistor T n3 The surge current discharge path is formed, and the clamping voltage on the surge current discharge path is equal to the sum of the voltages of the second diode D2 or the fourth diode D4 and the Zener diode Z in the voltage stabilizing clamping circuit, which can avoid the latch-up effect.

3. The electrostatic surge protection circuit for multi-channel bidirectional communication chips according to claim 1, characterized in that, When a forward electrostatic discharge or surge transient pulse occurs at I / O_1 port and I / O_2 port, the second diode D2, the Zener diode Z, and the third diode D3 in the voltage regulation clamping circuit turn on, pushing the surge current discharge path, thereby forming a path for the first PNP transistor T. p1 Second NPN transistor T n2 The surge current discharge path is formed; the voltage clamping effect of the Zener diode Z can be used to avoid latch-up.

4. The electrostatic surge protection circuit for multi-channel bidirectional communication chips according to claim 1, characterized in that, When negative electrostatic discharge or surge transient pulse occurs at I / O_1 port and I / O_2 port, the fourth diode D4, Zener diode Z, and first diode D1 in the voltage regulation clamping circuit turn on, pushing the surge current discharge path, thereby forming a path for the second PNP transistor T. p2 and the first NPN transistor T n1 The surge current discharge path is formed; by utilizing the voltage clamping function of the Zener diode Z, latch-up effect can be avoided.

5. A multi-channel bidirectional electrostatic surge protection circuit for communication chips according to claim 1, characterized in that, The number of I / O ports in the multi-channel bidirectional electrostatic surge protection circuit for communication chips can be set to more than three as required.

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