Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a first device region and a second device region, wherein a groove is formed in the substrate of the second device region, and a first well region is formed in the substrate at the bottom of the groove; forming an isolation layer on the sidewalls of the substrate exposed in the groove; forming a channel layer in the groove, the channel layer covering the sidewalls of the isolation layer, wherein the material stress of the channel layer is greater than the material stress of the substrate; forming a second well region in the substrate of the first device region; patterning the first well region, the channel layer, and the first well region; forming a first fin protruding from the remaining second well region in the first device region; forming a second fin protruding from the remaining first well region in the second device region; the patterned remaining first well region, the second well region, and the substrate serve as a substrate; and removing the isolation layer after forming the first fin, the second fin, and the substrate. This reduces the probability that ions in the second well region will diffuse into the first well region and the channel layer due to stress.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a first device region and a second device region; a first well region located in the substrate of the second device region; a second well region located in the substrate of the first device region, the second well region having a different doping type than the first well region; a first fin protruding from the second well region, the first fin having a first type of doping; a second fin protruding from the first well region, the second fin having a second type of doping; an opening located in the first device region and the second device region, the opening being formed by the sidewall of the first fin and the top of the substrate, the sidewall of the second fin and the top of the substrate, the sidewall of the first fin and the second fin, and the top of the substrate; and an isolation dielectric layer located in the opening, the top surface of the isolation dielectric layer being lower than the top surface of the first fin and the second fin, and the isolation dielectric layer covering the sidewalls of the first fin and the second fin.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region and a second device region, a groove formed in the substrate of the second device region, a first well region formed in the substrate at the bottom of the groove, the first well region exposing a portion of the sidewall of the substrate in the first device region; forming an isolation layer at the junction of the first device region and the second device region on the sidewall of the substrate exposed in the groove; forming a channel layer in the groove, the channel layer covering the sidewall of the isolation layer, the material stress of the channel layer being greater than the material stress of the substrate; forming a second well region in the substrate of the first device region; patterning the channel layer and the second well region, forming a first fin protruding from the remaining second well region in the first device region, forming a second fin protruding from the remaining first well region in the second device region, the patterned remaining first well region, the second well region and the substrate serving as a substrate; and removing the isolation layer after forming the first fin, the second fin and the substrate.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a method for forming a semiconductor structure. At the junction of a first device region and a second device region, an isolation layer is formed on the sidewall of the substrate exposed in the groove. The isolation layer can prevent the channel layer from contacting the second well region. Correspondingly, it reduces the stress generated by the channel layer on the sidewall of the second well region, thereby reducing the probability that ions in the second well region will diffuse into the first well region and the channel layer due to stress. This reduces the risk of leakage between the source and drain doped layers formed in subsequent processes, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0011] Figures 6 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0012] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one semiconductor structure formation method as an example.

[0013] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0014] refer to Figure 1 A substrate 10 is provided, the substrate 10 including a first device region 10A and a second device region 10B. A first mask layer 11 is formed on the top of the substrate of the second device region 10B. Using the first mask layer 11 as a mask, a first ion implantation process is performed on the substrate 10 in the first device region 10A to transform the substrate after the first ion implantation process into a first well region 12.

[0015] Specifically, the first device region 10A is used to form an NMOS transistor, and the second device region 10B is used to form a PMOS transistor.

[0016] After forming the first well region 12, the process further includes: removing the first mask layer 11.

[0017] refer to Figure 2 A second mask layer 16 is formed on top of the first well region 12 in the first device region 10A. Using the second mask layer 16 as a mask, a second ion implantation process is performed on the substrate 10 in the second device region 10B to transform the substrate 10 after the second ion implantation process into the second well region 13.

[0018] refer to Figure 3 Using the second mask layer 16 as a mask, a portion of the thickness of the second well region 13 is etched to form a groove 60 that exposes a portion of the sidewall of the first well region 12.

[0019] Specifically, after forming the groove 60, the process further includes removing the second mask layer 16.

[0020] refer to Figure 4The groove 60 is filled with a channel layer 20, which covers part of the sidewall of the first well region 12 exposed in the groove 60, and the material stress of the channel layer 20 is greater than the material stress of the substrate 10.

[0021] Research has revealed that after the channel layer 20 is formed in the second device region 10B, the sidewalls of the channel layer 20 are in direct contact with the sidewalls of the first well region 12, and the material stress of the channel layer 20 is greater than that of the substrate 10. Consequently, the channel layer 20 tends to exert stress on the sidewalls of the first well region 12. This significantly increases the probability that ions in the first well region 12 will diffuse into the channel layer 20 and the second well region 13 due to the stress. Consequently, the probability of leakage between the source and drain doped layers formed in subsequent processes is also greatly increased, which in turn affects the performance of the semiconductor structure.

[0022] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region and a second device region, a groove formed in the substrate of the second device region, a first well region formed in the substrate at the bottom of the groove, the first well region exposing a portion of the sidewall of the substrate in the first device region; forming an isolation layer at the junction of the first device region and the second device region on the sidewall of the substrate exposed by the groove; forming a channel layer in the groove, the channel layer covering the sidewall of the isolation layer, the material stress of the channel layer being greater than the material stress of the substrate; forming a second well region in the substrate of the first device region; patterning the channel layer and the second well region, forming a first fin protruding from the remaining second well region in the first device region, and forming a second fin protruding from the remaining first well region in the second device region, the patterned remaining first well region, the second well region, and the substrate serving as a substrate; and removing the isolation layer after forming the first fin, the second fin, and the substrate.

[0023] In the embodiment of the present invention, an isolation layer is formed on the sidewall of the substrate exposed in the groove at the junction of the first device region and the second device region. The isolation layer can prevent the channel layer from contacting the second well region. Correspondingly, it reduces the stress generated by the channel layer on the sidewall of the second well region, thereby reducing the probability that ions in the second well region will diffuse into the first well region and the channel layer due to stress. This reduces the risk of leakage between the source and drain doped layers formed in subsequent processes, thereby improving the performance of the semiconductor structure.

[0024] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0026] The semiconductor structure includes: a substrate 218, the substrate 218 including a first device region 200A and a second device region 200B; a first well region 209 located in the substrate 218 of the second device region 200B; a second well region 217 located in the substrate 218 of the first device region 200A, the second well region 217 having a different doping type than the first well region 209; a first fin 221 protruding from the second well region 217, the first fin 221 having a first type of doping; and a second fin 220 protruding from the first well region 209, the second fin 220 having a second type of doping. An opening 260 is located in the first device region 200A and the second device region 200B. The opening 260 is formed by the sidewall of the first fin 221 and the top of the substrate 218, the sidewall of the second fin 220 and the top of the substrate 218, the sidewalls of the first fin 221 and the second fin 220, and the top of the substrate 218. An isolation dielectric layer 212 is located in the opening 260. The top surface of the isolation dielectric layer 212 is lower than the top surface of the first fin 221 and the second fin 220, and the isolation dielectric layer 212 covers the sidewalls of the first fin 221 and the second fin 220.

[0027] The substrate 218 provides the basis for the process operation of forming the semiconductor structure.

[0028] The semiconductor structure includes the fin field-effect transistor.

[0029] In this embodiment, the substrate 218 is made of silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0030] In this embodiment, the substrate 218 further includes a base 200 located at the bottom of the first well region 209 and the second well region 217.

[0031] In this embodiment, the first device region 200A is an NMOS region, and the second device region 200B is a PMOS region.

[0032] Specifically, the NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor.

[0033] In this embodiment, the channel materials of the first device region 200A and the second device region 200B are different. By using different channel materials, the respective performance requirements of the NMOS transistor and the PMOS transistor are met. In other embodiments, the NMOS transistor and the PMOS transistor may use the same channel material.

[0034] In this embodiment, the doped ions in the first well region 209 are N-type ions.

[0035] The first well region 209 is used to provide the P-type substrate required for the operation of the PMOS transistor.

[0036] Specifically, the first well region 209 contains well region ions, and the conductivity type of the well region ions is opposite to that of the channel conductivity type of the PMOS transistor. That is, the well region ions corresponding to the PMOS transistor are N-type ions.

[0037] In this embodiment, the N-type ion includes one or more of boron ions, phosphorus ions, and arsenic ions.

[0038] The second well region 217 is used to provide the N-type substrate required for the operation of the NMOS transistor.

[0039] Specifically, the second well region 217 contains well region ions, the conductivity type of which is opposite to that of the channel conductivity type of the NMOS transistor. That is, the well region ions corresponding to the NMOS transistor are P-type ions.

[0040] In this embodiment, the P-type ions include B ions, Ga ions, or In ions.

[0041] In this embodiment, the first fin 221 is used to provide a conductive channel for the fin field-effect transistor.

[0042] In this embodiment, the first fin 221 and the second well region 217 are an integral structure, and therefore, the material of the first fin 221 is silicon.

[0043] In this embodiment, the first fin 221 has a first type of doping, which is an N-type ion.

[0044] In this embodiment, the tops of the first fin 221 and the second fin 220 are flush.

[0045] Specifically, the tops of the first fin 221 and the second fin 220 are flush, resulting in a high degree of flatness at the top of the first fin 221 and the top of the second fin 220. This provides a good process foundation for the formation of the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0046] The second fin 220 is used to provide a conductive channel for the fin field-effect transistor.

[0047] In this embodiment, the second fin 220 has a second type of doping, which is a P-type ion.

[0048] In this embodiment, the material of the second fin 220 is one or more of phosphorus-doped silicon germanide, boron-doped silicon germanide, and arsenic-doped silicon germanide.

[0049] Specifically, the NMOS transistor in the first device region 200A and the PMOS transistor in the second device region 200B have different channel materials. Therefore, in this embodiment, the channel material of the NMOS transistor is silicon, and the channel material of the PMOS transistor (i.e., the second fin 220) is silicon germanide. By using silicon germanide for the PMOS transistor, the channel mobility of the PMOS transistor is improved. At the same time, it helps to improve the negative bias temperature instability (NBTI) problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.

[0050] By performing N-type ion doping on the second fin 220, the N-type ion concentration in the second fin 220 meets the process requirements, thereby reducing the impact of related processes (e.g., annealing process) on the carrier mobility of the second fin 220 during the semiconductor structure formation step.

[0051] The opening 260 provides space for the isolation medium layer 212.

[0052] The isolation dielectric layer 212 serves to isolate adjacent device regions.

[0053] The material of the isolation dielectric layer 212 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0054] Silicon nitride, silicon oxide, and silicon oxynitride are all insulating materials. As an example, the material of the insulating dielectric layer 212 is silicon oxide.

[0055] The top surface of the isolation dielectric layer 212 is lower than the top surfaces of the first fin 221 and the second fin 220, providing space for the formation of other device structures in the first device region 200A and the second device region 200B.

[0056] Figures 6 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0057] refer to Figures 6 to 8 A substrate 100 is provided, the substrate 100 including a first device region 100A and a second device region 100B, a groove 110 is formed in the substrate of the second device region 100B, a first well region 109 is formed in the substrate 100 at the bottom of the groove 110, and the first well region 109 exposes a portion of the sidewall of the substrate 100 in the first device region 100A.

[0058] The substrate 100 provides the basis for the process operation of forming the semiconductor structure.

[0059] The semiconductor structure includes the fin field-effect transistor.

[0060] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0061] In this embodiment, the first device region 100A is an NMOS region, the second device region 100B is a PMOS region, and the doped ions in the first well region 109 are N-type ions.

[0062] Specifically, the NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor.

[0063] In this embodiment, the channel materials of the first device region 100A and the second device region 100B are different. By using different channel materials, the respective performance requirements of the NMOS transistor and the PMOS transistor are met. In other embodiments, the NMOS transistor and the PMOS transistor may use the same channel material.

[0064] In this embodiment, a first well region 109 is formed in the substrate of the second device region 100B. The first well region 109 is used to provide a P-type substrate required for the operation of the PMOS transistor.

[0065] Specifically, the first well region 109 contains well region ions, and the conductivity type of the well region ions is opposite to that of the channel conductivity type of the PMOS transistor. That is, the well region ions corresponding to the PMOS transistor are N-type ions.

[0066] In this embodiment, the N-type ion includes one or more of boron ions, phosphorus ions, and arsenic ions.

[0067] In this embodiment, after forming a first well region 109 in the substrate 100 of the second device region 100B, a portion of the thickness of the substrate 100 corresponding to the first well region 109 is removed, and the groove 110 is formed in the substrate 100.

[0068] In order to selectively form the first well region 109 in the substrate 100 of the second device region 100B, a mask layer is required to protect the first device region 100A. Accordingly, when forming the first well region 109, the top surface of the substrate 100 is a flat surface, which helps to reduce the process difficulty of forming a mask layer on the top of the substrate of the first device region 100A.

[0069] Furthermore, when the first well region 109 is formed, the groove 110 has not yet been formed. Accordingly, the sidewalls of the first well region 109 and the top of the remaining first well region 109 that needs to be retained after the groove 110 is formed are not exposed. This reduces the process of forming a mask layer on the top of the substrate 100 of the first device region 100A, and reduces damage to the sidewalls of the first well region 109 and the top of the remaining first well region 109 that needs to be retained after the groove 110 is formed. This is beneficial to improving the formation quality of the subsequent channel layer.

[0070] In this embodiment, the step of forming the first well region 109 in the substrate 100 of the second device region 100B includes: as follows Figure 6 As shown, a first mask layer 108 is formed on top of the substrate 100 of the first device region 100A; as Figure 7 As shown, using the first mask layer 108 as a mask, the substrate 100 in the second device region 100B is subjected to a first ion implantation process, transforming the substrate 100 after the first ion implantation process into a first well region 109.

[0071] Specifically, the first ion implantation process is a process that accelerates ions to a certain high energy level and implants them into the surface layer of a solid material to change the physical and chemical properties of the surface layer. This process has the characteristics of high efficiency and strong modified layer, thereby transforming the substrate 100 after the first ion implantation process into the first well region 109.

[0072] In this embodiment, the first mask layer 108 includes a first organic material layer 103, a first anti-reflective coating 102 located on the first organic material layer 103, and a first photoresist layer 101 located on the first anti-reflective coating 102.

[0073] The first organic material layer 103 is made of organic materials. In this embodiment, the organic material layer 103 is made of spin-on carbon (SOC). In other embodiments, the organic material layer may also be made of other organic materials, such as one or more of the following: ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), and APF (Advanced Patterning Film).

[0074] The material of the first anti-reflective coating 102 includes a BARC (bottom anti-reflective coating) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

[0075] Specifically, during the formation of the first mask layer 108, the first photoresist layer 101 is used as a mask to sequentially etch the first anti-reflective coating 102 and the first organic material layer 103, thereby forming the first mask layer 108 on the top of the substrate of the first device region 100A and exposing the second device region 100B.

[0076] It should be noted that during the formation of the first mask layer 108, the first photoresist layer 101 is used as a mask to sequentially etch the first anti-reflective coating 102 and the first organic material layer 103.

[0077] It should also be noted that in other embodiments, the first mask layer may also be made of a dielectric material. For example, the dielectric material may include one or both of silicon oxide and silicon nitride.

[0078] Furthermore, in this embodiment, the formation method is used to form a fin field-effect transistor (FinFET), meaning that a first fin and a second fin will be formed subsequently. As the critical dimensions of the device continue to decrease, the linewidth of the fins becomes increasingly smaller. If well region ion implantation is performed on the first and second fins after their formation to form well regions, it is easy to damage the first and second fins. Therefore, in this embodiment, the well regions are formed before the first and second fins are formed, thereby avoiding damage to the fins caused by the formation processes of the first and second well regions.

[0079] refer to Figure 8After forming a first well region 109 in the substrate 100 of the second device region 100B, a portion of the thickness of the substrate 100 corresponding to the first well region 109 is removed, and the groove 110 is formed in the substrate 100.

[0080] The groove 110 provides space for the subsequent formation of the channel layer.

[0081] In this embodiment, the process for forming the groove 110 includes a dry etching process.

[0082] The dry etching process is an anisotropic etching process, which helps to reduce damage to the sidewalls of the substrate 100 in the first device region 100A. At the same time, the dry etching process can better control the process parameters, so that the thickness of the substrate 100 corresponding to the removal of the first well region 109 can be controlled more precisely.

[0083] Specifically, using the first mask layer 108 as a mask, a portion of the thickness of the first well region 109 corresponding to the substrate 100 is etched to form a groove 110 in the substrate 100.

[0084] It should be noted that during the process of etching the substrate 100 corresponding to the first well region 109 of a certain thickness using the first mask layer 108 as a mask, the first photoresist layer will be consumed. Therefore, the first mask layer 108 includes only the first anti-reflective coating 102 and the first organic material layer 103.

[0085] It should be noted that the distance from the bottom of the groove 110 to the top of the substrate 100 in the first device region 100A should not be too large or too small. If the distance is too large, it can easily lead to excessively large heights of the subsequently formed first and second fins, resulting in a large depth-to-width ratio between adjacent fins. This increases the difficulty of filling the sidewalls of the first and second fins with film, and also makes it more difficult to remove the isolation layer due to the smaller process window, thus affecting the performance of the semiconductor structure. If the distance is too small, the heights of the subsequently formed first and second fins may not meet the process requirements, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the distance from the bottom of the groove 110 to the top of the substrate 100 in the first device region 100A is 40 nanometers to 70 nanometers.

[0086] refer to Figures 9 to 10An isolation layer 112 is formed on the sidewall of the substrate 100 exposed in the groove 110 at the junction of the first device region 100A and the second device region 100B.

[0087] It should be noted that at the junction of the first device region 100A and the second device region 100B, an isolation layer 112 is formed on the sidewall of the substrate 100 exposed in the groove 110. The isolation layer 112 can prevent the contact between the subsequently formed channel layer and the second well region. Correspondingly, it reduces the stress generated by the channel layer on the sidewall of the second well region, thereby reducing the probability that ions in the second well region will diffuse into the first well region 109 and the channel layer due to stress. This reduces the risk of leakage between the source and drain doped layers formed in subsequent processes, thereby improving the performance of the semiconductor structure.

[0088] In this embodiment, the step of forming an isolation layer 112 on the sidewall of the substrate 100 exposed in the groove 110 includes: as follows Figure 9 As shown, a barrier material layer 111 is formed on the top of the substrate 100 in the first device region 100A, and on the bottom and sidewalls of the groove 110; as Figure 10 As shown, the barrier material layer 111 at the top of the substrate 100 and the bottom of the groove 110 of the first device region 100A is removed, and the remaining barrier material layer 111 serves as the isolation layer 112.

[0089] In this embodiment, the process for forming the isolation layer 112 includes atomic layer deposition.

[0090] The atomic layer deposition process includes multiple atomic layer deposition cycles, which helps to improve the thickness uniformity of the isolation layer 112 and allows the isolation layer 112 to cover the sidewalls of the substrate 100 exposed in the groove 110. In other embodiments, the isolation layer can also be formed using chemical vapor deposition (CVD).

[0091] It should be noted that, in the direction perpendicular to the sidewall of the groove 110, the lateral dimension of the isolation layer 112 should not be too large or too small. If the lateral dimension of the isolation layer 112 is too large, it will easily occupy too much space in the subsequently formed channel layer, thereby occupying the formation area of ​​the subsequently formed second fin. At the same time, during the subsequent removal of the isolation layer 112, the close proximity of the isolation layer 112 to the adjacent first and second fins increases the difficulty of removing the isolation layer 112 and increases the risk of damage to the first and second fins. Therefore, in this embodiment, in the direction perpendicular to the sidewall of the groove 110, the lateral dimension of the isolation layer 112 is 2 nanometers to 10 nanometers.

[0092] The material of the isolation layer 112 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0093] Silicon nitride, silicon oxide, and silicon oxynitride are all insulating materials with a strong ability to block ion diffusion, thereby preventing ions in the second well region from diffusing into the first well region 109 and the channel layer. At the same time, silicon nitride, silicon oxide, and silicon oxynitride materials have a high etching selectivity with the subsequently formed first and second fins, which is beneficial for the subsequent removal of the isolation layer 112.

[0094] refer to Figure 11 A channel layer 113 is formed in the groove 110, the channel layer 113 covers the sidewall of the isolation layer 112, and the material stress of the channel layer 113 is greater than the material stress of the substrate 100.

[0095] The channel layer 113 provides a process basis for the subsequent formation of the second fin in the second device region 100B.

[0096] In this embodiment, the channel layer 113 is formed using an epitaxial process.

[0097] The epitaxial growth process can better control the process parameters, has high process controllability, and is easy to obtain a more accurate thickness of the channel layer 113. Moreover, the epitaxial growth process is easy to form a film layer with fewer impurities, resulting in a higher formation quality of the channel layer 113.

[0098] In this embodiment, the material of the channel layer 113 is one or more of phosphorus-doped silicon germanide, boron-doped silicon germanide, and arsenic-doped silicon germanide.

[0099] Specifically, the NMOS transistor in the first device region 100A and the PMOS transistor in the second device region 100B use different channel materials. Therefore, in this embodiment, the channel material of the NMOS transistor is silicon, and the channel material of the PMOS transistor (i.e., the channel layer 113) is silicon germanide. By using silicon germanide for the PMOS transistor, the channel mobility of the PMOS transistor is improved. Simultaneously, this helps to improve the negative bias temperature instability (NBTI) problem of the PMOS transistor, thereby improving the performance of the PMOS transistor.

[0100] It should be noted that after the channel layer 113 is formed in the groove 110, the channel layer 113 is subjected to N-type ion doping treatment so that the N-type ion concentration in the subsequently formed second fin meets the process requirements. In the subsequent semiconductor structure formation steps, the influence of related processes (e.g., annealing process) on the carrier mobility of the second fin is reduced.

[0101] refer to Figures 12 to 13 A second well region 117 is formed in the substrate 100 of the first device region 100A.

[0102] The second well region 117 is used to provide the N-type substrate required for the operation of the NMOS transistor.

[0103] Specifically, the second well region 117 contains well region ions, the conductivity type of which is opposite to that of the channel conductivity type of the NMOS transistor. That is, the well region ions corresponding to the NMOS transistor are P-type ions.

[0104] In this embodiment, the P-type ions include B ions, Ga ions, or In ions.

[0105] In this embodiment, after the channel layer 113 is formed, a second well region 117 is formed in the substrate 100 of the first device region 100A.

[0106] Compared to the approach of forming the second well region first and then the channel layer, in this embodiment, during the formation of the second well region 117, since an isolation layer 112 is formed at the junction of the first device region 100A and the second device region 100B, the second well region 117 can still be formed in the first device region 100A even if the second mask layer is not formed on top of the isolation layer 112 during the subsequent formation of the second mask layer in the second device region 100B. Accordingly, the process requirements for forming the second mask layer in the second device region 100B are lower.

[0107] In other embodiments, the second well region may be formed before the trench layer is formed. For example, the second well region may be formed before the groove is formed.

[0108] In this embodiment, the step of forming a second well region 117 in the substrate 100 of the first device region 100A includes: forming a second mask layer 116 on top of the channel layer 113 in the second device region 100B; using the second mask layer 116 as a mask, performing a second ion implantation process on the substrate 100 in the first device region 100A, and transforming the substrate 100 after the second ion implantation process into the second well region 117.

[0109] Specifically, the second ion implantation process accelerates ions to a certain high energy level and implants them into the surface layer of a solid material to change the physical and chemical properties of the surface layer. This process has the characteristics of high efficiency and strong modified layer, thereby transforming the substrate 100 after the second ion implantation process into the second well region 117.

[0110] The second mask layer 116 is described as described above as the first mask layer 108, and will not be repeated here.

[0111] It should be noted that after forming the second well region 117 in the substrate 100 of the first device region 100A, the method further includes: removing the second mask layer 116.

[0112] Specifically, the second mask layer 116 is removed to provide a process basis for the subsequent formation of the first fin and the second fin in the first device region 100A and the second device region 100B, respectively.

[0113] Continue to refer to Figure 12 After forming the channel layer 113 on top of the first well region 109 and before forming the second well region 117 in the substrate 100 of the first device region 100A, the method further includes: using the top of the substrate 100 in the first device region 100A as a stop position, planarizing the isolation layer 112 and the channel layer 113 that are higher than the substrate 100, and the top of the remaining isolation layer 112 and the channel layer 113 being flush with the top of the substrate 100.

[0114] Specifically, the isolation layer 112 and the channel layer 113 above the substrate 100 are planarized, so that the top of the channel layer 113 and the top of the second well region 117 have a high degree of flatness, thereby making the height of the subsequently formed first fin and second fin consistent, thereby improving the performance of the semiconductor structure.

[0115] It should be noted that after the trench layer 113 is formed on the top of the first well region 109 and before the second well region 117 is formed in the substrate 100 of the first device region 100A, the process further includes: removing the first mask layer 108.

[0116] The first mask layer 108 is removed to expose the substrate 100 of the first device region 100A, thereby preparing for the formation of a second well region 117 in the substrate 100 of the first device region 100A.

[0117] Specifically, during the planarization of the isolation layer 112 and the channel layer 113 above the substrate 100, the first mask layer 108 on top of the substrate 100 in the first device region 100A is removed.

[0118] In this embodiment, the process of planarizing the isolation layer 112 and the channel layer 113 above the substrate 100 includes a chemical mechanical polishing process.

[0119] refer to Figure 14 The channel layer 113 and the second well region 117 are patterned, and a first fin 121 protruding from the remaining second well region 117 is formed in the first device region 100A, and a second fin 120 protruding from the remaining first well region 109 is formed in the second device region 100B. The patterned remaining first well region 109, second well region 117 and substrate 100 serve as substrate 118.

[0120] The first fin 121 and the second fin 120 are used to provide conductive channels for fin field-effect transistors.

[0121] In this embodiment, since the first fin 121 and the second well region 117 are an integral structure, the material of the first fin 121 is silicon.

[0122] In this embodiment, the steps of forming a first fin 121 in the first device region 100A and a second fin 120 in the second device region 100B include: forming a fin mask layer (not shown) on top of the channel layer 113 and the second well region 117; etching the first well region 109 and the channel layer 113 using the fin mask layer as a mask; the remaining unetched first well region 109, second well region 117, and substrate 100 serve as a substrate 118; the second well region 117 protruding from the substrate 118 in the first device region 100A serves as the first fin 121; and the channel layer 113 protruding from the substrate 118 in the second device region 100B serves as the second fin 120.

[0123] Specifically, patterning the channel layer 113 and the second well region 117 with the fin mask layer helps to improve the accuracy of pattern transfer and form the first fin 121 and the second fin 120 with higher dimensional accuracy.

[0124] In this embodiment, the process of forming the first fin 121 in the first device region 100A and the second fin 120 in the second device region 100B includes a dry etching process.

[0125] The dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its transverse etching rate. While completing accurate pattern transformation, it ensures the morphological quality of the sidewalls of the first fin 121 and the second fin 120.

[0126] refer to Figure 15After forming the first fin 121 and the second fin 120, as well as the substrate 118, the isolation layer 112 is removed.

[0127] Specifically, removing the isolation layer 112 provides a process basis for the subsequent formation of an isolation layer on top of the substrate 118. At the same time, it also increases the process window between adjacent first fin 121 and second fin 120, reducing the filling difficulty of each film layer formed between the first fin 121 and second fin 120.

[0128] In this embodiment, the process for removing the isolation layer 112 includes a dry etching process.

[0129] In this embodiment, during the removal of the isolation layer 112, the etching process also etches a portion of the thickness of the first well region 109 and the second well region 117, so that the total height of the first fin 121 and the second fin 120 meets the process requirements, providing space for the subsequent formation of the isolation layer on the top of the substrate 118, and ensuring that the effective height of the first fin 121 and the second fin 120 meets the process requirements, thereby satisfying the requirements for carrier mobility.

[0130] Moreover, this embodiment utilizes the step of removing the isolation layer 112 to simultaneously adjust the total height of the first fin 121 and the second fin 120, which helps to save process time.

[0131] The dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its transverse etching rate. While removing the isolation layer 112, it ensures the morphological quality of the sidewalls of the first fin 121 and the second fin 120.

[0132] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first device region and a second device region, a groove is formed in the substrate of the second device region, a first well region is formed in the substrate at the bottom of the groove, and the first well region exposes a portion of the sidewall of the substrate in the first device region; An isolation layer is formed on the sidewall of the substrate exposed in the groove at the junction of the first device region and the second device region. A channel layer is formed in the groove, the channel layer covers the sidewall of the isolation layer, the material stress of the channel layer is greater than the material stress of the substrate, and the isolation layer is used to block the stress generated by the channel layer on the sidewall of the second well region formed in the substrate; After the channel layer is formed, a second well region is formed in the substrate of the first device region; The channel layer and the second well region are patterned, a first fin is formed in the first device region that protrudes from the remaining second well region, a second fin is formed in the second device region that protrudes from the remaining first well region, and the bottom of the second fin is in contact with the top of the first well region. The patterned remaining first well region, second well region and substrate are used as a substrate. After forming the first fin, the second fin, and the substrate, the isolation layer is removed.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming an isolation layer on the sidewall of the substrate exposed in the groove includes: forming a barrier material layer on the top of the substrate in the first device region, and on the bottom and sidewall of the groove; removing the barrier material layer on the top of the substrate in the first device region and the bottom of the groove, with the remaining barrier material layer serving as the isolation layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, after forming a first well region in the substrate of the second device region, a portion of the thickness of the substrate corresponding to the first well region is removed, and the groove is formed in the substrate.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the first device region is an NMOS region, the second device region is a PMOS region, and the doped ions in the first well region are N-type ions; In the step of forming a second well region in the substrate of the first device region, the dopant ions in the second well region are P-type ions.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The step of forming a first well region in the substrate of the second device region includes: forming a first mask layer on top of the substrate of the first device region; using the first mask layer as a mask, performing a first ion implantation process on the substrate in the second device region to transform the substrate after the first ion implantation process into a first well region; After forming a trench layer on top of the first well region and before forming a second well region in the substrate of the first device region, the method further includes: removing the first mask layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a second well region in the substrate of the first device region includes: forming a second mask layer on top of the channel layer in the second device region; using the second mask layer as a mask, performing a second ion implantation process on the substrate in the first device region to transform the substrate after the second ion implantation process into a second well region; and removing the second mask layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming a channel layer on top of the first well region and before forming a second well region in the substrate of the first device region, the method further includes: using the top of the substrate in the first device region as a stop position, planarizing the isolation layer and channel layer above the substrate, with the top of the remaining isolation layer and channel layer flush with the top of the substrate.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the isolation layer includes a dry etching process.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of removing the isolation layer further includes removing a portion of the substrate.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The direction perpendicular to the sidewall of the groove is transverse, and the transverse dimension of the isolation layer is 2 nanometers to 10 nanometers.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The distance from the bottom of the groove to the top of the substrate in the first device region is 40 nanometers to 70 nanometers.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The channel layer material includes one or more of phosphorus-doped silicon germanide, boron-doped silicon germanide, and arsenic-doped silicon germanide.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the isolation layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

14. A semiconductor structure formed using the formation method according to any one of claims 1 to 13, characterized in that, include: A substrate, the substrate comprising a first device region and a second device region; The first well region is located in the substrate of the second device region; A second well region is located in the substrate of the first device region, and the second well region has a different doping type than the first well region; A first fin protrudes from the second well region, and the first fin has a first type of doping. The second fin protrudes from the first well region, the second fin has a second type of doping, and the bottom of the second fin is in contact with the top of the first well region; An opening is located in the first device area and the second device area. The opening is formed by the sidewall of the first fin and the top of the substrate, the sidewall of the second fin and the top of the substrate, the sidewall of the first fin and the second fin, and the top of the substrate. An isolation medium layer is located in the opening, the top surface of the isolation medium layer is lower than the top surface of the first fin and the second fin, and the isolation medium layer covers the sidewalls of the first fin and the second fin.

15. The semiconductor structure as described in claim 14, characterized in that, The first device region is an NMOS region, and the second device region is a PMOS region; The first well region is doped with N-type ions, and the second well region is doped with P-type ions.

16. The semiconductor structure as claimed in claim 14, characterized in that, The first type of doping is N-type ions; the second type of doping is P-type ions.

17. The semiconductor structure as claimed in claim 14, characterized in that, The material of the isolation dielectric layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

18. The semiconductor structure as described in claim 14, characterized in that, The material of the second fin includes one or more of phosphorus-doped silicon germanide, boron-doped silicon germanide, and arsenic-doped silicon germanide.

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