Semiconductor device and manufacturing method thereof

Abstract

The present invention relates to the field of semiconductor technology, and discloses a semiconductor device and a method for manufacturing the same. The semiconductor device includes a source structure, a gate structure, a first opening, a semiconductor structure, a gate dielectric layer, an insulating structure, and a gap. The gate structure is arranged above the source structure. The first opening passes through the gate structure in the vertical direction. The semiconductor structure is partially arranged in the first opening, and at least a portion of the gate structure is located on two opposite sides of the semiconductor structure in the horizontal direction. The gate dielectric layer is arranged in the first opening and is located between the semiconductor structure and the gate structure. At least a portion of the insulating structure is arranged in the first opening, at least a portion of the semiconductor structure is located between the insulating structure and the gate dielectric layer, and the gap is located in the insulating structure. In this way, the effect of improving the operating performance of the semiconductor device can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Semiconductor integrated circuit technology continues to advance over time, with each new generation of manufacturing processes featuring smaller and more complex circuit designs than the previous generation. The number and density of functional components on each chip area must continue to increase due to product innovation, which naturally requires the geometric dimensions of each component to become smaller and smaller.

[0003] Since the traditional planar metal-oxide-semiconductor (MOS) transistor manufacturing process is difficult to continue to shrink, how to improve the traditional planar transistor elements so as to reduce the geometric size of the transistor elements and / or improve the operating performance of the transistor elements has become a technical problem that needs to be solved urgently. Summary of the Invention

[0004] Therefore, the present invention provides a semiconductor device, aiming to form a gap in an insulating structure surrounding a semiconductor, so as to improve the operating performance of the semiconductor device.

[0005] The above-mentioned invention objectives are mainly achieved through the following technical solutions:

[0006] In a first aspect, a semiconductor device is provided, comprising:

[0007] A source structure, a gate structure, a first opening, a semiconductor structure, a gate dielectric layer, an insulating structure and a gap; the gate structure is arranged above the source structure; the first opening passes through the gate structure in the vertical direction; the semiconductor structure is partially arranged in the first opening, and at least a portion of the gate structure is located on two opposite sides of the semiconductor structure in the horizontal direction; the gate dielectric layer is arranged in the first opening, and the gate dielectric layer is located between the semiconductor structure and the gate structure; at least a portion of the edge structure is arranged in the first opening, at least a portion of the semiconductor structure is located between the insulating structure and the gate dielectric layer, and the gap is located in the insulating structure; wherein the vertical direction is the z-axis direction of the spatial rectangular coordinate system, and the horizontal direction is the x-axis or y-axis direction of the spatial rectangular coordinate system.

[0008] In a second aspect, a method for manufacturing a semiconductor device is provided, comprising the following steps:

[0009] A gate structure is formed above the source structure; a first opening is formed in a vertical direction and passes through the gate structure, wherein the vertical direction is the z-axis direction of a spatial rectangular coordinate system; a gate dielectric layer is formed in the first opening; an insulating structure is formed, wherein at least a portion of the insulating structure is formed in the first opening, and a gap is formed in the insulating structure; a semiconductor structure is formed, wherein a portion of the semiconductor structure is located in the first opening; at least a portion of the gate structure is located on two opposite sides of the semiconductor structure in a horizontal direction, the gate dielectric layer is located between the semiconductor structure and the gate structure, and at least a portion of the semiconductor structure is located between the insulating structure and the gate dielectric layer, wherein the horizontal direction is the x-axis or y-axis direction of a spatial rectangular coordinate system.

[0010] Compared with the prior art, the present invention has the following beneficial effects: through the structural improvement of a semiconductor device, the insulating structure can indirectly control the composition of the semiconductor structure and support the semiconductor structure, and the gaps in the insulating structure can be used to reduce the overall dielectric constant of the insulating structure, thereby improving the operating performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0012] Figure 2 is a partial top view schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0013] Figure 3 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0014] Figure 4 In a method for manufacturing a semiconductor device according to an embodiment of the present invention, Figure 3 Schematic diagram of the situation afterwards;

[0015] Figure 5 In a method for manufacturing a semiconductor device according to an embodiment of the present invention, Figure 4 Schematic diagram of the situation afterwards;

[0016] Figure 6 In a method for manufacturing a semiconductor device according to an embodiment of the present invention, Figure 5 Schematic diagram of the situation afterwards;

[0017] Figure 7 In a method for manufacturing a semiconductor device according to an embodiment of the present invention, Figure 6 Schematic diagram of the situation afterwards;

[0018] Figure 8 In a method for manufacturing a semiconductor device according to an embodiment of the present invention, Figure 7 Schematic diagram of the situation afterwards;

[0019] Figure 9 In a method for manufacturing a semiconductor device according to an embodiment of the present invention, Figure 8 Schematic diagram of the situation afterwards;

[0020] Figure 10 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0021] Figure 11 is a schematic cross-sectional view of another semiconductor device according to an embodiment of the present invention;

[0022] Figure 12 is a schematic cross-sectional view of another semiconductor device according to an embodiment of the present invention;

[0023] Figure 13 is a schematic cross-sectional view of another semiconductor device according to an embodiment of the present invention;

[0024] The description of the accompanying drawings is as follows:

[0025] 10-dielectric layer; 10B-lower surface; 10T-upper surface; 12-barrier layer; 14-conductive layer; 16-barrier layer; 18-bottom semiconductor layer; 20-dielectric layer; 22-barrier layer; 24-conductive layer; 26-dielectric layer; 28-gate dielectric layer; 28A-first portion; 28B-second portion; 30-first semiconductor layer; 32-second semiconductor layer; 34-insulating material; 34P-insulating structure; 34T-upper surface; 34V-gap; 36-third Semiconductor layer; 36V-gap; 38-dielectric layer; 40-barrier layer; 42-conductive layer; 90-etch-back process; 101-semiconductor device; 102-semiconductor device; 103-semiconductor device; 104-semiconductor device; 105-semiconductor device; D1-vertical direction; D2-horizontal direction; D3-horizontal direction; DE-drain structure; GE-gate structure; OP1-first opening; OP2-second opening; SE-source structure; SS-semiconductor structure. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0027] One embodiment of the present invention provides a semiconductor device, such as Figure 1As shown, semiconductor device 101 includes a source structure SE, a gate structure GE, a first opening OP1, a semiconductor structure SS, a gate dielectric layer 28, an insulating structure 34P, and a void 34V. The gate structure GE is disposed above the source structure SE. The first opening OP1 penetrates the gate structure GE in a vertical direction D1, where the vertical direction is the z-axis of a spatial rectangular coordinate system. The semiconductor structure SS is partially disposed in the first opening OP1, and at least a portion of the gate structure GE is located on two opposite sides of the semiconductor structure SS in a horizontal direction D2, where the horizontal direction is the x-axis or y-axis of the spatial rectangular coordinate system. The gate dielectric layer 28 is disposed in the first opening OP1 and is located between the semiconductor structure SS and the gate structure GE. At least a portion of the insulating structure 34P is disposed in the first opening OP1, and at least a portion of the semiconductor structure SS is located between the insulating structure 34P and the gate dielectric layer 28. The void 34V is located in the insulating structure 34P. The insulating structure 34P may be used to indirectly control the composition of the semiconductor structure SS and / or support the semiconductor structure SS. The voids 34V in the insulating structure 34P may be used to reduce the overall dielectric constant of the insulating structure 34P, thereby improving the operating performance of the semiconductor device 101 , but the present invention is not limited thereto.

[0028] In a more preferred embodiment based on the above embodiment, the above-mentioned source structure SE, gate structure GE, first opening OP1, semiconductor structure SS, gate dielectric layer 28 and insulating structure 34P can be arranged on the upper surface 10T of the dielectric layer 10, and the upper surface 10T and the lower surface 10B of the dielectric layer 10 can be two opposite surfaces of the dielectric layer 10 in the vertical direction D1. Therefore, the vertical direction D1 can be regarded as the thickness direction of the dielectric layer 10, but is not limited to this. As described herein, the distance in the vertical direction D1 between a relatively higher position and / or component and the upper surface 10T of the dielectric layer 10 may be greater than the distance in the vertical direction D1 between a relatively lower position and / or component and the upper surface 10T of the dielectric layer 10; the lower portion or bottom portion of each component may be closer to the upper surface 10T of the dielectric layer 10 in the vertical direction D1 than the upper portion or top portion of the component; another component above a certain component may be considered to be relatively far away from the upper surface 10T of the dielectric layer 10 in the vertical direction D1, and another component below a certain component may be considered to be relatively close to the upper surface 10T of the dielectric layer 10 in the direction D1.

[0029] In a more preferred embodiment based on the above embodiment, the semiconductor device 101 further includes a bottom semiconductor layer 18, a dielectric layer 20, a drain structure DE, a dielectric layer 26, a dielectric layer 38, and a second opening OP2. The dielectric layer 20 and the bottom semiconductor layer 18 may be disposed between the gate structure GE and the source structure SE in the vertical direction D1. The bottom semiconductor layer 18 may be disposed between the dielectric layer 20 and the source structure SE in the vertical direction D1. The semiconductor structure SS may penetrate the dielectric layer 20 in the vertical direction D1 and be connected to the bottom semiconductor layer 18. The dielectric layer 26 may be disposed on the gate structure GE in the vertical direction D1, and the first opening OP1 may penetrate the dielectric layer 26 and the gate structure GE in the vertical direction D1. The dielectric layer 38 may be disposed on the dielectric layer 26 in the vertical direction D1. The drain structure DE may be disposed on the semiconductor structure SS, the gate dielectric layer 28, and the dielectric layer 26 in the vertical direction D1. At least a portion of the drain structure DE may be disposed in the dielectric layer 38, but the present invention is not limited thereto.

[0030] In a more preferred embodiment based on the above embodiment, the second opening OP2 may penetrate the dielectric layer 20 in the vertical direction D1, the second opening OP2 may be directly connected to the first opening OP1, and a portion of the semiconductor structure SS may be disposed in the second opening OP2, so that the semiconductor structure SS may be directly connected to the bottom semiconductor layer 18 through the second opening OP2.

[0031] In a more preferred embodiment based on the above embodiment, the semiconductor structure SS may include a first semiconductor layer 30, a second semiconductor layer 32, and a third semiconductor layer 36. The first semiconductor layer 30 may be disposed in the first opening OP1, the second semiconductor layer 32 may be partially disposed in the first opening OP1 and partially disposed in the second opening OP2, and the third semiconductor layer 36 may be disposed on the insulating structure 34P in the vertical direction D1. The first semiconductor layer 30 may surround the second semiconductor layer 32 in a horizontal direction (e.g., horizontal direction D2 and / or horizontal direction D3), the second semiconductor layer 32 may surround the third semiconductor layer 36 and the insulating structure 34P in a horizontal direction (e.g., horizontal direction D2 and / or horizontal direction D3), a portion of the semiconductor structure SS (e.g., the third semiconductor layer 36) may be located between the insulating structure 34P and the drain structure DE in the vertical direction D1, and a portion of the second semiconductor layer 32 may be located between the insulating structure 34P and the bottom semiconductor layer 18 in the vertical direction D1.

[0032] In a more preferred embodiment based on the above embodiment, the semiconductor structure SS may be composed of a first semiconductor layer 30, a second semiconductor layer 32 and a third semiconductor layer 36, and the second semiconductor layer 32 in the semiconductor structure SS may be directly connected to the first semiconductor layer 30, the third semiconductor layer 36, the bottom semiconductor layer 18 and the insulating structure 34P respectively, but is not limited to this.

[0033] In a more preferred embodiment based on the above embodiment, the gate dielectric layer 28 may include a first portion 28A and a second portion 28B directly connected to the first portion 28A. The first portion 28A may extend generally along a vertical direction D1, while the second portion 28B may extend generally along a horizontal direction (e.g., horizontal direction D2 and / or horizontal direction D3) and be disposed between the semiconductor structure SS and the source structure SE in the vertical direction D1. In other words, a portion of the gate dielectric layer 28 may be sandwiched horizontally between the first semiconductor layer 30 of the semiconductor structure SS and the gate structure GE, while another portion of the gate dielectric layer 28 may be sandwiched vertically between the first semiconductor layer 30 and the dielectric layer 20. The gate dielectric layer 28 sandwiched between the first semiconductor layer 30 and the dielectric layer 20 in the vertical direction D1 may be considered as a protrusion of the gate dielectric layer 28 extending toward the insulating structure 34P, but the present invention is not limited thereto. Furthermore, the upper surface 34T of the insulating structure 34P may be directly connected to the third semiconductor layer 36, while the void 34V in the insulating structure 34P may be lower than the upper surface 34T of the insulating structure 34P in the vertical direction D1. Therefore, a portion of the insulating structure 34P may be located between the void 34V and the third semiconductor layer 36 in the vertical direction D1, while another portion of the insulating structure 34P may be located between the void 34V and the second semiconductor layer 32 in the vertical direction D1, but this is not a limitation. Furthermore, the void 34V may be located partially within the first opening OP1 and partially within the second opening OP2, but this is not a limitation.

[0034] In a more preferred embodiment based on the above embodiment, the source structure SE, gate structure GE, and drain structure DE may each be formed from multiple layers of conductive material. For example, the source structure SE may include a barrier layer 12, a barrier layer 16, and a conductive layer 14 disposed between the barrier layer 12 and the barrier layer 16 in the vertical direction D1. The gate structure GE may include a barrier layer 22 and a conductive layer 24 disposed on the barrier layer 22 in the vertical direction D1. The drain structure DE may include a barrier layer 40 and a conductive layer 42 disposed on the barrier layer 40 in the vertical direction D1, but the present invention is not limited thereto. The barrier layers 12, 16, 22, and 40 may include titanium nitride, tantalum nitride, or other suitable conductive barrier materials. The material compositions of the barrier layers 12, 16, 22, and 40 may be the same or different. The conductive layers 14, 24, and 42 may comprise copper, aluminum, tungsten, or other suitable low-resistivity conductive materials, and the material compositions of the conductive layers 14, 24, and 42 may be the same or different. Furthermore, the bottom semiconductor layer 18 and the first, second, and third semiconductor layers 30, 32, and 36 of the semiconductor structure SS may comprise silicon-containing semiconductor materials (such as, but not limited to, polycrystalline silicon or amorphous silicon), oxide semiconductor materials (such as, but not limited to, indium gallium zinc oxide), or other suitable semiconductor materials, and the material compositions of the first, second, and third semiconductor layers 30, 32, and 36 as well as the bottom semiconductor layer 18 may be the same or different.

[0035] In a more preferred embodiment based on the above embodiment, dielectric layers 10, 20, 26, and 28 may comprise oxide dielectric materials (such as, but not limited to, silicon oxide), nitride dielectric materials (such as, but not limited to, silicon nitride), or other suitable dielectric materials. Gate dielectric layer 28 may comprise nitride dielectric materials (such as, but not limited to, silicon nitride), oxide dielectric materials (such as, but not limited to, silicon oxide), high-k dielectric materials (such as, but not limited to, dielectric materials with a dielectric constant greater than 3.9 or greater than 4.52), or other suitable dielectric materials. Insulation structure 34P may comprise oxide insulating materials (such as, but not limited to, silicon oxide) or other suitable insulating materials. Furthermore, voids 34V within insulation structure 34P may comprise, but are not limited to, seams and / or air gaps formed by the manufacturing process for forming insulation structure 34P.

[0036] In a more preferred embodiment based on the above embodiment, as Figure 1 and 2As shown, the drain structure DE can completely cover the first opening OP1 in the vertical direction D1, and the first opening OP1 can completely cover the second opening OP2 in the vertical direction, but the present invention is not limited thereto. In some embodiments, the gate dielectric layer 28, the first semiconductor layer 30, the second semiconductor layer 32, and the insulating structure 34P can be columnar structures extending along the vertical direction D1, and the central axes of the columnar structures extending along the vertical direction D1 can substantially overlap with each other, but the present invention is not limited thereto. Therefore, in the top view of the semiconductor device 101, the gate structure GE can be horizontally (e.g., Figure 1 The semiconductor structure SS is surrounded by the first opening OP1 in the horizontal direction D2, the horizontal direction D3 and / or other horizontal directions substantially orthogonal to the vertical direction D1 shown in the figure. The second semiconductor layer 32 in the semiconductor structure SS may surround the insulating structure 34P and the third semiconductor layer 36 in the horizontal direction. The first semiconductor layer 30 may surround the second semiconductor layer 32, the insulating structure 34P and the third semiconductor layer 36 in the horizontal direction. The gate dielectric layer 28 may surround the first semiconductor layer 30, the second semiconductor layer 32, the insulating structure 34P and the third semiconductor layer 36 in the horizontal direction. In addition, the semiconductor structure SS may surround the insulating structure 34P in the top view and the cross-sectional view of the semiconductor device 101. It is worth noting that the shapes of the first opening OP1 and the second opening OP2 in the top view of the semiconductor device of the present invention are not necessarily the same as those in the figure. Figure 2 The conditions shown are limited and the visual design may require other different shapes.

[0037] In a more preferred embodiment based on the above embodiment, the dielectric layer 10 may be disposed on a substrate (not shown), and the substrate may include a semiconductor substrate such as a silicon substrate, a silicon-germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials, but is not limited thereto. Furthermore, other components (such as transistors) and / or circuits (not shown) may be formed on the substrate, and the semiconductor device 101 may be electrically connected downwardly and / or upwardly to the other components and / or circuits on the substrate, but is not limited thereto.

[0038] In a more preferred embodiment based on the above embodiment, the manufacturing method of the semiconductor device 101 can be integrated with the back end of line (BEOL) manufacturing process in the semiconductor manufacturing process, but is not limited thereto.

[0039] In a more preferred embodiment based on the above embodiments, the semiconductor device 101 can be regarded as having a vertical transistor structure in which the gate surrounds the semiconductor layer in the horizontal direction, but the present invention is not limited thereto.

[0040] See also Figure 1as well as Figures 3 to 9 ; Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 and Figure 9 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 4 for Figure 3 Schematic diagram of the situation afterwards, Figure 5 for Figure 4 Schematic diagram of the situation afterwards, Figure 6 for Figure 5 Schematic diagram of the situation afterwards, Figure 7 for Figure 6 Schematic diagram of the situation afterwards, Figure 8 for Figure 7 The following diagram shows the situation: Figure 9 for Figure 8 Schematic diagram of the situation afterwards. Figure 1 Can be considered as Figure 9 The following is a schematic diagram of the situation, but the present invention is not limited to this.

[0041] like Figure 1 As shown, the manufacturing method of the semiconductor device of this embodiment may include the following steps: forming a gate structure GE on the source structure SE; forming a first opening OP1, the first opening OP1 penetrating the gate structure GE in the vertical direction D1; forming a gate dielectric layer 28 in the first opening OP1; forming an insulating structure 34P and a semiconductor structure SS; at least a portion of the insulating structure 34P is formed in the first opening OP1, and the semiconductor structure SS is partially formed in the first opening OP1; the gap 34V is located in the insulating structure 34P, at least a portion of the gate structure GE is located on two opposite sides of the semiconductor structure SS in the horizontal direction D2, at least a portion of the semiconductor structure SS is located between the insulating structure 34P and the gate dielectric layer 28, and the gate dielectric layer 28 is located between the semiconductor structure SS and the gate structure GE.

[0042] In a more preferred embodiment based on the above embodiment, as Figure 3As shown, a source structure SE, a bottom semiconductor layer 18, a dielectric layer 20, a gate structure GE, and a dielectric layer 26 may be sequentially formed on the upper surface 10T of the dielectric layer 10. Then, a first opening OP1 is formed penetrating the dielectric layer 26 and the gate structure GE in the vertical direction D1, thereby exposing a portion of the dielectric layer 20. In other words, the bottom semiconductor layer 18 and the dielectric layer 20 may be formed on the source structure SE before the step of forming the gate structure GE, and the dielectric layer 20 may be formed on the bottom semiconductor layer 18. Therefore, the bottom semiconductor layer 18 may be located between the dielectric layer 20 and the source structure SE in the vertical direction D1, and the dielectric layer 20 may be located between the gate structure GE and the bottom semiconductor layer 18 in the vertical direction D1.

[0043] In a more preferred embodiment based on the above embodiment, as Figure 4 As shown, a gate dielectric layer 28 may be formed, and the gate dielectric layer 28 may be conformally formed on the bottom and sidewalls of the first opening OP1 and conformally formed on the dielectric layer 26. In other words, the gate dielectric layer 28 may be partially formed in the first opening OP1 and partially formed outside the first opening OP1. The gate dielectric layer 28 may be formed by a film formation process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable methods.

[0044] In a more preferred embodiment based on the above embodiment, as Figure 5 As shown, a first semiconductor layer 30 can be formed on the gate dielectric layer 28. The first semiconductor layer 30 can be conformally formed on the gate dielectric layer 28, so the first semiconductor layer 30 can be partially formed in the first opening OP1 and partially formed outside the first opening OP1. The first semiconductor layer 30 can be formed by a film formation process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable methods. In some embodiments, the gate dielectric layer 28 and the first semiconductor layer 30 can be formed by the same process, and the gate dielectric layer 28 and the first semiconductor layer 30 can be formed successively in the same process chamber, but the present invention is not limited thereto.

[0045] In a more preferred embodiment based on the above embodiment, as Figure 5 and Figure 6As shown, after forming the first semiconductor layer 30, the first semiconductor layer 30 and the gate dielectric layer 28 located outside the first opening OP1 can be removed, and a second opening OP2 can be formed to penetrate the dielectric layer 20 in the vertical direction D1 to expose a portion of the bottom semiconductor layer 18. In some embodiments, the second opening OP2 can overlap with the first opening OP1 in the vertical direction D1, the area of ​​the second opening OP2 in the vertical direction D1 can be smaller than the area of ​​the first opening OP1 in the vertical direction D1, and the second opening OP2 can be directly connected to the first opening OP1. In addition, a portion of the first semiconductor layer 30 and the gate dielectric layer 28 located at the bottom of the first opening OP1 needs to be removed to form the second opening OP2 that penetrates the dielectric layer 20. Therefore, a portion of the first semiconductor layer 30 and a portion of the gate dielectric layer 28 can be removed by the process of forming the second opening OP2. After the second opening OP2 is formed, the gate dielectric layer 28 can have the above-mentioned first portion 28A and second portion 28B, but is not limited thereto.

[0046] In a more preferred embodiment based on the above embodiment, as Figure 7 As shown, after the second opening OP2 is formed, a second semiconductor layer 32 can be formed. The second semiconductor layer 32 can be partially formed in the first opening OP1, partially formed in the second opening OP2, and partially formed outside the first opening OP1 and the second opening OP2. The second semiconductor layer 32 can be formed by a film forming process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable methods. In some embodiments, the second semiconductor layer 32 can be conformally formed on the bottom and sidewalls of the second opening OP2, on the sidewalls of the gate dielectric layer 28, and on the sidewalls of the first semiconductor layer 30, while the second semiconductor layer 32 located outside the first opening OP1 and the second opening OP2 can be formed on the dielectric layer 26, the gate dielectric layer 28, and the first semiconductor layer 30 in the vertical direction D1. The first semiconductor layer 30 can surround the second semiconductor layer 32 located in the first opening OP1 in the horizontal direction, and the second semiconductor layer 32 formed in the second opening OP2 can be connected to the bottom semiconductor layer 18.

[0047] In a more preferred embodiment based on the above embodiment, as Figure 8As shown, after the second semiconductor layer 32 is formed, an insulating material 34 can be formed on the second semiconductor layer 32. In some embodiments, the insulating material 34 can be partially formed in the first opening OP1, partially formed in the second opening OP2, and partially formed outside the first opening OP1 and the second opening OP2, but the present invention is not limited thereto. The insulating material 34 can be formed by a film forming process such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable methods, and the insulating material 34 can include an oxide insulating material (such as, but not limited to, silicon oxide) or other suitable insulating materials. In addition, by adjusting the process conditions for forming the insulating material 34 and / or adjusting the aspect ratio of the recess formed by the surface of the second semiconductor layer 32, the above-mentioned void 34V can be formed in the insulating material 34, but the present invention is not limited thereto.

[0048] In a more preferred embodiment based on the above embodiment, as Figure 8 and Figure 9 As shown, the insulating material 34 may be subjected to an etch-back process 90 to remove a portion of the insulating material 34 (e.g., removing the insulating material 34 outside the first opening OP1 and the second opening OP2 and removing a portion of the insulating material 34 in the first opening OP1) to form the insulating structure 34P. Therefore, after the etch-back process 90, the topmost surface (e.g., the top surface 34T) of the insulating structure 34P may be lower than the topmost surface of the dielectric layer 26 in the vertical direction D1, but the present invention is not limited thereto. It is worth noting that the method for forming the insulating structure 34P of the present invention may include, but is not limited to, the above-mentioned method. Figure 8 and Figure 9 The method is limited, so Figure 1 The insulating structure 34P shown in FIG. 3 may also be formed using other suitable methods depending on design requirements.

[0049] In a more preferred embodiment based on the above embodiment, as Figure 9 and Figure 1 As shown, after the insulating structure 34P is formed, a third semiconductor layer 36 may be formed on the insulating structure 34P. In some embodiments, the third semiconductor layer 36 and the second semiconductor layer 32 outside the first opening OP1 may be removed by a planarization process to form a Figure 1, so after this planarization process, the uppermost surface of the dielectric layer 26, the uppermost surface of the gate dielectric layer 28, the uppermost surface of the first semiconductor layer 30, the uppermost surface of the second semiconductor layer 32, and the uppermost surface of the third semiconductor layer 36 can be substantially coplanar, but the present invention is not limited thereto. By the above method, a semiconductor structure SS including the first semiconductor layer 30, the second semiconductor layer 32, and the third semiconductor layer 36 can be formed. It is worth noting that the method for forming the semiconductor structure SS of the present invention may include but is not limited to the above method. Figure 1 The semiconductor structure SS shown in FIG. 1 may also be formed using other suitable methods depending on design requirements.

[0050] like Figure 1 As shown, after forming the semiconductor structure SS, the drain structure DE and dielectric layer 38 described above may be formed to form the semiconductor device 101. In some embodiments, the material composition of the dielectric layer 26 may be different from the material composition of the dielectric layer 38 to provide a desired etching selectivity during the process, but the present invention is not limited thereto. The drain structure DE may be formed on the semiconductor structure SS and the gate dielectric layer 28. The drain structure DE may be directly connected to the semiconductor structure SS and the gate dielectric layer 28, and a portion of the semiconductor structure SS (e.g., the third semiconductor layer 36) may be located between the insulating structure 34P and the drain structure DE in the vertical direction D1.

[0051] The following description will focus on different embodiments of the present invention. For simplicity, the following description will focus on the different parts of each embodiment, and will not repeat the same parts. In addition, the same components in each embodiment of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0052] See also Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 as well as Figure 1 . Figure 10 FIG. 1 is a cross-sectional view of a semiconductor device 102 according to a second embodiment of the present invention. Figure 11 FIG. 1 is a schematic cross-sectional view of a semiconductor device 103 according to a third embodiment of the present invention. Figure 12 is a cross-sectional view of a semiconductor device 104 according to a fourth embodiment of the present invention. Figure 13 FIG. 1 is a schematic cross-sectional view of a semiconductor device 105 according to a fifth embodiment of the present invention.

[0053] In the present invention, by adjusting the process conditions for forming the insulating structure and / or adjusting the aspect ratio of the recess formed on the surface of the second semiconductor layer, the above-mentioned gap can be formed in the insulating structure and the position of the gap can be controlled. Figure 10As shown, the void 34V in the semiconductor device 102 may be completely located in the first opening OP1 and not formed in the second opening OP2. Figure 11 As shown, in the semiconductor device 103, the void 34V may be directly connected to the upper surface 34T of the insulating structure 34P, and a portion of the third semiconductor layer 36 may be formed in the void 34V and form another void 36V. In other words, the void 36V may be considered to be formed in the third semiconductor layer 36 located in the void 34V, and the void 34V may be considered to include a portion of the third semiconductor layer 36 and the void 36V, so the void 36V may also be considered to be formed and / or disposed in the insulating structure 34P. Therefore, a portion of the semiconductor structure SS (e.g., a portion of the third semiconductor layer 36) may be located between the void 36V and the insulating structure 34P. In addition, as Figure 12 As shown, in the semiconductor device 104, the void 34V may be partially formed in the first opening OP1 and partially formed in the second opening OP2, the third semiconductor layer 36 located in the void 34V may also be partially formed in the first opening OP1 and partially formed in the second opening OP2, and the void 36V may be formed in the first opening OP1, but is not limited thereto. Figure 13 As shown, in the semiconductor device 105, the void 34V may be completely located in the first opening OP1 and not formed in the second opening OP2, the void 34V may be directly connected to the upper surface 34T of the insulating structure 34P and the third semiconductor layer 36, and the third semiconductor layer 36 may not fill the void 34V.

[0054] In summary, in the semiconductor device and its manufacturing method of the present invention, the insulating structure can be used to indirectly control the composition of the semiconductor structure surrounding the insulating structure and / or support the semiconductor structure, and the gaps located in the insulating structure can be used to reduce the overall dielectric constant of the insulating structure, thereby improving the operating performance of the semiconductor device.

[0055] In summary, the description of the above embodiments is only used to help understand the method of the present invention and its core concept; at the same time, for those skilled in the art, according to the concept of the present invention, there will be changes in the specific implementation method and application scope, and the content of this specification should not be understood as limiting the present invention.

Claims

1. A semiconductor device, characterized in that: include: Source structure; a gate structure, disposed above the source structure; a first opening penetrating the gate structure in a vertical direction, wherein the vertical direction is the z-axis direction of a spatial rectangular coordinate system; a dielectric layer, disposed between the gate structure and the source structure in the vertical direction; a semiconductor structure, wherein a portion of the semiconductor structure is disposed in the first opening, and a portion of the gate structure is located on two opposite sides of the semiconductor structure in a horizontal direction, where the horizontal direction is the x-axis or y-axis direction of a spatial rectangular coordinate system; a gate dielectric layer disposed in the first opening and between the semiconductor structure and the gate structure; an insulating structure, a portion of the insulating structure being disposed in the first opening, and a portion of the semiconductor structure being located between the insulating structure and the gate dielectric layer; A gap is provided in the insulating structure, and a portion of the semiconductor structure is located between the gap and the insulating structure.

2. A semiconductor device according to claim 1, characterized in that The gate dielectric layer comprises: a first portion extending along the vertical direction; The second portion extends along the horizontal direction, and the second portion is arranged between the semiconductor structure and the source structure in the vertical direction.

3. The semiconductor device according to claim 1, wherein: Also includes: A bottom semiconductor layer is disposed between the dielectric layer and the source structure in the vertical direction, wherein the semiconductor structure penetrates the dielectric layer in the vertical direction and is connected to the bottom semiconductor layer.

4. A semiconductor device according to claim 3, characterized in that Also includes: A second opening penetrates the dielectric layer in the vertical direction, wherein the second opening is connected to the first opening, and the semiconductor structure is connected to the bottom semiconductor layer through the second opening.

5. A semiconductor device according to claim 4, characterized in that A portion of the gap is located in the first opening, and another portion is located in the second opening.

6. A semiconductor device according to claim 4, characterized in that The semiconductor structure comprises: A first semiconductor layer is disposed in the first opening; a second semiconductor layer, a portion of which is disposed in the first opening and another portion of which is disposed in the second opening; wherein, in a top view of the semiconductor device, the first semiconductor layer surrounds the second semiconductor layer; and the second semiconductor layer is connected to the bottom semiconductor layer; The third semiconductor layer is arranged above the insulating structure in the vertical direction; wherein, in a top view of the semiconductor device, the second semiconductor layer surrounds the third semiconductor layer; and the second semiconductor layer is connected to the first semiconductor layer and the third semiconductor layer respectively.

7. A semiconductor device according to claim 6, characterized in that: A portion of the second semiconductor layer is located between the bottom semiconductor layer and the insulating structure in the vertical direction.

8. The semiconductor device according to claim 1, wherein: The gap is located below the upper surface of the insulation structure in the vertical direction.

9. The semiconductor device according to claim 1, wherein: Also includes: A drain structure is disposed above the semiconductor structure and the gate dielectric layer, wherein in the vertical direction, a portion of the semiconductor structure is located between the insulating structure and the drain structure.

10. A method for manufacturing a semiconductor device, characterized in that: A method for manufacturing a semiconductor device according to any one of claims 1 to 9, the method comprising: forming a gate structure above the source structure; forming a first opening in a vertical direction and passing through the gate structure, wherein the vertical direction is the z-axis direction of the spatial rectangular coordinate system; forming a gate dielectric layer in the first opening; forming an insulating structure, wherein at least a portion of the insulating structure is located in the first opening; and forming a gap in the insulating structure; A semiconductor structure is formed, wherein a portion of the semiconductor structure is located in the first opening; at least a portion of the gate structure is located on two opposite sides of the semiconductor structure in a horizontal direction, the gate dielectric layer is located between the semiconductor structure and the gate structure, and at least a portion of the semiconductor structure is located between the insulating structure and the gate dielectric layer, wherein the horizontal direction is the x-axis or y-axis direction of a spatial rectangular coordinate system.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: Also includes: Before forming the gate structure, forming a bottom semiconductor layer on the source structure; A dielectric layer is formed on the bottom semiconductor layer, wherein the bottom semiconductor layer is located between the dielectric layer and the source structure in the vertical direction, and the dielectric layer is located between the gate structure and the bottom semiconductor layer in the vertical direction.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: Forming the semiconductor structure includes: forming a first semiconductor layer on the gate dielectric layer; A second opening is formed, which penetrates the dielectric layer in the vertical direction, wherein the second opening is connected to the first opening, and a portion of the first semiconductor layer and a portion of the gate dielectric layer are removed in the process of forming the second opening.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: forming the semiconductor structure, further comprising: After the second opening is formed, a second semiconductor layer is formed, wherein a portion of the second semiconductor layer is located in the first opening, another portion is located in the second opening, and the second semiconductor layer is connected to the bottom semiconductor layer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: A portion of the second semiconductor layer is located between the bottom semiconductor layer and the insulating structure in the vertical direction.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: Forming the insulating structure includes: forming an insulating material above the second semiconductor layer; An etch-back process is performed on the insulating material to remove a portion of the insulating material, thereby forming the insulating structure.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: forming the semiconductor structure, further comprising: A third semiconductor layer is formed on the insulating structure, wherein the second semiconductor layer is connected to the first semiconductor layer and the third semiconductor layer respectively, and the semiconductor structure includes the first semiconductor layer, the second semiconductor layer and the third semiconductor layer.

17. The method for manufacturing a semiconductor device according to claim 10, wherein: forming a gate dielectric layer in the first opening, comprising: Extending along the vertical direction to form a first portion; Extending along the horizontal direction to form a second portion; The gate dielectric layer includes the first portion and the second portion, wherein the second portion is located between the semiconductor structure and the source structure in the vertical direction.

18. The method for manufacturing a semiconductor device according to claim 10, wherein: Also includes: A drain structure is formed above the semiconductor structure and the gate dielectric layer, wherein a portion of the semiconductor structure is located between the insulating structure and the drain structure in the vertical direction.

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