A millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology

Abstract

The present invention discloses a millimeter-wave dual-frequency on-chip antenna with enhanced gain through packaging technology, comprising a packaging structure and a chip structure; the packaging structure comprises a carrier layer and a chip surrounding layer of the chip structure, and the carrier layer and the chip surrounding layer are connected by an adhesive layer; the adhesive layer and the chip surrounding layer of the packaging structure are provided with a middle groove, and the chip structure is located in the middle groove. The chip structure comprises a silicon substrate, an oxide layer and a passivation layer from bottom to top, and a chip antenna is engraved on the passivation layer. The oxide layer comprises ten metal layers, and the chip antenna is located in the tenth metal layer. The present invention adopts a symmetrical bowtie-shaped structure, which enables the antenna to operate in two frequency bands without increasing the chip area; the packaging structure is simple and low-cost. The package protects the chip from damage and interference from the external environment, and at the same time acts as a matching layer between two different media, the silicon substrate and the air, which can effectively couple the electromagnetic waves in the silicon substrate to the outside world, thereby improving the radiation performance of the antenna.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic products, and in particular relates to a millimeter-wave dual-frequency on-chip antenna with enhanced gain through packaging technology. Background Art

[0002] In recent years, with the rapid development of 5G wireless communications, radar, and personal consumer electronics, the realization of high-performance, low-cost, and low-power transceivers has become an important research topic. Antennas are the first unit of the receiving system and the last unit of the transmitting system. Whether discrete or integrated, they need to be connected to the circuit as an interface. Impedance matching between antennas and circuits is the key to ensuring maximum power transmission between modules. In the traditional design process, antenna engineers and circuit designers are independent of each other. The two are connected by 50 However, the disadvantage of this is that an impedance matching network needs to be designed, and the antenna designed on the PCB needs to be connected to the integrated circuit through wiring. The wiring greatly affects the matching performance and increases the loss and wiring complexity of the circuit. With the development of semiconductor technology, people have proposed to replace the traditional board-level system with a system on chip (SoC) to improve the system integration. The introduction of on-chip antennas is proposed to realize the real SoC. The emergence of on-chip antennas solves the above problems and is different from the traditional 50 The matching is different, providing more precise impedance matching control between the on-chip antenna and the front-end circuit. The collaborative design of the antenna and circuit can utilize the imaginary reactance of different components to achieve conjugate matching, thereby achieving better system optimization.

[0003] In the past few years, most on-chip antennas have adopted silicon-based technology. However, there are still many challenges in achieving high-performance on-chip antennas on silicon. For example, the silicon substrate has a high dielectric constant ( =11.9) and low resistivity ( =10Ω·cm), which makes the gain and efficiency of on-chip antennas very low. The gain of ordinary silicon-based on-chip antennas is generally around -10 dBi, and the efficiency is generally around 10%. On the other hand, the antenna size can be reduced to 1mm in the millimeter wave band, making it feasible to implement the antenna on chip. In order to improve the gain and efficiency of on-chip antennas, people have proposed the following solutions: (1) Use high-resistance silicon substrates instead of low-resistance silicon substrates to reduce loss and increase antenna gain. (2) Use micro-electromechanical Systems (MEMS) technology for collaborative design, dig out part of the substrate, thereby reducing loss and increasing antenna gain. (3) Make a silicon lens on the substrate on the back of the antenna so that the antenna energy is radiated through the silicon lens (I. Sarkas, J. Hasch, A. Balteanu, and SP Voinigescu, “AFundamental Frequency 120-GHz SiGe BiCMOS Distance Sensor With IntegratedAntenna,” IEEE Trans. Microw. Theory Tech. , vol. 60, no. 3, pp. 795–812, Mar. 2012, doi: 10.1109 / TMTT.2011.2176504.). However, all of the aforementioned improvements increase antenna gain by modifying the standard CMOS process, which in turn introduces many new challenges. For example, the introduction of micromachining significantly increases the complexity of the chip fabrication process, while the presence of cavities in the substrate also reduces chip reliability. Furthermore, while the introduction of silicon lenses can significantly increase antenna gain, the size of silicon lenses is generally much larger than the chip size, thus reducing the system's miniaturization.

[0004] Based on the standard CMOS process, scholars have also carried out a lot of research by changing the antenna radiation principle. The main methods are as follows: (1) Using an artificial magnetic conductor (AMC) to isolate the antenna from the silicon substrate (X.-Y. Bao, Y.-X. Guo, and Y.-Z. Xiong, “60-GHz AMC-Based Circularly Polarized On-Chip Antenna Using Standard 0.18-μ m CMOS Technology,” IEEE Trans. Antennas Propag., vol. 60, no. 5, pp. 2234–2241,2012, doi: 10.1109 / TAP.2012.2189725.), thereby partially shielding the influence of the substrate, reducing the loss of the electromagnetic field in the silicon substrate, and forming an in-phase mirror current to improve the antenna gain. (2) Based on the dielectric integrated waveguide (SIW) technology, a via is made from the antenna layer to the M1 layer to form a slot antenna plus a back-feed resonant cavity and prevent the electromagnetic field from entering the silicon substrate to improve the antenna gain; (3) A dielectric resonator (DR) with the same resonant frequency as the antenna is glued to the passivation layer above the antenna to construct a dielectric resonant antenna to form secondary radiation, guiding the electromagnetic field to radiate above the antenna, thereby improving the antenna gain and efficiency. However, these methods require high post-production processing costs and may also affect the performance of circuit components on the chip. Summary of the Invention

[0005] In order to solve the above problems, the present invention provides a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology. The purpose is to provide a high-gain dual-band on-chip antenna based on CMOS technology without increasing system complexity and cost.

[0006] The present invention is achieved through at least one of the following technical solutions.

[0007] A millimeter-wave dual-frequency on-chip antenna with enhanced gain through packaging technology comprises a packaging structure and a chip structure; the packaging structure comprises a carrier layer and a chip surrounding layer of the chip structure, the carrier layer and the chip surrounding layer being connected by an adhesive layer; the adhesive layer and the chip surrounding layer of the packaging structure are provided with a middle groove, and the chip structure is located in the middle groove.

[0008] Furthermore, the chip structure includes a silicon substrate, an oxide layer and a passivation layer from bottom to top, and a feed line is engraved on the passivation layer.

[0009] Furthermore, the oxide layer includes ten metal layers, and the chip antenna is located in the tenth metal layer.

[0010] Furthermore, the chip antenna is a cross-shaped structure with an opening in the middle.

[0011] Furthermore, the chip antenna includes a long arm and a short arm that are symmetrical to each other, and the excitation signals of the long arm and the short arm are of equal amplitude and phase. An adjacent long arm and short arm of the chip antenna are connected to the feeder through a metal via.

[0012] Furthermore, the length of the long arm is twice that of the short arm.

[0013] Furthermore, the long arm and the short arm are both trapezoidal in shape.

[0014] Furthermore, an impedance converter is provided on one side of the feeder, and the two are integrated.

[0015] Furthermore, the feed line is located on the eleventh metal layer of the passivation layer.

[0016] Furthermore, copper foil is provided on the upper and lower surfaces of the chip surrounding layer and the upper surface of the carrier layer.

[0017] Compared with the existing technology, the beneficial effects of the present invention are:

[0018] (1) The dual-band on-chip antenna adopts a symmetrical bow-tie structure, which enables the antenna to operate in two frequency bands without increasing the chip area.

[0019] (2) The packaging structure is simple and low-cost. The packaging protects the chip from damage and interference from the external environment, and at the same time acts as a matching layer between the two different media, the silicon substrate and air, which can effectively couple the electromagnetic waves in the silicon substrate to the outside world, thereby improving the radiation performance of the antenna.

[0020] (3) The antenna feed structure is placed on the top passivation layer, and the antenna is placed on the M10 metal layer with the highest resistivity, which can reduce the radiation loss of the on-chip antenna and thus improve the gain and efficiency of the on-chip antenna.

[0021] (4) The bow tie structure antenna has an opening in the middle, which reduces the electromagnetic coupling between the feed and the antenna and increases the impedance bandwidth of the antenna.

[0022] (5) The on-chip antenna can be integrated with CMOS process chips, eliminating the influence of interconnection lines between chips, making the structure simple, reducing integration and packaging costs, and simplifying the matching problem of signal transmission between chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent by describing in detail the embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0024] Figure 1 This is a front view of a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to an embodiment of the present invention;

[0025] Figure 2 This is a cross-sectional view of a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to an embodiment of the present invention;

[0026] Figure 3 This is a top view of a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to an embodiment of the present invention;

[0027] Figure 4This is a cross-sectional view of a chip structure of a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to an embodiment of the present invention;

[0028] Figure 5 This is a top view of a millimeter-wave dual-band on-chip antenna structure with enhanced gain through packaging technology according to an embodiment of the present invention;

[0029] Figure 6 This is a return loss diagram of a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to an embodiment of the present invention;

[0030] Figure 7 This is a diagram of the isolation of a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to an embodiment of the present invention;

[0031] Figure 8 This is a graph showing the gain and efficiency of a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to an embodiment of the present invention;

[0032] Figure 9 This is a directional pattern at 150 GHz of a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to an embodiment of the present invention;

[0033] Figure 10 This is a directional pattern at 300 GHz of a millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology in an embodiment of the present invention.

[0034] Figure 11 This is a schematic diagram of a dual-frequency on-chip antenna according to an embodiment of the present invention applied to a broadband radar system;

[0035] The figure shows: 1- packaging structure; 2- chip structure; 3- chip surrounding layer; 4- adhesive layer; 5- carrier layer; 6- copper foil; 7- bow tie antenna; 8- feed line; 9- impedance matching line; 10- passivation layer; 11- oxide layer; 12- silicon substrate. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0037] Example 1

[0038] A millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology includes a packaging structure 1 and a chip structure 2. The chip structure 2 and the packaging structure 1 are connected by a bonding wire. The bonding wire should be kept away from the chip antenna to reduce the impact on the chip antenna performance. The packaging structure is simple and low-cost.

[0039] like Figure 2 As shown, the package structure 1 includes a chip carrier layer 5 and a chip surrounding layer 3. The carrier layer 5 and the chip surrounding layer 3 are connected by an adhesive layer 4. The upper and lower surfaces of the chip surrounding layer 3 are both provided with copper foil 6. The carrier layer 5 and the chip surrounding layer 3 are bonded together by the adhesive layer 4. The adhesive layer 4 and the chip surrounding layer 3 of the package structure are provided with a middle groove for placing the chip structure 2, such as Figure 2 As shown, the position and size of the middle groove correspond to the opening.

[0040] In this embodiment, the carrier layer 5 of the chip is made of low-loss material and its size is L S * W S * h MS (like Figure 3 As shown); the copper foil 6 at the center of the carrier layer 5 is provided with an opening to propagate electromagnetic waves, and the length and width of the aperture are ( L C + S )*( W C + S )( S is the distance between the chip edge and the opening edge, L C and W C Represent the length and width of the chip respectively). The thickness of the adhesive layer 4 and the chip surrounding layer 3 are h P 、 h PS The chip surrounding layer 3 is made of a relatively low-cost material, and copper foil 6 is applied to the upper and lower surfaces thereof.

[0041] like Figure 4 As shown, the chip structure adopts 40nm CMOS process, the chip structure includes silicon substrate 12, oxide layer 11 and passivation layer 10, the chip structure is bonded to the carrier layer 5 with epoxy resin bonding sheet, the bonding sheet should be as thin as possible to reduce the impact on antenna performance, the chip size is L C * W C * h Si ,thickness h Si It is generally a standard 12mil, and can be further thinned to enhance radiation characteristics. The depth of the middle groove of the package structure ( h P + h MS ) should be slightly larger than the thickness of the chip ( h Si).

[0042] Due to the high dielectric constant of the silicon substrate 12 ( 11.9) causes the surface effect, which confines the electromagnetic wave in the silicon substrate 12, while its low resistivity ( The 10 Ω·cm resistance creates a low-resistance current loop between the chip antenna and the silicon substrate 12, causing the chip antenna's electromagnetic energy to be lost in the silicon substrate 12, resulting in low gain and efficiency. The package protects the chip from damage and interference from the external environment and also acts as a matching layer between the two dissimilar media of the silicon substrate 12 and air, effectively coupling electromagnetic waves from the silicon substrate 12 to the air, thereby improving the antenna's gain and efficiency.

[0043] For the 40nm CMOS process, the oxide layer 11 includes ten metal layers from bottom to top (M1 to M10 metal layers). Since the tenth metal layer M10 has the highest conductivity, the tenth metal layer is used to design the chip antenna, which can reduce the radiation loss of the on-chip chip antenna, thereby improving the gain and efficiency of the antenna.

[0044] The chip antenna has a symmetrical cross-shaped structure, with both the long and short arms shaped like trapezoids. The symmetrical long arms are approximately twice as long as the short arms, and the excitation signals for these two pairs of long and short arms should be of equal amplitude and in phase. Adjacent long and short arms are connected to feeder line 8 via metal vias, converting high-frequency current into radiatable electromagnetic waves. To prevent the chip antenna and feeder line 8 from intersecting, feeder line 8 is placed in a passivation layer, which also reduces interference with antenna radiation. An impedance transformer 9 is integrated on one side of feeder line 8.

[0045] Example 2

[0046] The antenna of this embodiment is a bow tie antenna 7, such as Figure 5 As shown, it is evolved from the traditional dipole antenna, with the advantages of wide bandwidth and low profile, and has wide bandwidth characteristics when the angle is large; the arm length of the bow tie antenna 7 L 1 and L 2 is an important parameter that determines the resonant frequency of the antenna. The longer the antenna arm, the better the low-frequency coverage performance of the antenna. The bow tie antenna 7 has an opening in the middle, which reduces the electromagnetic coupling between the antenna and the feeder and increases the impedance bandwidth of the antenna.

[0047] The bow tie antenna 7 comprises two pairs of symmetrical long arms and short arms, such as Figure 5 As shown, the long arm and the short arm are both trapezoidal in shape. The long arm is approximately twice as long as the short arm. The long arm works at low frequencies. f 1. Short arm works at high frequency f 2. Two pairs of bow-tie antennas are placed orthogonally, so the antennas can operate in two frequency bands without increasing the chip area;

[0048] In this embodiment, the passivation layer is provided with four feed lines 8, and each of the adjacent long arms and short arms is provided with two feed lines 8. An impedance transformer 9 is provided on one side of each feed line 8. The impedance transformer 9 is located between the two feed lines 8, and the two are integrated. Each of the two feed lines 8 is located in an adjacent long arm and short arm, and a spacing is provided between the two impedance transformers 9, such as Figure 5 shown.

[0049] The resonant frequency of the bow tie antenna 7 can be determined by the lengths of the long arm and the short arm. L 1 and L 2 adjustment, the input impedance is adjusted by the length of the feed line 8 L f1 、L f3 and width W f1 、 W f3 The length of the impedance converter 9 L f2 、 L f4 and width W f2 、 W f4 and the spacing of the impedance transformers D 1 、D 2 Adjustment: The circuit portion of the chip structure can be simulated by a large piece of metal to evaluate the impact of the circuit on the antenna.

[0050] When the impedance converter 9 is connected to the front-end integrated circuit, the antenna converts the high-frequency current of the feed line 8 into radiable electromagnetic waves, thereby transmitting and receiving signals.

[0051] Example 3

[0052] This embodiment is based on a high-gain dual-band on-chip antenna in 40nm CMOS process. f 1=150GHz, frequency f2 = 300GHz. The carrier layer 5 of the package structure 1 uses low-loss Rogers 3006, with dimensions of 4 cm * 4 cm * 0.752 mm. Its upper surface is copper-clad, with an opening at the center for electromagnetic wave propagation, with a diameter of 2.3 mm * 2.3 mm. The chip enclosure layer 3 can be made of lower-cost FR4, with a thickness of 0.2 mm. Both its upper and lower surfaces are copper-clad. The carrier layer 5 and chip enclosure layer 3 are bonded with epoxy resin adhesive, with a thickness of 0.1 mm. The thickness of the copper foil on the two layers of PCB surface is 35 μm. The chip is placed on the chip carrier layer 5 and bonded with an epoxy resin adhesive sheet 4. The thickness of the adhesive sheet 4 is approximately 20 μm, which has little impact on antenna performance. The chip silicon substrate 12 has dimensions of 2 mm * 2 mm * 12 mil. In this embodiment, the material of the chip carrier layer 5 is Rogers dielectric.

[0053] like Figure 6-10 As shown, Figure 6 The return loss curves of the antenna are shown, and their relative bandwidths are 30% ( f 1=150GHz) and 18% ( f 2=300GHz), indicating that the antenna is well matched in the frequency bands around 150GHz and 300GHz respectively. Figure 7 The antenna's port isolation in both frequency bands is shown, which is better than -20dB across the entire frequency band. Figure 8 The antenna's gain and radiation efficiency are shown near 150 GHz and 300 GHz, respectively. At 150 GHz, the gain and radiation efficiency are 0.3 dBi and 37%, respectively; at 300 GHz, the gain and radiation efficiency are 1.7 dBi and 29%, respectively. This demonstrates that the designed antenna's gain and radiation efficiency are improved, and their gain and radiation efficiency are relatively stable across both frequency bands. Figure 9 and Figure 10 The radiation patterns of the antenna at 150 GHz and 300 GHz are shown, indicating that the designed antenna has good directivity.

[0054] The dual-frequency on-chip antenna is applied to the broadband radar system, and the circuit modules in the radar system are integrated into the chip structure 2, such as Figure 11 The figure shows a block diagram of a radar system. The radar system includes a transmitter and a receiver, which share a common antenna. The transmitter includes an amplifier and a radar signal generator, with the amplifier output connected to a dual-frequency on-chip antenna. The receiver includes the dual-frequency on-chip antenna, an amplifier, a mixer, and a filter.

[0055] The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology, characterized in that: The invention comprises a packaging structure (1) and a chip structure (2); the packaging structure (1) comprises a carrier layer (5) of the chip structure (2) and a chip surrounding layer (3); the carrier layer (5) and the chip surrounding layer (3) are connected via an adhesive layer (4); the adhesive layer (4) and the chip surrounding layer (3) of the packaging structure are provided with a middle groove, and the chip structure (2) is located in the middle groove; The chip structure comprises a silicon substrate (12), an oxide layer (11) and a passivation layer (10) from bottom to top, and a feed line is engraved on the passivation layer (10); The oxide layer (11) includes ten metal layers, and the chip antenna is located in the tenth metal layer; The chip antenna is a cross-shaped structure with an opening in the middle; The chip antenna comprises a long arm and a short arm that are symmetrical to each other, and the excitation signals of the long arm and the short arm are of equal amplitude and phase, and an adjacent long arm and short arm of the chip antenna are connected to the feed line (8) through a metal via.

2. The millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to claim 1, characterized in that: The long arm is twice as long as the short arm.

3. The millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to claim 1, characterized in that: The long arm and the short arm are both trapezoidal in shape.

4. The millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to claim 1, characterized in that: An impedance converter (9) is provided on one side of the feeder (8), and the two are integrated.

5. The millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to claim 4, characterized in that: The feed line (8) is located on the eleventh metal layer of the passivation layer (10).

6. The millimeter-wave dual-band on-chip antenna with enhanced gain through packaging technology according to any one of claims 1 to 5, characterized in that: The upper and lower surfaces of the chip surrounding layer (3) and the upper surface of the carrier layer (5) are both provided with copper foil.

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