Charge pump and chip

Abstract

The embodiment of the present disclosure discloses a charge pump and a chip, the charge pump comprises a first capacitor, a second capacitor, a first control circuit and a second control circuit; the first control circuit discharges the first capacitor to a load circuit according to the potential of the second plate of the second capacitor, and at the same time, the second control circuit charges the second plate of the second capacitor by the second voltage source according to the potential of the second plate of the first capacitor; the first control circuit charges the second plate of the first capacitor by the first voltage source according to the potential of the second plate of the second capacitor, and at the same time, the second control circuit discharges the second capacitor to the load circuit according to the potential of the second plate of the first capacitor. The embodiment of the present disclosure does not need to use a complex control circuit to generate a control signal, but only needs to control the first control circuit and the second control circuit by the potential of the second plate of the first capacitor and the second plate of the second capacitor at the same time. That is, the first capacitor can be charged, and at the same time, the second capacitor is discharged, and vice versa.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to the technical field of semiconductor technology, and relates to but not limited to a charge pump and a chip. BACKGROUND

[0002] With the development of integrated circuits, the size of integrated circuits is also developing in the direction of stronger performance and smaller size, so the integrated circuits have the characteristics of miniaturization, integration and functionalization.

[0003] In the design of integrated circuits, it is often necessary to use a charge pump to adjust the voltage so that the voltage meets the driving requirements of a specific power device. The charge pump also occupies a certain proportion of the area in the integrated circuit, and how to miniaturize the charge pump has become a problem to be solved. SUMMARY

[0004] Therefore, the embodiment of the present disclosure provides a charge pump and a chip.

[0005] In a first aspect, the embodiment of the present disclosure provides a charge pump, which comprises:

[0006] a first capacitor, a first plate of the first capacitor receiving a clock signal;

[0007] a second capacitor, a first plate of the second capacitor receiving a complementary clock signal, the clock signal and the complementary clock signal being inverse signals of each other;

[0008] a first control circuit connected to a second plate of the first capacitor, a second plate of the second capacitor, a first voltage source and a load circuit;

[0009] a second control circuit connected to the second plate of the second capacitor, the second plate of the first capacitor, a second voltage source and the load circuit;

[0010] Wherein, the first control circuit makes the first capacitor discharge to the load circuit according to the potential of the second plate of the second capacitor, and at the same time, the second control circuit makes the second voltage source charge the second plate of the second capacitor according to the potential of the second plate of the first capacitor; the first control circuit makes the first voltage source charge the second plate of the first capacitor according to the potential of the second plate of the second capacitor, and at the same time, the second control circuit makes the second capacitor discharge to the load circuit according to the potential of the second plate of the first capacitor.

[0011] In some embodiments, the first control circuit comprises a first charging control circuit and a first discharging control circuit; the first charging control circuit is connected between the first voltage source and the second plate of the first capacitor; the first discharging control circuit is connected between the second plate of the first capacitor and the load.

[0012] The control end of the first charging control circuit and the control end of the first discharging control circuit are connected to the second plate of the second capacitor.

[0013] In some embodiments, the first charging control circuit comprises a first P-type transistor, the first plate of the first P-type transistor is connected to the first voltage source, the second plate of the first P-type transistor is connected to the second plate of the first capacitor, and the gate of the first P-type transistor is connected to the second plate of the second capacitor.

[0014] The first discharging control circuit comprises a first N-type transistor, the first plate of the first N-type transistor is connected to the load, the second plate of the first N-type transistor is connected to the second plate of the first capacitor, and the gate of the first N-type transistor is connected to the second plate of the second capacitor.

[0015] In some embodiments, the control end of the first charging control circuit and the control end of the first discharging control circuit are connected to the second plate of the second capacitor through a first wire.

[0016] In some embodiments, the second control circuit comprises a second charging control circuit and a second discharging control circuit; the second charging control circuit is connected between the second voltage source and the second plate of the second capacitor; the second discharging control circuit is connected between the second plate of the second capacitor and the load.

[0017] The control end of the second charging control circuit and the control end of the second discharging control circuit are connected to the second plate of the first capacitor.

[0018] In some embodiments, the second charging control circuit comprises a second P-type transistor, the first plate of the second P-type transistor is connected to the second voltage source, the second plate of the second P-type transistor is connected to the second plate of the second capacitor, and the gate of the second P-type transistor is connected to the second plate of the first capacitor.

[0019] The second discharging control circuit comprises a second N-type transistor, the first plate of the second N-type transistor is connected to the load, the second plate of the second N-type transistor is connected to the second plate of the second capacitor, and the gate of the second N-type transistor is connected to the second plate of the first capacitor.

[0020] In some embodiments, the control end of the second charging control circuit and the control end of the second discharging control circuit are connected to the second plate of the first capacitor through a second wire.

[0021] In some embodiments, the first voltage source and the second voltage source are ground terminals.

[0022] In some embodiments, the first capacitor and the first control circuit are arranged in a first direction in sequence, and the second capacitor and the second control circuit are arranged in the first direction in sequence; the first capacitor and the second capacitor are arranged in a second direction in sequence, and the first control circuit and the second control circuit are arranged in the second direction in sequence; wherein the first direction is perpendicular to the second direction.

[0023] In some embodiments, the first control circuit and the second control circuit are arranged in axial symmetry.

[0024] In some embodiments, the first capacitor and the second capacitor are arranged in axial symmetry.

[0025] In a second aspect, the embodiments of the present disclosure further provide a chip comprising the charge pump according to any one of the above embodiments.

[0026] In some embodiments, the chip is a memory chip.

[0027] The embodiments of the present disclosure do not need to use a complex control circuit to generate a control signal, but only need to use the potentials of the second plates of the first capacitor and the second capacitor to simultaneously control the first control circuit and the second control circuit, so that the first control circuit can make the first capacitor discharge to the load according to the potential of the second plate of the second capacitor, and at the same time, the second control circuit can charge the second capacitor by using the second voltage source under the action of the potential of the second plate of the first capacitor. The second control circuit can make the second capacitor discharge to the load according to the potential of the second plate of the first capacitor, and at the same time, the first control circuit can charge the second capacitor by using the first voltage source under the action of the potential of the second plate of the second capacitor. Since the embodiments of the present disclosure reduce the required control circuit, using the embodiments of the present disclosure can greatly save the area occupied by the charge pump circuit. For example, when the reduced control circuit accounts for half of the total amount of the original control circuit, about half of the circuit area can be saved. Moreover, the embodiments of the present disclosure can still ensure that the power conversion efficiency is basically unchanged under the premise that the charge sharing is fully performed. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A schematic diagram of the charge pump in some embodiments;

[0029] Figure 2A schematic diagram of voltage-time waveforms of a first clock signal CLK1 and a second clock signal CLK2 received by a charge pump in some embodiments;

[0030] Figure 3 A schematic diagram of a charge pump provided in embodiments of the present disclosure;

[0031] Figure 4 A schematic diagram of voltage-time waveforms of a clock signal CLK and a complementary clock signal CLK' received by a charge pump in embodiments of the present disclosure;

[0032] Figures 5-9 A schematic diagram of another charge pump provided in embodiments of the present disclosure;

[0033] Figure 10 A schematic diagram of voltage-time waveforms of points a and b in embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] For the purpose of promoting an understanding of the disclosure, the present disclosure will now be described in greater detail with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] In some embodiments, as shown in Figure 1 The charge pump 100 includes a first capacitor C3, a second capacitor C4, a first control circuit 10, a second control circuit 20, a third control circuit 30, and a fourth control circuit 40. The charge pump 100 is also connected with a load 70, and the charge pump is used to transfer charges to the load 70.

[0037] The first control circuit 10 and the first capacitor C3 are used to receive a first clock signal CLK1, and the second control circuit 20 and the second capacitor C4 are used to receive a second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 are complementary signals. Figure 2 A voltage-time waveform of the first clock signal CLK1 and the second clock signal CLK2 is shown.

[0038] During the time interval from t0 to t1, the first clock signal CLK1 is at a low level (VSS), and the second clock signal CLK2 is at a high level (VDD). During the time interval from t1 to t2, the first clock signal CLK1 is at a high level (VDD), and the second clock signal CLK2 is at a low level (VSS). The time interval from t0 to t2 can be considered as a cycle, and subsequent time intervals are repetitions of this cycle.

[0039] When the first capacitor C3 is charged at the rising edge of the first clock signal CLK1, a control signal is provided to the fourth control circuit 40 through the first control circuit 10, causing the second capacitor C4 to share charge with the load 70, that is, to transfer charge to the load 70. In this circuit, the control signal of the fourth control circuit 40 is generated by the first control circuit 10.

[0040] Similarly, when the second capacitor C4 is charged at the rising edge of the second clock signal CLK2, a control signal is provided to the third control circuit 30 through the second control circuit 20, so that the first capacitor C3 shares charge with the load 70, that is, the charge is transferred to the load 70. In this circuit, the control signal of the third control circuit 30 is generated by the second control circuit 20.

[0041] The above embodiment uses four control circuits to control the charging and discharging of the two capacitors respectively. This ensures that when the first charging / discharging circuit 30 is charging, the second charging / discharging circuit 40 is discharging; and when the first charging / discharging circuit 30 is discharging, the second charging / discharging circuit 40 is charging.

[0042] In some embodiments, if the area occupied by the first control circuit 10 and the second control circuit 20 is relatively large, the area occupied by the charge pump 100 will also increase accordingly. How to achieve miniaturization and flexibility of the charge pump 100 has become an urgent problem to be solved.

[0043] This disclosure provides a charge pump 1000, such as... Figure 3 As shown, the charge pump 1000 includes: a first capacitor 110, the first plate of the first capacitor 110 receiving a clock signal CLK;

[0044] The second capacitor 210 has a first plate that receives a complementary clock signal CLK', wherein the clock signal CLK and the complementary clock signal CLK' are inverse signals to each other.

[0045] The first control circuit 120 is connected to the second plate of the first capacitor 110, the second plate of the second capacitor 210, the first voltage source 130 and the load circuit 300.

[0046] The second control circuit 220 is connected to the second plate of the second capacitor 210, the second plate of the first capacitor 110, the second voltage source 230 and the load circuit 300.

[0047] The first control circuit 120 discharges the first capacitor 110 to the load circuit 300 according to the potential of the second plate of the second capacitor 210, and the second control circuit 220 charges the second plate of the second capacitor 210 by the second voltage source 230 according to the potential of the second plate of the first capacitor 110. The first control circuit 120 charges the second plate of the first capacitor 110 by the first voltage source 130 according to the potential of the second plate of the second capacitor 210, and the second control circuit 220 discharges the second capacitor 210 to the load circuit 300 according to the potential of the second plate of the first capacitor 110. In some embodiments, the load circuit 300 includes a load capacitor.

[0048] Figure 4 The voltage-time waveform diagrams of the clock signal CLK and the complementary clock signal CLK' are shown. In the t0-t1 time period, the clock signal CLK is at the low level V2, and the complementary clock signal CLK' is at the high level V1; in the t1-t2 time period, the clock signal CLK is at the high level V1, and the complementary clock signal CLK' is at the low level V2. The t0-t2 time period can be regarded as a period, i.e., the clock signal CLK and the complementary clock signal CLK' are periodic signals. In some embodiments, V2 can be VSS, and V1 can be VDD.

[0049] As shown in Figure 3 The charge pump 1000 shown in the embodiments of the present disclosure includes the first capacitor 110 and the second capacitor 210. The first plate of the first capacitor 110 is configured to receive the clock signal CLK, and the first plate of the second capacitor 210 is configured to receive the complementary clock signal CLK'. In some embodiments, the first plate of the first capacitor 110 is configured to receive the clock signal CLK', and the first plate of the second capacitor 210 is configured to receive the clock signal CLK. In summary, the signal received by the first plate of the first capacitor 110 and the signal received by the first plate of the second capacitor 210 are complementary signals.

[0050] The second plate of the first capacitor 110 is connected to the first control unit 120, and the second plate of the first capacitor 110 is also connected to the second control unit 220. That is, the voltage signal at the second plate of the first capacitor 110 (denoted as point A) can act on not only the first control unit 120 but also the second control unit 220.

[0051] The second plate of the second capacitor 210 is connected to the second control unit 220, and the second plate of the second capacitor 210 is also connected to the first control unit 120. That is, the voltage signal at the second plate of the second capacitor 210 (denoted as point B) can act on not only the second control unit 220 but also the first control unit 120.

[0052] The first control unit 120 is further connected to a first power supply end 130, and the first control unit 120 is configured to control the first voltage supply 130 to charge the point A.

[0053] The second control unit 220 is further connected to a second power supply end 230, and the second control unit 220 is configured to control the second voltage supply 230 to charge the point B.

[0054] The first control unit 120 is further connected to a load 300, and the first control unit 120 is configured to connect the first capacitor 110 and the load 300 to realize charge sharing between the first capacitor 110 and the load 300, i.e., the first capacitor 110 discharges the load 300.

[0055] The second control unit 220 is further connected to the load 300, and the second control unit 220 is configured to connect the second capacitor 210 and the load 300 to realize charge sharing between the second capacitor 210 and the load 300, i.e., the second capacitor 210 discharges the load 300.

[0056] The first control unit 120 controls the first voltage supply 130 to provide the first voltage to the point A according to the voltage of the point B, and charges the first capacitor 110, while the second control unit 220 controls the second capacitor 210 to discharge the load circuit 300 according to the voltage of the point A.

[0057] The second control unit 220 controls the second voltage supply 230 to provide the second voltage to the point B according to the voltage of the point A, and charges the second capacitor 210, while the first control unit 120 controls the first capacitor 110 to discharge the load circuit 300 according to the voltage of the point B.

[0058] The embodiment of the present disclosure does not need to use a control circuit, but only needs to control the first control circuit 120 and the second control circuit 220 simultaneously according to the potential of the point A and the potential of the point B, so that the first control circuit 120 controls the first capacitor 110 to discharge the load 300 according to the potential of the point B, while the second control circuit 220 controls the second capacitor 210 to discharge the load 300 according to the potential of the point A, and the first control circuit 120 controls the first voltage supply 130 to charge the point B according to the potential of the point B.

[0059] The embodiment of the present disclosure can greatly save the area occupied by the charge pump 1000 circuit, for example, when the area occupied by the control circuit is similar to the area occupied by the charging and discharging circuit, about half of the circuit area can be saved. Moreover, the embodiment of the present disclosure can still ensure that the power conversion efficiency is basically unchanged under the premise that the charge sharing is fully performed.

[0060] In some embodiments, asFigure 5 As shown, the first control circuit 120 includes a first charging control circuit 122 and a first discharging control circuit 121; the first charging control circuit 120 is connected between the first voltage source 130 and the second plate of the first capacitor 110; the first discharging control circuit 121 is connected between the second plate of the first capacitor 110 and the load 300.

[0061] The control terminal of the first charging control circuit 122 and the control terminal of the first discharging control circuit 121 are connected to the second plate of the second capacitor 210.

[0062] like Figure 5 As shown, the potential at point B can control the conduction or cutoff of the first charging control circuit 122 and the first discharging control circuit 121. For example, the first charging control circuit 122 is turned on under the influence of the potential at point B, while the first discharging control circuit 121 is turned off under the influence of the potential at point B. Or, the first charging control circuit 122 is turned off under the influence of the potential at point B, while the first discharging control circuit 121 is turned on under the influence of the potential at point B.

[0063] When the first charging control circuit 122 is turned on under the action of the potential at point B, since the first charging control circuit 120 is connected between the first voltage source 130 and the second plate of the first capacitor 110, the first voltage source 130 provides charge to the second plate of the first capacitor 110, so that the potential at point A is the first voltage.

[0064] When the first discharge control circuit 121 is turned on under the action of the potential at point B, since the first discharge control circuit 121 is connected between the second plate of the first capacitor 110 and the load 300, the first capacitor 110 and the load 300 achieve charge sharing.

[0065] In some embodiments, such as Figure 6 As shown, the first charging control circuit 122 includes a first P-type transistor P1, the first terminal of the first P-type transistor P1 is connected to the first voltage source 130, the second terminal of the first P-type transistor P1 is connected to the second plate of the first capacitor 110, and the gate of the first P-type transistor is connected to the second plate of the second capacitor 210.

[0066] The first discharge control circuit 121 includes a first N-type transistor N1, the first terminal of the first N-type transistor N1 is connected to the load 300, the second terminal of the first N-type transistor N1 is connected to the second plate of the first capacitor 110, and the gate of the first N-type transistor N1 is connected to the second plate of the second capacitor 210.

[0067] The first terminal of the first P-type transistor P1 can be either the source or the drain, and the second terminal can be either the drain or the source. For example, when its first terminal is the source, its second terminal is the drain; when its second terminal is the source, its first terminal is the drain. The gate of the first P-type transistor P1 is the control terminal of the first charging control unit 122.

[0068] The gate of the first P-type transistor P1 is connected to the second plate of the second capacitor 210. When the potential at point B is the first potential, for example, a low level, the first P-type transistor P1 is turned on, and the first voltage source 130 provides charge to point A through the first P-type transistor P1.

[0069] The first terminal of the first N-type transistor N1 can be either the source or the drain, and the second terminal can be either the drain or the source. For example, when its first terminal is the source, its second terminal is the drain; when its second terminal is the source, its first terminal is the drain. The gate of the first N-type transistor N1 is the control terminal of the first discharge control unit 121.

[0070] The gate of the first N-type transistor N1 is connected to the second plate of the second capacitor 210. When the potential at point B is the second potential, for example, a high level (the high level here is relative to the low level of the first potential), the first N-type transistor N1 is turned on, and the first capacitor 110 shares charge with the load through the first N-type transistor N1.

[0071] In some embodiments, such as Figure 5 As shown, the control terminals of the first charging control circuit 122 and the first discharging control circuit 121 are connected to the second plate of the second capacitor 210 via a first wire L1. The first wire L1 has a first length. In other embodiments, the control terminals of the first charging control circuit 122 and the first discharging control circuit 121 can be connected to the second plate of the second capacitor 210 via a conductive layer, conductive material, or conductive plug, etc.

[0072] In some embodiments, such as Figure 5 As shown, the second control circuit 220 includes a second charging control circuit 222 and a second discharging control circuit 221; the second charging control circuit 220 is connected between the second voltage source 230 and the second plate of the second capacitor 210; the second discharging control circuit 221 is connected between the second plate of the second capacitor 210 and the load 300.

[0073] The control terminal of the second charging control circuit 222 and the control terminal of the second discharging control circuit 221 are connected to the second plate of the first capacitor 110.

[0074] like Figure 5As shown, the potential at point A can control the turn-on or turn-off of the second charge control circuit 222 and the second discharge control circuit 221. For example, the second charge control circuit 222 is turned on under the action of the potential at point A, while the second discharge control circuit 221 is turned off under the action of the potential at point A. Or the second charge control circuit 222 is turned off under the action of the potential at point A, while the second discharge control circuit 221 is turned on under the action of the potential at point B.

[0075] When the second charge control circuit 222 is turned on under the action of the potential at point A, since the second charge control circuit 220 is connected between the second voltage source 230 and the second plate of the second capacitor 210, the second voltage source 230 provides charges to the second plate of the second capacitor 210, so that the potential at point B is the second voltage.

[0076] When the second discharge control circuit 221 is turned on under the action of the potential at point A, since the second discharge control circuit 221 is connected between the second plate of the second capacitor 210 and the load 300, the second capacitor 210 and the load 300 realize charge sharing.

[0077] In some embodiments, the second charge control circuit comprises a second P-type transistor, a first electrode of the second P-type transistor is connected to the second voltage source, a second electrode of the second P-type transistor is connected to the second plate of the second capacitor, and a gate of the second P-type transistor is connected to the second plate of the first capacitor.

[0078] The second discharge control circuit comprises a second N-type transistor, a first electrode of the second N-type transistor is connected to the load, a second electrode of the second N-type transistor is connected to the second plate of the second capacitor, and a gate of the second N-type transistor is connected to the second plate of the first capacitor.

[0079] The first electrode of the second P-type transistor P2 can be the source or the drain, and the second electrode can be the drain or the source, for example, when the first electrode is the source, the second electrode is the drain; when the second electrode is the source, the first electrode is the drain. The gate of the second P-type transistor P2 is the control electrode of the second charge control unit 122.

[0080] The gate of the second P-type transistor P2 is connected to the second plate of the first capacitor 110. When the potential at point A is a third potential, for example, a low level, the second P-type transistor P2 is turned on, and the second voltage source 230 provides charges to point B through the second P-type transistor P2.

[0081] The first terminal of the second N-type transistor N2 can be either the source or the drain, and the second terminal can be either the drain or the source. For example, when its first terminal is the source, its second terminal is the drain; when its second terminal is the source, its first terminal is the drain. The gate of the second N-type transistor N2 is the control terminal of the second discharge control unit 221.

[0082] The gate of the second N-type transistor N2 is connected to the second plate of the second capacitor 210. When the potential at point B is the fourth potential, for example, a high level (the high level here is relative to the low level of the third potential), the second N-type transistor N2 is turned on, and the second capacitor 210 shares charge with the load through the second N-type transistor N2.

[0083] In some embodiments, such as Figure 5 As shown, the control terminals of the second charging control circuit 222 and the second discharging control circuit 221 are connected to the second plate of the first capacitor 110 via a second wire L2. The second wire L2 has a second length. In other embodiments, the control terminals of the second charging control circuit 222 and the second discharging control circuit 221 can be connected to the second plate of the first capacitor 110 via a conductive layer, conductive material, or conductive plug, etc.

[0084] In some embodiments, the first length of the first conductor L1 and the second length of the second conductor L2 may be the same.

[0085] In some embodiments, such as Figure 8 As shown, the first voltage source 130 and the second voltage source 230 are grounded terminals. That is, when the first charging control unit 122 is turned on, the first voltage source 130 can provide ground voltage to the second plate of the first capacitor 110. When the second charging control unit 222 is turned on, the second voltage source 230 can provide ground voltage to the second plate of the second capacitor 210.

[0086] In some embodiments, such as Figure 7 As shown, the charge pump 1000 further includes:

[0087] Initialize circuit 400;

[0088] The initialization circuit 400 is used to provide a first initial potential Vx to the second plate of the first capacitor 110 and a second initial potential Vy to the second plate of the second capacitor 210 before the first capacitor 110 receives the clock signal CLK or the second capacitor 210 receives the complementary clock signal CLK'.

[0089] Before the charge pump 1000 receives the clock signal CLK, the initialization circuit 400 can provide a first initial voltage Vx to the second plate of the first capacitor 110 and a second initial voltage Vy to the second plate of the second capacitor 210. The first initial voltage Vx and the second initial voltage Vy can be lower than the high level V1 provided by the clock signal CLK. Due to the initial voltages, there is a voltage difference between the two plates of the first capacitor 110 or the second capacitor 210, and the first capacitor 110 or the second capacitor 210 is charged. The first initial voltage Vx and the second initial voltage Vy can be the same or different.

[0090] In some embodiments, due to the coupling of the internal circuit elements of the charge pump 1000, the potential at the second plate A of the first capacitor 110 before the charge pump 1000 receives the clock signal CLK can be coupled to the first initial voltage Vx, and the potential at the second plate B of the second capacitor 210 can be coupled to the second initial voltage Vy. The first initial voltage Vx and the second initial voltage Vy are both lower than the high level V1 provided by the clock signal CLK, and the first initial voltage Vx and the second initial voltage Vy can be the same or different.

[0091] In some embodiments, the initialization circuit 400 can be arranged outside the charge pump 1000 and coupled to the second plate of the first capacitor 110 and the second plate of the second capacitor 210 through wires, contact nodes, etc. to provide the first initial voltage Vx and the second initial voltage Vy before the charge pump 1000 receives the clock signal CLK.

[0092] In some embodiments, as shown in Figure 3 the first capacitor 110 and the first control circuit 120 are arranged in a first direction, for example, the X direction, and the second capacitor 210 and the second control circuit 220 are arranged in the first direction, for example, the X direction; the first capacitor 110 and the second capacitor 210 are arranged in a second direction, for example, the Y direction, and the first control circuit 120 and the second control circuit 220 are arranged in the second direction, for example, the Y direction; and the first direction (for example, the X direction) is perpendicular to the second direction (for example, the Y direction).

[0093] In some embodiments, as shown in Figure 3 the first control circuit 120 and the second control circuit 220 are arranged in axial symmetry. For example, the first control circuit 120 and the second control circuit 220 are symmetric about the axis X1. The axis X1 extends in the X direction.

[0094] In some embodiments, the first capacitor 110 and the second capacitor 210 are arranged in axial symmetry. For example, the first capacitor 110 and the second capacitor 210 are symmetric about the axis X1.

[0095] In some embodiments, the load 300 can be located on the axis X1.

[0096] In a second aspect, the embodiments of the present disclosure further provide a chip comprising the charge pump according to any one of the above embodiments.

[0097] The chip includes, but is not limited to, a CPU (Central Processing Unit) chip, a memory chip, a digital multimedia chip, and the like.

[0098] In some embodiments, the chip is a memory chip.

[0099] The memory chip includes, but is not limited to, a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a DRAM (Dynamic Random Access Memory), a FRAM (Ferroelectric Random Access Memory), a MRAM (Magnetoresistive Random Access Memory), a PCRAM (Phase Change Random Access Memory), a RRAM (Resistive Random Access Memory), a Nano-RAM (Nano Random Access Memory), and the like.

[0100] The embodiments of the present disclosure further provide the following examples, as shown in Figure 9 The first buffer 510 is connected between the clock signal CLK and the first capacitor 110, and is used to maintain the clock signal CLK to avoid signal attenuation. For example, the first buffer 510 can be a repeater or an inverter.

[0101] The second buffer 520 is connected between the complementary signal CLK' and the second capacitor 210, and is used to maintain the complementary signal CLK' to avoid signal attenuation. For example, the second buffer 520 can be a repeater or an inverter.

[0102] The voltage-time waveform diagram of the clock signal CLK after passing through the first buffer 510 and reaching the first plate a of the first capacitor 110 is shown in Figure 2, and the voltage-time waveform diagram of the complementary signal CLK' after passing through the second buffer 520 and reaching the first plate b of the second capacitor 210 is shown in Figure 3. Figure 10 At time period t0-t1, the voltage at point a is VDD, and the voltage at point b is VSS. At time period t1-t2, the voltage at point a is VSS, and the voltage at point b is VDD. The time period t0-t2 can be regarded as a clock cycle. The subsequent time period is a cycle of the clock cycle.

[0103] Further, before the clock signal CLK is sent out, due to the coupling effect of the internal circuit elements of the charge pump 1000, the potential at the second plate A of the first capacitor 110 is coupled to a first initial potential Vx, and the potential at the second plate B of the second capacitor 210 is coupled to a second initial potential Vy. The first initial potential Vx is less than VDD, and the second initial potential Vy is less than VDD. The first initial potential Vx and the second initial potential Vy can be the same or different.

[0104] At time period t0-t1, the voltage at the first plate (i.e., point a) of the first capacitor 110 is VDD, and the potential at the second plate (i.e., point A) of the first capacitor 110 is Vx. At this time, the first plate 110 is charged first.

[0105] At time t1, the potential at point a is inverted from VDD to VSS, and the voltage variation is (VSS-VDD). The voltage variation at point A is also (VSS-VDD), and the voltage at point A is (Vx+(VSS-VDD)) at this time. For the second charge control unit, i.e., the second P-type transistor P2 (denoted as P2), V gs (Vx+(VSS-VDD)-VSS) is less than the threshold voltage of P2, and P2 is turned on. After P2 is turned on, the potential at point B is pulled from the second initial potential Vy to VSS. For the first charge control unit, i.e., the first P-type transistor P1 (denoted as P1), V gs (VSS-VSS) is greater than the threshold voltage of P1, and P1 is turned off. For the first discharge control unit, i.e., the first N-type transistor N1 (denoted as N1), V gs (VSS-(Vx+(VSS-VDD)) is greater than the threshold voltage of N1, and N1 is turned on, and the first capacitor 110 realizes charge sharing with the load through N1. For the second charge control unit, i.e., the second N-type transistor N2 (denoted as N2), V gs (Vx+(VSS-VDD)-VSS) is less than the threshold voltage of N2, and N2 is turned off. th

[0106] ​Therefore, at the time t1 to t2, the first capacitor 110 discharges to the load 300, and the potential of point A gradually increases until the potential of point A no longer changes after the N1 is turned off. Meanwhile, since the potential of point b is VDD and the potential of point B is VSS (since the P2 is turned on, the potential of point B remains unchanged at the time t1 to t2), the second capacitor 210 is charged at this time.

[0107] At the time t2, the potential of point b flips to VSS, and the change amount of the potential of point b is (VSS-VDD). Therefore, the change amount of the potential of point B is also (VSS-VDD), and the potential of point B is (2VSS-VDD). For the P1, V gs = (2VSS-VDD-VSS) is less than the threshold voltage of the P1, the P1 is turned on, the first voltage terminal 130 is connected to the ground voltage, and the voltage of point A is pulled to VSS. For the P2, V gs = (VSS-VSS) is less than the threshold voltage of the P2, the P2 is turned off, and for the N2, V gs = (VSS-(2VSS-VDD)) is greater than the threshold voltage of the N2, the N2 is turned on. For the N1, V gs = (2VSS-VDD-VSS) is less than the threshold voltage of the N1, the N1 is turned off.

[0108] Therefore, at the time t2 to t3, the second capacitor 210 discharges to the load 300, and the potential of point B continuously increases until the potential of point B no longer changes after the N2 is turned off. Meanwhile, since the potential of point a is VDD and the potential of point A is VSS (since the P1 is turned on, the potential of point A remains unchanged at the time t2 to t3), the first capacitor 110 is charged at this time.

[0109] In summary, the embodiment of the present disclosure uses a simple phase complementary circuit structure to achieve the charging of the first capacitor C1 while the potential output of the second capacitor C2. Moreover, the charging of the second capacitor C2 while the potential output of the first capacitor C1 is achieved.

[0110] The embodiment of the present disclosure uses two control circuits to make the two capacitors charge and share charges at the rising and falling edges of the clock signal or the complementary clock signal to which the two control circuits are connected. The voltage signal to be transmitted to the output terminal of one control circuit is used as the control signal for charging or discharging of the other control circuit, so that the charge pump function of the control circuit without additional generation of the control signal is achieved.

[0111] The replacement can save nearly half of the area resources, and still ensure that the power conversion efficiency is basically unchanged under the premise that the charge sharing is fully performed, and is particularly suitable for high-voltage charge pump circuits with strict area requirements

[0112] It should be understood that any reference to an "embodiment" or "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of steps in the above-described various embodiments of the disclosure does not mean that the execution order of the steps is prior or posterior, and the execution order of the steps should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the disclosure. The sequence number of the above-described embodiments of the disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0113] It should be noted that the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0114] The above describes only the embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the disclosure, which should be covered within the protection scope of the disclosure. Therefore, the protection scope of the disclosure should be subject to the protection scope of the claims.

Claims

1. A charge pump characterized by, The charge pump comprises: a first capacitor, a first plate of the first capacitor receiving a clock signal; a second capacitor, a first plate of the second capacitor receiving a complementary clock signal, the clock signal and the complementary clock signal being complementary signals; a first control circuit, connecting a second plate of the first capacitor, a second plate of the second capacitor, a first voltage source and a load circuit; a second control circuit, connecting the second plate of the second capacitor, the second plate of the first capacitor, a second voltage source and the load circuit; wherein the first control circuit discharges the first capacitor to the load circuit according to the potential of the second plate of the second capacitor, and simultaneously, the second control circuit charges the second plate of the second capacitor by the second voltage source according to the potential of the second plate of the first capacitor; the first control circuit charges the second plate of the first capacitor by the first voltage source according to the potential of the second plate of the second capacitor, and simultaneously, the second control circuit discharges the second capacitor to the load circuit according to the potential of the second plate of the first capacitor.

2. The charge pump of claim 1, wherein, The first control circuit comprises a first charging control circuit and a first discharging control circuit; the first charging control circuit is connected between the first voltage source and the second plate of the first capacitor; the first discharging control circuit is connected between the second plate of the first capacitor and the load; the control end of the first charging control circuit and the control end of the first discharging control circuit are connected to the second plate of the second capacitor.

3. The charge pump of claim 2, wherein, The first charging control circuit comprises a first P-type transistor, a first electrode of the first P-type transistor being connected to the first voltage source, a second electrode of the first P-type transistor being connected to the second plate of the first capacitor, and a gate of the first P-type transistor being connected to the second plate of the second capacitor; The first discharging control circuit comprises a first N-type transistor, a first electrode of the first N-type transistor being connected to the load, a second electrode of the first N-type transistor being connected to the second plate of the first capacitor, and a gate of the first N-type transistor being connected to the second plate of the second capacitor.

4. The charge pump of claim 2, wherein, The control end of the first charging control circuit and the control end of the first discharging control circuit are connected to the second plate of the second capacitor by a first wire.

5. The charge pump of claim 1, wherein, The second control circuit comprises a second charging control circuit and a second discharging control circuit; the second charging control circuit is connected between the second voltage source and the second plate of the second capacitor; the second discharging control circuit is connected between the second plate of the second capacitor and the load; the control end of the second charging control circuit and the control end of the second discharging control circuit are connected to the second plate of the first capacitor.

6. The charge pump of claim 5, wherein, The second charging control circuit comprises a second P-type transistor, a first electrode of the second P-type transistor being connected to the second voltage source, a second electrode of the second P-type transistor being connected to the second plate of the second capacitor, and a gate of the second P-type transistor being connected to the second plate of the first capacitor; The second discharge control circuit comprises a second N-type transistor, a first pole of the second N-type transistor is connected to the load, a second pole of the second N-type transistor is connected to a second pole plate of the second capacitor, and a gate of the second N-type transistor is connected to the second pole plate of the first capacitor.

7. The charge pump of claim 6, wherein, A control end of the second charge control circuit and a control end of the second discharge control circuit are connected to the second pole plate of the first capacitor through a second wire.

8. The charge pump according to any one of claims 1 to 7, characterized in that The first voltage source and the second voltage source are ground terminals.

9. The charge pump of claim 1, wherein, The first capacitor and the first control circuit are arranged in a first direction in sequence, and the second capacitor and the second control circuit are arranged in the first direction in sequence; the first capacitor and the second capacitor are arranged in a second direction in sequence, and the first control circuit and the second control circuit are arranged in the second direction in sequence; wherein the first direction is perpendicular to the second direction.

10. The charge pump of claim 9, wherein, The first control circuit and the second control circuit are arranged in axial symmetry.

11. The charge pump of claim 9, wherein, The first capacitor and the second capacitor are arranged in axial symmetry.

12. A chip, characterized by The chip is a memory chip.

13. The chip of claim 12, wherein, The chip is a memory chip.

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