A differential delay unit and a numerically controlled ring oscillator integrated circuit with strong robustness
By designing differential delay units and variable capacitor arrays, the problems of power supply noise sensitivity and temperature variation of ring oscillators are solved, achieving clock jitter suppression that is insensitive to power supply noise and improving the accuracy of digital phase-locked loops, exhibiting excellent robustness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU TUOER MICROELECTRONICS CO LTD
- Filing Date
- 2022-12-02
- Publication Date
- 2026-06-26
AI Technical Summary
Existing power supply noise-insensitive ring oscillators suffer from problems such as large parasitic capacitance, low regulation efficiency, and poor robustness, and cannot effectively cope with the effects of temperature and process changes.
The differential delay unit structure includes a latch, an inverter with non-inverting and inverting inputs, and first and second resistor array adjustment circuits. The number of resistors through which the current flows is adjusted by controlling the opening and closing of the switch. Combined with a positive temperature coefficient compensation resistor unit and a variable capacitor array, the sensitivity of the power supply voltage can be adjusted.
It effectively suppresses clock jitter caused by power supply noise, improves the accuracy of digital phase-locked loops, does not introduce additional parasitic capacitance, and maintains stable performance with excellent robustness over a wide temperature and process variation range.
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Figure CN115940886B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital phase-locked loop technology, and in particular to a differential delay unit and a robust numerically controlled ring oscillator integrated circuit. Background Technology
[0002] The numerically controlled oscillator (CNC) circuit is a core component of a digital phase-locked loop (PLL) chip. Its output clock, after frequency division, is compared with the PLL's input reference clock. After passing through frequency and phase detectors, loop filters, and other modules, the clock signal is fed back to the CNC oscillator's input, enabling functions such as phase locking, clock jitter filtering, and frequency synthesis. In integrated circuits, on-chip oscillators mainly include LC oscillators and ring oscillators. Compared to LC oscillators, which occupy a large chip area due to their inductance, ring oscillators, although noisier, are widely used in integrated circuits due to their smaller footprint. The clock jitter of the CNC ring oscillator is crucial to the performance of the digital PLL system. In high-speed data communication, the clock jitter of the digital PLL output clock caused by the CNC ring oscillator results in a phase shift between the sampling clock and the sampled data. This leads to a smaller sampling time window for the sampled data, thereby increasing the system's bit error rate. The clock jitter of the ring oscillator mainly originates from noise in its internal circuitry and power supply voltage. Clock jitter caused by internal circuit noise can typically be suppressed by optimizing the internal circuit structure of the ring oscillator to minimize the number of components, increase transistor size, and increase signal swing. Clock jitter caused by power supply noise is usually suppressed using a differential ring oscillator because it has a high common-mode rejection ratio. Common differential delay unit structures include... Figure 1 As shown, (a) is a differential amplifier type, (b) is an n-transistor input-diode parallel cross-coupled load type, (c) is an inverter input-latch load type, and (d) is another form of the inverter input-latch load type.
[0003] Currently, several techniques exist to further reduce the sensitivity of ring oscillators to power supply noise. These techniques primarily involve optimizing the power supply or bias circuitry of the ring oscillator. For example, one paper employs a self-biasing circuit based on an operational amplifier and a reference voltage source to provide a constant bias voltage to the ring oscillator independent of the power supply voltage. This ensures that the ring oscillator's operating state is largely unaffected by power supply voltage variations, effectively reducing its sensitivity to power supply noise. Another paper uses a similar approach, constructing a power supply noise filter based on an operational amplifier, level shifter, and PMOS transistor. This filter provides the ring oscillator with a weakly correlated supply voltage through the feedback of the operational amplifier, effectively suppressing power supply noise. However, these methods only reduce the ring oscillator's sensitivity to power supply noise from the perspective of the supply voltage or bias circuitry; they do not improve the circuit structure of the ring oscillator itself, thus achieving limited effectiveness. In another document, based on the commonly used inverter input-latch load type delay unit, a compensation resistor RD is introduced to compensate for the power supply voltage sensitivity of the delay unit, thus forming a power supply noise-insensitive ring oscillator. Its delay unit is as follows: Figure 2 As shown. Since the propagation delay of the inverter has a positive power supply voltage sensitivity coefficient, while the propagation delay of the latch has a negative power supply voltage sensitivity coefficient, the ratio between the two can be adjusted by adjusting the value of the compensation resistor, thereby reducing the sensitivity of the ring oscillator to the power supply voltage to near 0.
[0004] However, this technique has a significant drawback: the ring oscillator's sensitivity to power supply voltage varies greatly with temperature and process variations. Changes in ambient temperature or deviations in the integrated circuit manufacturing process can reduce the ring oscillator's ability to suppress power supply noise. To overcome this drawback, an n-type MOS transistor operating in the linear region and two series resistors are introduced in parallel with the aforementioned compensation resistor. By controlling the gate voltage of the n-type MOS transistor, the range of the ring oscillator's insensitivity to power supply voltage can be extended, and adjustments can be made to accommodate process variations. Figure 3 As shown. However, this structure also has three drawbacks: First, the path in parallel with the compensation resistor introduces more parasitic capacitance to the output node of the delay unit, which is not conducive to the rapid start-up of the oscillator and the improvement of the output frequency; second, this adjustment method is relatively inefficient, requiring up to 10 bits of adjustment to obtain good accuracy; in addition, this adjustment method cannot effectively cope with the effects of temperature changes, and the control voltage must be adjusted in real time according to the ambient temperature to obtain a good power supply noise suppression effect. It is not possible to obtain good temperature characteristics through one-time fuse adjustment, which is not conducive to the rapid operation of the ring oscillator.
[0005] Therefore, overcoming the shortcomings of existing power supply noise-insensitive ring oscillators, such as large parasitic capacitance, low regulation efficiency, and poor robustness, is a technical problem that needs to be solved. Summary of the Invention
[0006] This invention discloses a differential delay unit and a robust numerically controlled ring oscillator integrated circuit, which can overcome the shortcomings of existing power supply noise-insensitive ring oscillators, such as large parasitic capacitance, low regulation efficiency, and poor robustness.
[0007] To solve the above-mentioned technical problems, the present invention provides a differential delay unit, comprising:
[0008] latch;
[0009] The non-inverting input is connected to the inverter and then to the first terminal of the latch.
[0010] The inverting input is connected to the second terminal of the latch;
[0011] A first resistor array adjustment circuit is connected between the third terminal of the latch and the voltage source. The first resistor array adjustment circuit includes multiple first switches connected in parallel and resistors connected between two adjacent first switches. By controlling the opening and closing of one or more of the first switches, the number of resistors through which current flows can be adjusted.
[0012] The second resistor array adjustment circuit is connected between the fourth terminal of the latch and the reference ground. The second resistor array adjustment circuit includes a plurality of parallel second switches and a resistor connected between two adjacent second switches. By controlling the opening and closing of one or more of the second switches, the number of resistors through which the current flows can be adjusted.
[0013] The first resistor array adjustment circuit and the second resistor array adjustment circuit are used to adjust the power supply voltage sensitivity of the latch.
[0014] In an optional embodiment, the resistors in the first resistor array adjustment circuit and the resistors in the second resistor array adjustment circuit both have positive temperature coefficients. A first compensation resistor unit with a positive temperature coefficient is also connected between the first terminal of the latch and the non-inverting input inverter, and a second compensation resistor unit with a positive temperature coefficient is also connected between the second terminal of the latch and the inverting input inverter.
[0015] In an optional embodiment, the first compensation resistor unit includes a first resistor and a second resistor connected in series, wherein the first resistor is input to the inverter near the non-inverting input, and the temperature coefficient of the first resistor is 15-20 times that of the second resistor; the second compensation resistor unit includes a third resistor and a fourth resistor connected in series, wherein the fourth resistor is input to the inverter near the inverting input, and the temperature coefficient of the third resistor is 15-20 times that of the fourth resistor.
[0016] In an optional configuration, the temperature coefficient of the resistor in the first resistor array adjustment circuit is 7-9 times that of the second resistor and the fourth resistor, and the temperature coefficient of the resistor in the second resistor array adjustment circuit is the same as that of the second resistor and the fourth resistor.
[0017] In an optional embodiment, the non-inverting input inverter includes:
[0018] A first PMOS transistor and a first NMOS transistor, wherein the source of the first PMOS transistor is connected to the voltage source, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and connected to the first terminal of the latch, the source of the first NMOS transistor is connected to the reference ground, and the gates of the first PMOS transistor and the first NMOS transistor are connected.
[0019] The inverting input inverter includes:
[0020] A second PMOS transistor and a second NMOS transistor, wherein the source of the second PMOS transistor is connected to the voltage source, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and connected to the second terminal of the latch, the source of the second NMOS transistor is connected to the reference ground, and the gates of the second PMOS transistor and the second NMOS transistor are connected.
[0021] In an optional embodiment, the latch includes:
[0022] A third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor are provided. The gate of the third PMOS transistor is connected to the gate of the third NMOS transistor, and the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, and also connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor. The source of the third PMOS transistor is connected to the first resistor array adjustment circuit. The source of the third NMOS transistor is connected to the second resistor array adjustment circuit.
[0023] The gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and is also connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor; the source of the fourth PMOS transistor is connected to the first resistor array adjustment circuit; and the source of the fourth NMOS transistor is connected to the second resistor array adjustment circuit.
[0024] In an optional embodiment, the first resistor array adjustment circuit is divided into a first adjustment unit and a second adjustment unit. The first adjustment unit is connected between the source of the third PMOS transistor and the voltage source, and the second adjustment unit is connected between the source of the fourth PMOS transistor and the voltage source.
[0025] The second resistor array adjustment circuit is divided into a third adjustment unit and a fourth adjustment unit. The third adjustment unit is connected between the source of the third NMOS transistor and the reference ground, and the fourth adjustment unit is connected between the source of the fourth NMOS transistor and the reference ground.
[0026] In an optional embodiment, the differential delay unit further includes a first decoder and a second decoder. The first decoder is connected to the first resistor array adjustment circuit, and the second decoder is connected to the second resistor array adjustment circuit. The first decoder is used to control the opening and closing of the switches in the first resistor array adjustment circuit, and the second decoder is used to control the opening and closing of the switches in the second resistor array adjustment circuit.
[0027] The present invention also provides a robust numerically controlled ring oscillator integrated circuit, including at least two of the above-mentioned differential delay units, and further including multiple variable capacitor arrays, wherein the variable capacitor arrays are connected between two adjacent differential delay units, and the overall capacitance value of the variable capacitor arrays is adjustable.
[0028] In an optional embodiment, the variable capacitor array includes multiple branches connected in parallel, each branch including a switch and a capacitor connected in series, and a capacitor is connected in series between two designated branches.
[0029] The beneficial effects of this invention are as follows:
[0030] This invention is not only insensitive to power supply noise, effectively suppressing clock jitter caused by power supply noise and improving the accuracy of digital phase-locked loops, but also does not introduce additional parasitic capacitance in the main signal path, does not reduce the speed of the oscillator, and can maintain stable performance over a wide range of temperature and process angle variations, exhibiting excellent robustness. Attached Figure Description
[0031] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.
[0032] Figure 1 Several differential delay unit circuits commonly used in the prior art are shown.
[0033] Figure 2 The delay unit circuit of a power supply noise-insensitive differential ring oscillator in the prior art is shown.
[0034] Figure 3 The delay unit circuit of a power supply noise-insensitive differential ring oscillator in the prior art is shown.
[0035] Figure 4 A schematic diagram of a robust numerically controlled ring oscillator integrated circuit according to an embodiment of the present invention is shown.
[0036] Figure 5 A circuit structure for a numerically controlled capacitor in a robust numerically controlled ring oscillator according to an embodiment of the present invention is shown. Detailed Implementation
[0037] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and drawings. However, it should be noted that the concept of the technical solution of the present invention can be implemented in many different forms and is not limited to the specific embodiments described herein. The accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0038] Reference Figure 4 An embodiment of the present invention provides a differential delay unit, comprising:
[0039] latch;
[0040] The non-inverting input is connected to the inverter and then to the first terminal of the latch.
[0041] The inverting input is connected to the second terminal of the latch;
[0042] A first resistor array adjustment circuit is connected between the third terminal of the latch and the voltage source. The first resistor array adjustment circuit includes multiple first switches connected in parallel and resistors connected between two adjacent first switches. By controlling the opening and closing of one or more of the first switches, the number of resistors through which current flows can be adjusted.
[0043] The second resistor array adjustment circuit is connected between the fourth terminal of the latch and the reference ground. The second resistor array adjustment circuit includes a plurality of parallel second switches and a resistor connected between two adjacent second switches. By controlling the opening and closing of one or more of the second switches, the number of resistors through which the current flows can be adjusted.
[0044] The first resistor array adjustment circuit and the second resistor array adjustment circuit are used to adjust the power supply voltage sensitivity of the latch.
[0045] Specifically, the resistors in the first resistor array adjustment circuit and the resistors in the second resistor array adjustment circuit both have positive temperature coefficients. A first compensation resistor unit with a positive temperature coefficient is also connected between the first terminal of the latch and the non-inverting input inverter. A second compensation resistor unit with a positive temperature coefficient is also connected between the second terminal of the latch and the inverting input inverter.
[0046] The first compensation resistor unit includes a first resistor R connected in series. C1 Second resistor R C2 The first resistor R C1 The first resistor R is located near the non-inverting input of the inverter. C1 The temperature coefficient is the second resistor R C2 The temperature coefficient is 15-20 times; the second compensation resistor unit includes a third resistor R connected in series. C1 and the fourth resistor R C2 The fourth resistor is located near the inverting input of the inverter, and the third resistor R C1 The temperature coefficient is the fourth resistor R C2 The temperature coefficient is 15-20 times that of the second and fourth resistors. The temperature coefficient of the resistors in the first resistor array adjustment circuit is 7-9 times that of the second and fourth resistors, and the temperature coefficient of the resistors in the second resistor array adjustment circuit is the same as that of the second and fourth resistors. In other embodiments, the multiple of the temperature coefficient of each resistor can be flexibly set as needed.
[0047] In this embodiment, the non-inverting input inverter includes: a first PMOS transistor MP1 and a first NMOS transistor MN1, wherein the source of the first PMOS transistor MP1 is connected to the voltage source VDD, the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1 and connected to the first terminal of the latch, the source of the first NMOS transistor MN1 is connected to the reference ground, and the gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected together; the inverting input inverter includes: a second PMOS transistor MP2 and a second NMOS transistor MN2, wherein the source of the second PMOS transistor MP2 is connected to the voltage source VDD, the drain of the second PMOS transistor MP1 is connected to the drain of the second NMOS transistor MN2 and connected to the second terminal of the latch, the source of the second NMOS transistor MN2 is connected to the reference ground, and the gates of the second PMOS transistor MP1 and the second NMOS transistor MN2 are connected together.
[0048] In this embodiment, the latch includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. The gate of the third PMOS transistor MP3 is connected to the gate of the third NMOS transistor MN3, and the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, and also connected to the drain of the first PMOS transistor MP1 and the drain of the first NMOS transistor MN1. The source of the third PMOS transistor MP3 is connected to the first resistor array adjustment circuit. The source of the third NMOS transistor MN3 is connected to the second resistor array adjustment circuit. The gate of the fourth PMOS transistor MP4 is connected to the gate of the fourth NMOS transistor MN4, and the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, and also connected to the drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2. The source of the fourth PMOS transistor MP4 is connected to the first resistor array adjustment circuit. The source of the fourth NMOS transistor MN4 is connected to the second resistor array adjustment circuit.
[0049] In this embodiment, the first resistor array adjustment circuit is divided into a first adjustment unit and a second adjustment unit. The first adjustment unit is connected between the source of the third PMOS transistor MP3 and the voltage source VDD, and the second adjustment unit is connected between the source of the fourth PMOS transistor PM3 and the voltage source VDD. The second resistor array adjustment circuit is divided into a third adjustment unit and a fourth adjustment unit. The third adjustment unit is connected between the source of the third NMOS transistor MN3 and the reference ground, and the fourth adjustment unit is connected between the source of the fourth NMOS transistor MN4 and the reference ground.
[0050] More specifically, the differential delay unit in this embodiment adopts a completely symmetrical circuit structure. MP1 and MN1 form a non-inverting input inverter, MP2 and MN2 form an inverting input inverter, and MP3, MN3, MP4, and MN4 form a latch structure; the first resistor R C1 Second resistor R C2 The resistor array is connected in series between the inverter and the latch to reduce the inverter's sensitivity to the power supply voltage. The second resistor array adjustment circuit is divided into a third adjustment unit and a fourth adjustment unit, each of which includes 8 resistors R. A and 8 NMOS switches BN <0> To BN <7> This constitutes a coarse adjustment circuit. The first resistor array adjustment circuit is divided into a first adjustment unit and a second adjustment unit. Both the first adjustment unit and the second adjustment unit include 8 resistors R. B and 8 PMOS switches BP <0> To BP <7> This constitutes a fine-tuning circuit. By adjusting the upper and lower resistor arrays, the power supply voltage sensitivity of the latch can be adjusted, so that the latch's sensitivity, which is negatively correlated with the power supply voltage, compensates for the inverter's sensitivity, which is positively correlated with the power supply voltage. This makes the entire differential delay circuit insensitive to power supply noise. To achieve good temperature stability, the temperature coefficients of the inverter path and the latch path need to compensate for each other. The compensation resistor unit uses two resistors R with different positive temperature coefficients. C1 and R C2 The inverter is configured to adjust the temperature drift coefficient corresponding to the equivalent power supply voltage sensitivity, and also employs a resistor R with a specific positive temperature coefficient. A and R B As a tuning resistor, this can be achieved by appropriately selecting R. C1 R C2 R A and R B The value of can match the positive temperature drift coefficient corresponding to the equivalent power supply voltage sensitivity of the inverter with the negative temperature drift coefficient of the power supply voltage sensitivity of the latch, so that the ring oscillator has stable power supply noise insensitivity characteristics.
[0051] In this embodiment, the differential delay unit further includes a first decoder and a second decoder. The first decoder is connected to the first resistor array adjustment circuit, and the second decoder is connected to the second resistor array adjustment circuit. The first decoder is used to control the opening and closing of the switches in the first resistor array adjustment circuit, and the second decoder is used to control the opening and closing of the switches in the second resistor array adjustment circuit. Both the first and second decoders are 3-to-8 decoders. The two 3-to-8 decoders are used to convert two sets of 3-bit binary code values into two sets of 8-bit one-hot codes to control the first resistor array adjustment circuit and the second resistor array adjustment circuit in the delay unit, respectively. Each of the two resistor arrays has 8 control switches, each controlled by a 3-bit binary code, requiring only 6 bits of binary code to achieve the adjustment function.
[0052] This embodiment is not only insensitive to power supply noise, effectively suppressing clock jitter caused by power supply noise and improving the accuracy of the digital phase-locked loop, but also does not introduce additional parasitic capacitance in the main signal path, does not reduce the speed of the oscillator, and can maintain stable performance over a wide range of temperature and process angle variations, exhibiting excellent robustness.
[0053] Another embodiment of the present invention provides a robust numerically controlled ring oscillator integrated circuit, including at least two of the above-mentioned differential delay units, and also including a plurality of variable capacitor arrays, wherein the variable capacitor arrays are connected between two adjacent differential delay units, and the overall capacitance value of the variable capacitor arrays is adjustable.
[0054] Reference Figure 5 In one specific example, the variable capacitor array includes multiple branches connected in parallel, each branch including a switch and a capacitor connected in series, and a capacitor is connected in series between two designated branches.
[0055] This invention incorporates a variable resistor array as a power supply voltage sensitivity adjustment circuit along the latch's power supply path. When adjusting the power supply noise sensitivity of the ring oscillator, the adjustment circuit does not introduce additional parasitic capacitance into the main signal path, thus preventing a decrease in the ring oscillator's frequency. This adjustment circuit requires only 6 bits of binary code to achieve high-precision adjustment, simplifying the control circuit.
[0056] The ring oscillator's power supply voltage sensitivity can approach zero temperature coefficient, maintaining excellent power supply voltage insensitivity characteristics over a wide range of ambient temperature variations, effectively enhancing its robustness. This also allows the tuning circuit to adjust the power supply voltage sensitivity in a single fuse adjustment, eliminating the need for real-time adjustments to counteract the effects of temperature changes, thus facilitating the rapid operation of the ring oscillator.
[0057] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A differential delay unit, characterized in that, include: latch; The non-inverting input is connected to the inverter and then to the first terminal of the latch. The inverting input is connected to the second terminal of the latch; A first resistor array adjustment circuit is connected between the third terminal of the latch and the voltage source. The first resistor array adjustment circuit includes multiple first switches connected in parallel and resistors connected between two adjacent first switches. By controlling the opening and closing of one or more of the first switches, the number of resistors through which current flows can be adjusted. The second resistor array adjustment circuit is connected between the fourth terminal of the latch and the reference ground. The second resistor array adjustment circuit includes a plurality of parallel second switches and a resistor connected between two adjacent second switches. By controlling the opening and closing of one or more of the second switches, the number of resistors through which the current flows can be adjusted. The first resistor array adjustment circuit and the second resistor array adjustment circuit are used to adjust the power supply voltage sensitivity of the latch; The non-inverting input inverter includes: A first PMOS transistor and a first NMOS transistor, wherein the source of the first PMOS transistor is connected to the voltage source, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and connected to the first terminal of the latch, the source of the first NMOS transistor is connected to the reference ground, and the gates of the first PMOS transistor and the first NMOS transistor are connected. The inverter input inverter includes: A second PMOS transistor and a second NMOS transistor, wherein the source of the second PMOS transistor is connected to the voltage source, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor and connected to the second terminal of the latch, the source of the second NMOS transistor is connected to the reference ground, and the gates of the second PMOS transistor and the second NMOS transistor are connected. The latch includes: A third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, and a fourth NMOS transistor are connected as follows: the gate of the third PMOS transistor is connected to the gate of the third NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, and is also connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor; the source of the third PMOS transistor is connected to the first resistor array adjustment circuit; the source of the third NMOS transistor is connected to the second resistor array adjustment circuit; the gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, and is also connected to the drain of the second PMOS transistor and the drain of the second NMOS transistor; the source of the fourth PMOS transistor is connected to the first resistor array adjustment circuit; and the source of the fourth NMOS transistor is connected to the second resistor array adjustment circuit.
2. The differential delay unit as described in claim 1, characterized in that, The resistors in the first resistor array adjustment circuit and the resistors in the second resistor array adjustment circuit both have positive temperature coefficients. A first compensation resistor unit with a positive temperature coefficient is also connected between the first terminal of the latch and the non-inverting input inverter. A second compensation resistor unit with a positive temperature coefficient is also connected between the second terminal of the latch and the inverting input inverter.
3. The differential delay unit as described in claim 2, characterized in that, The first compensation resistor unit includes a first resistor and a second resistor connected in series, wherein the first resistor is input to the inverter near the non-inverting terminal, and the temperature coefficient of the first resistor is 15-20 times that of the second resistor; the second compensation resistor unit includes a third resistor and a fourth resistor connected in series, wherein the fourth resistor is input to the inverter near the inverting terminal, and the temperature coefficient of the third resistor is 15-20 times that of the fourth resistor.
4. The differential delay unit as described in claim 3, characterized in that, The temperature coefficient of the resistor in the first resistor array adjustment circuit is 7-9 times that of the second resistor and the fourth resistor, and the temperature coefficient of the resistor in the second resistor array adjustment circuit is the same as that of the second resistor and the fourth resistor.
5. The differential delay unit as described in claim 1, characterized in that, The first resistor array adjustment circuit is divided into a first adjustment unit and a second adjustment unit. The first adjustment unit is connected between the source of the third PMOS transistor and the voltage source, and the second adjustment unit is connected between the source of the fourth PMOS transistor and the voltage source. The second resistor array adjustment circuit is divided into a third adjustment unit and a fourth adjustment unit. The third adjustment unit is connected between the source of the third NMOS transistor and the reference ground, and the fourth adjustment unit is connected between the source of the fourth NMOS transistor and the reference ground.
6. The differential delay unit as described in claim 1, characterized in that, The differential delay unit further includes a first decoder and a second decoder. The first decoder is connected to the first resistor array adjustment circuit, and the second decoder is connected to the second resistor array adjustment circuit. The first decoder is used to control the opening and closing of the switches in the first resistor array adjustment circuit, and the second decoder is used to control the opening and closing of the switches in the second resistor array adjustment circuit.
7. A robust numerically controlled ring oscillator integrated circuit, characterized in that, It includes at least two differential delay units as described in any one of claims 1-6, and further includes a plurality of variable capacitor arrays connected between two adjacent differential delay units, wherein the overall capacitance value of the variable capacitor arrays is adjustable.
8. The robust numerically controlled ring oscillator integrated circuit as described in claim 7, characterized in that, The variable capacitor array includes multiple branches connected in parallel, each branch including a switch and a capacitor connected in series, and a capacitor is connected in series between two designated branches.