A reset circuit

Abstract

An embodiment of the present invention provides a reset circuit, which includes a power supply, a primary power supply module, a secondary power supply module, a reset module, and a power-consuming module. When a fault occurs in the secondary power supply module, a first level signal is output to the input end of the reset module through a fault error reporting output end, and within a preset time, the reset module outputs a second level signal to the enable end of the primary power supply module to turn off the output of the first voltage and stop power supply to the secondary power supply module. After exceeding the preset time, the reset module outputs a third level signal to the enable end of the primary power supply module to turn on the output of the first voltage. This is to achieve power supply interruption during a fault, resume power supply after reset, and the reset delay time can be flexibly adjusted, improving the reliability and flexibility of the reset circuit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of circuit technologies, and in particular, to a reset circuit. Background Art

[0002] Common reset chips mainly rely on monitoring voltage drops in the circuit to trigger reset. When the power supply of the reset chip itself fails (no output), the reset chip itself cannot work, that is, it cannot complete the reset of the system.

[0003] In addition, common reset chips are prone to trigger reset during power fluctuations and cannot set a long-delay reset (more than 5S), that is, the reset delay time cannot be flexibly set. Summary of the Invention

[0004] The embodiments of the present invention provide a reset circuit, which improves the reliability and flexibility of the reset circuit.

[0005] The embodiments of the present invention provide a reset circuit, including a power supply, a primary power module, a secondary power module, a reset module, and a power-consuming module;

[0006] The output end of the power supply is electrically connected to the input end of the primary power module, the output end of the primary power module is electrically connected to the input end of the secondary power module, the primary power module is used to convert the power supply voltage output by the power supply into a first voltage and output it to the secondary power module, the secondary power module includes a plurality of voltage output ends, and the plurality of voltage output ends are electrically connected to the power-consuming module;

[0007] The secondary power module includes a fault reporting output end, the fault reporting output end is electrically connected to the input end of the reset module, the output end of the reset module is electrically connected to the enable end of the primary power module. When the secondary power module detects a fault, the fault reporting output end outputs a first level signal to the input end of the reset module. According to the first level signal, the reset module outputs a second level signal to the enable end of the primary power module within a preset time to control the primary power module to turn off the output of the first voltage, and outputs a third level signal to the enable end of the primary power module after exceeding the preset time to control the primary power module to turn on the output of the first voltage.

[0008] Optionally, it further includes an AND gate circuit. The power-consuming module includes a control unit. The fault reporting output end is electrically connected to the first input end of the AND gate circuit, the general input / output port of the control unit is electrically connected to the second input end of the AND gate circuit, and the output end of the AND gate circuit is electrically connected to the input end of the reset module.

[0009] Optionally, the control unit is configured to output a fourth-level signal through the general-purpose input / output port during active reset.

[0010] Optionally, the control unit includes a microcontroller unit (MCU).

[0011] Optionally, the reset module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first diode, a second diode, a capacitor, a triode, and a MOS transistor;

[0012] The first end of the first resistor, the first end of the second resistor, and the cathode of the first diode are all electrically connected to the output end of the primary power supply module. The second end of the first resistor and the first end of the fifth resistor are both electrically connected to the input end of the reset module. The second end of the fifth resistor is electrically connected to the base of the triode. The second end of the second resistor, the cathode of the second diode, and the first end of the fourth resistor are all electrically connected to the collector of the triode. The emitter of the triode is grounded. The anode of the first diode and the anode of the second diode are both electrically connected to the first end of the third resistor. The second end of the third resistor, the second end of the fourth resistor, and the first end of the capacitor are all electrically connected to the gate of the MOS transistor. The second end of the capacitor and the source of the MOS transistor are both grounded. The drain of the MOS transistor is electrically connected to the enable end of the primary power supply module.

[0013] Optionally, it further includes a sixth resistor. The first end of the sixth resistor is connected to the output end of the power supply, and the second end of the sixth resistor is electrically connected to the enable end of the primary power supply module.

[0014] Optionally, the voltages of the first-level signal and the second-level signal are both less than the voltage of the third-level signal.

[0015] Optionally, the secondary power supply module includes a power management integrated circuit (PMIC).

[0016] Optionally, the faults detected by the secondary power supply module include at least one of input overvoltage, input undervoltage, or output short circuit.

[0017] Optionally, the preset time is greater than or equal to 100 ms and less than or equal to 100 s.

[0018] The reset circuit provided by the embodiment of the present invention, when a failure occurs in the secondary power supply module, outputs a first-level signal to the input end of the reset module through the fault error reporting output end, and within a preset time, the reset module outputs a second-level signal to the enable end of the primary power supply module to turn off the output of the first voltage and stop supplying power to the secondary power supply module. After exceeding the preset time, the reset module outputs a third-level signal to the enable end of the primary power supply module to turn on the output of the first voltage. To achieve power supply interruption during a fault, resume power supply after reset, and the reset delay time can be flexibly adjusted, improving the reliability and flexibility of the reset circuit.

[0019] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a schematic circuit diagram of a reset circuit provided by an embodiment of the present invention;

[0022] Figure 2 It is a schematic circuit diagram of another reset circuit provided by an embodiment of the present invention;

[0023] Figure 3 It is a schematic circuit diagram of a reset module provided by an embodiment of the present invention;

[0024] Figure 4 It is a schematic circuit diagram of yet another reset circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] In order to enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0027] Figure 1 The circuit schematic diagram of a reset circuit provided by an embodiment of the present invention is as Figure 1 shown. The reset circuit includes a power supply 500, a primary power module 100, a secondary power module 200, a reset module 300 and a power-consuming module 400. The output terminal VB of the power supply 500 is electrically connected to the input terminal of the primary power module 100, and the output terminal of the primary power module 100 is electrically connected to the input terminal of the secondary power module 200. The primary power module 100 is used to convert the power supply voltage output by the power supply 500 into a first voltage and output it to the secondary power module 200. The secondary power module 200 includes a plurality of voltage output terminals OUT1, OUT2,..., OUTN, and the plurality of voltage output terminals are electrically connected to the power-consuming module 400. The secondary power module 200 includes a fault reporting output terminal PGOOD, and the fault reporting output terminal PGOOD is electrically connected to the input terminal of the reset module 300. The output terminal of the reset module 300 is electrically connected to the enable terminal EN of the primary power module 100. When the secondary power module 200 detects a fault, the fault reporting output terminal PGOOD outputs a first level signal to the input terminal of the reset module 300. The reset module 300, according to the first level signal, outputs a second level signal to the enable terminal of the primary power module 100 within a preset time to control the primary power module 100 to turn off the output of the first voltage, and outputs a third level signal to the enable terminal of the primary power module 100 after exceeding the preset time to control the primary power module 100 to turn on the output of the first voltage.

[0028] Among them, the power supply 500 is used to supply power to electrical equipment or other power equipment electrically connected to the output terminal VB of the power supply 500. The primary power supply module 100 may include a voltage conversion circuit such as a boost circuit or a buck circuit to convert the power supply voltage output by the power supply 500 into a first voltage and output it to the secondary power supply module 200. The secondary power supply module 200 may include multiple voltage conversion circuits such as multiple boost circuits or multiple buck circuits to convert the first voltage output by the primary power supply module 100 into multiple identical or different voltages, and then output them to the electrical module 400 through multiple voltage output terminals OUT1, OUT2, …, OUTN. The power supply 500 may be a vehicle-mounted 14V power supply. The primary power supply module 100 may convert the 14V voltage into 3.3V for output. The multiple voltage output terminals of the secondary power supply module 200 may output voltages of different levels such as 3.3V / 1.8V / 1.1V / 0.75V to supply the subsequent SoC, peripheral modules, etc.

[0029] It can be understood that the preset time can be set as needed, and the embodiments of the present invention do not make specific limitations. Optionally, the preset time is greater than or equal to 100 ms and less than or equal to 100 s. In the primary power supply module 100, when the second level signal received by the enable terminal is high, the output of the first voltage is turned off. When the third electrical signal received by the enable terminal is low, the output of the first voltage is turned on. It can also be that when the second level signal received by the enable terminal is low, the output of the first voltage is turned off, and when the third electrical signal received by the enable terminal is high, the output of the first voltage is turned on. The embodiments of the present invention do not make limitations on this.

[0030] Specifically, when a fault situation such as undervoltage or overvoltage occurs and is detected in the secondary power supply module 200, the fault error output terminal PGOOD in the secondary power supply module 200 will output a first level signal to the input terminal of the reset module 300. Within the preset time, the reset module 300 outputs a second level signal to the enable terminal of the primary power supply module 100 to turn off the output of the first voltage and stop supplying power to the secondary power supply module 200. The secondary power supply module 200 can recover from the fault state to the normal state within this preset time. After exceeding the preset time, the reset module 300 outputs a third level signal to the enable terminal of the primary power supply module 100 to turn on the output of the first voltage and continue to supply power to the secondary power supply module 200.

[0031] The reset circuit provided in this embodiment, when a fault occurs in the secondary power supply module, outputs a first level signal to the input end of the reset module through the fault error reporting output end, and within a preset time, the reset module outputs a second level signal to the enable end of the primary power supply module to turn off the output of the first voltage and stop supplying power to the secondary power supply module. After exceeding the preset time, the reset module outputs a third level signal to the enable end of the primary power supply module to turn on the output of the first voltage. This is to achieve power supply interruption during a fault, resume power supply after reset, and can flexibly adjust the reset delay time, improving the reliability and flexibility of the reset circuit.

[0032] Based on the above embodiment, Figure 2 is a circuit schematic diagram of another reset circuit provided by an embodiment of the present invention. As Figure 2 shown, the reset circuit further includes an AND gate circuit 600. The power-consuming module 400 includes a control unit 401. The fault error reporting output end PGOOD is electrically connected to the first input end A1 of the AND gate circuit 600. The general-purpose input / output port GPIO of the control unit 401 is electrically connected to the second input end A2 of the AND gate circuit 600. The output end A3 of the AND gate circuit 600 is electrically connected to the input end of the reset module 300.

[0033] Among them, when both the first input end A1 and the second input end A2 of the AND gate circuit 600 input high levels, the output end A3 of the AND gate circuit 600 outputs a high level. When at least one of the first input end A1 and the second input end A2 of the AND gate circuit 600 inputs a low level, that is, the first input end A1 of the AND gate circuit 600 inputs a high level and the second input end A2 inputs a low level, or the first input end A1 of the AND gate circuit 600 inputs a low level and the second input end A2 inputs a high level, or both the first input end A1 and the second input end A2 of the AND gate circuit 600 input low levels, the output end A3 of the AND gate circuit 600 outputs a low level. The high level is greater than the low level. Exemplarily, the high level is 1 and the low level is 0. The control unit 401 is used to control the working state of the power-consuming module 400, etc. Optionally, the control unit 401 includes a micro control unit MCU.

[0034] Specifically, when a fault occurs in the secondary power supply module 200 resulting in the secondary power supply module 200 closing multiple voltage output ends, both the power-consuming module 400 and the control unit 401 have no power supply and cannot output electrical signals. At this time, the first input end A1 of the AND gate circuit 600 receives a first level signal, and the second input end A2 has no electrical signal input. The output end A3 of the AND gate circuit 600 inputs an electrical signal to the input end of the reset module 300, and controls the primary power supply module 100 to output the first voltage to the secondary power supply module 200 according to the delay control logic inside the reset module 300.

[0035] Correspondingly, when the secondary power supply module 200 and the power-consuming module 400 are operating normally, the fault error reporting output terminal PGOOD in the secondary power supply module 200 and the general-purpose input / output port GPIO in the control unit 401 respectively input high-level signals to the first input terminal A1 and the second input terminal A2 of the AND gate circuit 600. The output terminal A3 of the AND gate circuit 600 inputs a high-level signal to the input terminal of the reset module 300, and the reset module 300 has no electrical signal output to the secondary power supply module 200.

[0036] In an optional embodiment, the control unit 401 is configured to output a fourth-level signal through the general-purpose input / output port GPIO during active reset.

[0037] Specifically, when the secondary power supply module 200 is normally powered and the power-consuming module 400 needs to actively reset the secondary power supply module 200, the general-purpose input / output port GPIO of the control unit 401 outputs a fourth-level signal (low level) to the second input terminal A2 of the AND gate circuit 600. Regardless of whether there is an electrical signal input to the first input terminal A1, the AND gate circuit 600 outputs a corresponding electrical signal to the reset module 300. According to the reset logic inside the reset module 300, the primary power supply module 100 outputs a first voltage to the secondary power supply module 200 to enable the secondary power supply module 200 to operate normally after reset.

[0038] Based on the above embodiments, Figure 3 A circuit schematic diagram of a reset module provided by an embodiment of the present invention is shown in Figure 3 As shown, the reset module 300 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first diode D1, a second diode D2, a capacitor C1, a triode Q1, and a MOS transistor Q2.

[0039] Referring to Figure 1 and Figure 3 , the first end of the first resistor R1, the first end of the second resistor R2, and the cathode of the first diode D1 are all electrically connected to the output terminal of the primary power supply module 100. The second end of the first resistor R1 and the first end of the fifth resistor R5 are both electrically connected to the input terminal of the reset module 300. The second end of the fifth resistor R5 is electrically connected to the base of the triode Q1. The second end of the second resistor R2, the cathode of the second diode D2, and the first end of the fourth resistor R4 are all electrically connected to the collector of the triode Q1. The emitter of the triode Q1 is grounded. The anode of the first diode D1 and the anode of the second diode D2 are both electrically connected to the first end of the third resistor R3. The second end of the third resistor R3, the second end of the fourth resistor R4, and the first end of the capacitor C1 are all electrically connected to the gate of the MOS transistor Q3. The second end of the capacitor C1 and the source of the MOS transistor Q3 are both grounded. The drain of the MOS transistor Q3 is electrically connected to the enable terminal of the primary power supply module 100.

[0040] Among them, the preset time is related to the fourth resistor R4 and the capacitor C1, and the preset time can be adjusted by adjusting the parameter information of the fourth resistor R4 and the capacitor C1. The specific parameters of the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the capacitor C1 can be set according to actual needs, and the embodiments of the present invention do not make specific limitations on this premise as long as the functions of the embodiments of the present invention are satisfied.

[0041] Specifically, the first end of the first resistor R1, the first end of the second resistor R2 and the negative electrode of the first diode D1 are all electrically connected to the output end of the primary power supply module 100. The reset module 300 receives the electric energy output by the primary power supply module 100 to enable the reset module 300 to work properly. When the fault error output terminal PGOOD of the secondary power supply module 200 outputs a first level signal (low level), at this time, the triode Q1 is not turned on, and the primary power supply module 100 charges the capacitor C1 through the second resistor R2 and the fourth resistor R4. The time when the voltage across the capacitor C1 is charged to a value that can drive the MOS transistor Q2 to turn on is the preset time. After the MOS transistor Q2 is turned on, it outputs a second level signal to the enable terminal of the primary power supply module 100 to control the primary power supply module 100 to turn off the output of the first voltage and stop supplying power to the secondary power supply module 200. Further, after exceeding the preset time, the capacitor C1 discharges through the third resistor R3 and the second diode D2, and the MOS transistor Q2 is turned off, and no electrical signal is output.

[0042] In an alternative embodiment, Figure 4 is a circuit schematic diagram of another reset circuit provided by the embodiment of the present invention, as Figure 4 shown. The reset circuit further includes a sixth resistor R6. The first end of the sixth resistor R6 is connected to the output end of the power supply 500, and the second end of the sixth resistor R6 is electrically connected to the enable terminal of the primary power supply module 100.

[0043] Specifically, after exceeding the preset time, the capacitor C1 discharges through the third resistor R3 and the second diode D2, the MOS transistor Q2 is turned off, and no electrical signal is output. At this time, the power supply 500 divides the voltage through the sixth resistor R6 and outputs a high level signal to the enable terminal of the primary power supply module 100 to control the primary power supply module 100 to turn on the output of the first voltage and achieve reset.

[0044] The technical solution of the embodiment of the present invention uses the RC (R - resistor, C - capacitor) charging and discharging principle, combines the very high gate input impedance (above 1 M ohm) of the MOSFET field - effect transistor and the unidirectional conduction characteristic of the diode, and designs a delay reset circuit implemented by a pure hardware circuit. The key steps are the precise configuration of the RC charging and discharging time parameters, and the trigger source of the circuit is the error signal output by the monitored circuit (secondary power supply module). Different from common voltage monitoring reset chips / watchdog monitoring reset chips, this circuit solution can provide a mechanism to reset the power supply of the reset input terminal after the system freezes / crashes, enabling the system to achieve the function of power - on reset and restarting the system. And it is implemented by a pure hardware circuit, which is more stable and reliable.

[0045] Optionally, the voltages of the first - level signal and the second - level signal are both less than the voltage of the third - level signal.

[0046] Exemplarily, the voltages of the first - level signal and the second - level signal are both low level 0, and the voltage of the third - level signal is high level 1. When the fault error output terminal PGOOD of the secondary power supply module 200 outputs the first - level signal 0, at this time, the triode Q1 is not conducting, and the primary power supply module 100 charges the capacitor C1 through the second resistor R2 and the fourth resistor R4. When the voltage across the capacitor C1 is charged to a level that can drive the MOS transistor Q2 to conduct, the MOS transistor Q2 outputs the second - level signal 0 to the enable terminal of the primary power supply module 100, turning off the output of the first voltage and stopping the power supply to the secondary power supply module 200. Further, after exceeding the preset time, the capacitor C1 discharges through the third resistor R3 and the second diode D2, the MOS transistor Q2 is turned off, and no electrical signal is output. At this time, the power supply 500 divides the voltage through the sixth resistor R6 and outputs the third - level signal 1 to the enable terminal of the primary power supply module 100, turning on the output of the first voltage to achieve reset.

[0047] Optionally, continue to refer to Figure 1 , the secondary power supply module 200 includes a power management integrated circuit PMIC.

[0048] Among them, the power management integrated circuit PMIC has the characteristics of configurability, programmability, high integration, and high efficiency, which can improve the integration of the secondary power supply module 200 and reduce the volume of the secondary power supply module 200, etc.

[0049] In an optional embodiment, the faults detected by the secondary power supply module 200 include at least one of input over - voltage, input under - voltage, or output short - circuit.

[0050] Specifically, if the secondary power supply module 200 experiences input overvoltage, input undervoltage, or output short circuit, the secondary power supply module 200 needs to be able to detect such a fault, so that the fault error output terminal PGOOD of the secondary power supply module 200 outputs a corresponding fault signal, in order to perform corresponding operations on the reset circuit subsequently, preventing the secondary power supply module 200 from operating abnormally or damaging the secondary power supply module 200.

[0051] The above specific implementation manners do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A reset circuit, characterized in that, It includes a power supply, a primary power supply module, a secondary power supply module, a reset module, and a power-consuming module; The output terminal of the power supply is electrically connected to the input terminal of the primary power supply module. The output terminal of the primary power supply module is electrically connected to the input terminal of the secondary power supply module. The primary power supply module is used to convert the power supply voltage output by the power supply into a first voltage and output it to the secondary power supply module. The secondary power supply module includes a plurality of voltage output terminals, and the plurality of voltage output terminals are electrically connected to the power-consuming module; The secondary power supply module includes a fault reporting output terminal. The fault reporting output terminal is electrically connected to the input terminal of the reset module. The output terminal of the reset module is electrically connected to the enable terminal of the primary power supply module. When the secondary power supply module detects a fault, the fault reporting output terminal outputs a first level signal to the input terminal of the reset module. The reset module, according to the first level signal, outputs a second level signal to the enable terminal of the primary power supply module within a preset time to control the primary power supply module to turn off the output of the first voltage, and outputs a third level signal to the enable terminal of the primary power supply module after exceeding the preset time to control the primary power supply module to turn on the output of the first voltage.

2. The reset circuit according to claim 1, wherein It further includes an AND gate circuit. The power-consuming module includes a control unit. The fault reporting output terminal is electrically connected to the first input terminal of the AND gate circuit. The general-purpose input / output port of the control unit is electrically connected to the second input terminal of the AND gate circuit. The output terminal of the AND gate circuit is electrically connected to the input terminal of the reset module.

3. The reset circuit according to claim 2, wherein The control unit is used to output a fourth level signal through the general-purpose input / output port during active reset.

4. The reset circuit according to claim 2, wherein The control unit includes a microcontroller unit (MCU).

5. The reset circuit according to claim 1, wherein The reset module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first diode, a second diode, a capacitor, a triode, and a MOS transistor; The first end of the first resistor, the first end of the second resistor, and the negative electrode of the first diode are all electrically connected to the output terminal of the primary power supply module. The second end of the first resistor and the first end of the fifth resistor are both electrically connected to the input terminal of the reset module. The second end of the fifth resistor is electrically connected to the base of the triode. The second end of the second resistor, the negative electrode of the second diode, and the first end of the fourth resistor are all electrically connected to the collector of the triode. The emitter of the triode is grounded. The positive electrode of the first diode and the positive electrode of the second diode are both electrically connected to the first end of the third resistor. The second end of the third resistor, the second end of the fourth resistor, and the first end of the capacitor are all electrically connected to the gate of the MOS transistor. The second end of the capacitor and the source of the MOS transistor are both grounded. The drain of the MOS transistor is electrically connected to the enable terminal of the primary power supply module.

6. The reset circuit according to claim 5, wherein It further includes a sixth resistor. The first end of the sixth resistor is connected to the output terminal of the power supply, and the second end of the sixth resistor is connected to the enable terminal of the primary power supply module.

7. The reset circuit according to claim 5, characterized in that, The voltages of both the first level signal and the second level signal are less than the voltage of the third level signal.

8. The reset circuit according to claim 1, wherein The secondary power supply module includes a power management integrated circuit PMIC.

9. The reset circuit according to claim 8, wherein The faults detected by the secondary power supply module include at least one of input overvoltage, input undervoltage, or output short circuit.

10. The reset circuit according to claim 1, characterized in that, The preset time is greater than or equal to 100 ms and less than or equal to 100 s.

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