A frame synchronization device and method

Abstract

The present application discloses a frame synchronization device and method. First, a parallel code stream is delayed and intercepted to generate a data stream signal, and a sliding convolution is performed on the data stream signal to obtain an autocorrelation peak. At the same time, the data stream signal is delayed and the delayed data stream signal is output to ensure the synchronization between the data stream signal and the autocorrelation peak. Then, the position of the frame header in the parallel code stream is judged by the autocorrelation peak to intercept the delayed data stream signal to obtain intercepted data information. Finally, phase ambiguity correction is performed on the intercepted data information based on the phase ambiguity information calculated from the autocorrelation peak. The frame header position is determined by the autocorrelation peak to ensure frame synchronization accuracy. Phase compensation is performed based on the phase ambiguity information calculated from the autocorrelation peak, thereby solving the phase ambiguity problem existing in the digital receiver system and further improving the frame synchronization accuracy.

Description

Technical Field

[0001] The present invention relates to the field of digital signal processing, and in particular to a frame synchronization device and method. Background Art

[0002] With the advancement of communications and computer technology, the demand for network data transmission bandwidth is increasing, and digital communication systems are becoming more and more widely used. Digital communication systems require functions such as real-time signal synchronization, gain compensation, carrier synchronization, and information encoding to meet diverse requirements. In digital communication systems, frame synchronization is an essential task for receivers and provides a prerequisite for channel decoding. Frame synchronization refers to the receiver's ability to distinguish the start and end of a frame in the received data stream. This can be achieved through matching calculations based on the autocorrelation of the received data stream or the cross-correlation between the received data stream and the local signal.

[0003] The accuracy of frame synchronization directly impacts channel decoding performance. Currently, there are two main frame synchronization methods: serial and parallel. Serial frame synchronization primarily targets low-speed transmission. It searches for a frame header in the serial bitstream and uses a shift register to buffer data over multiple cycles. Comparisons are made in the shift registers during each cycle until a frame header is detected. The bitstream is then output in parallel for synchronization and subsequent processing. However, due to the increasing demands on digital communication rates, existing serial frame synchronization methods cannot meet the transmission requirements of high-speed communications.

[0004] The existing parallel frame synchronization method for the transmission field is to first convert the serial code stream into a parallel code stream, and then use a serial processing method to search for the frame header of the parallel code stream. Subsequent synchronization processing can only be performed after the correct frame header is found. It can be seen that the above method not only consumes a lot of time, but also cannot meet the transmission requirements of high-speed applications. Since the position of the frame header is not fixed, if the exact position of the frame header cannot be found, it will also cause calculation errors, thereby affecting the accuracy of frame synchronization. Currently, a carrier synchronization algorithm based on a phase-locked loop is used to solve the problem of frame synchronization accuracy. However, due to the presence of the signal local oscillator, the signal may also have phase ambiguity, and the ambiguous phase will cause the signal to deflect by a certain angle, thereby affecting the accuracy of subsequent decoding. Therefore, how to correct the phase ambiguity and complete frame synchronization has become a problem that people in this field urgently need to solve. Summary of the Invention

[0005] The purpose of this application is to provide a frame synchronization device and method to overcome the existing technical defects, determine the frame header position by the autocorrelation peak obtained by sliding autocorrelation calculation to ensure the frame synchronization accuracy, and perform phase compensation by the fuzzy phase value calculated by the autocorrelation peak, thereby solving the phase ambiguity problem existing in the digital receiver system and further improving the frame synchronization accuracy.

[0006] The object of the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present application proposes a frame synchronization device, comprising: a signal stream processing module, an autocorrelation calculation module, a delay module, and a phase ambiguity resolution module, wherein:

[0008] The signal stream processing module is configured to delay and intercept the received M parallel code streams to generate at least one M data stream signal, and output the M data stream signal to the delay module and the autocorrelation calculation module, wherein the parallel code stream includes a data frame and a frame header corresponding to the data frame;

[0009] The autocorrelation calculation module is used to perform sliding convolution calculation on the M data stream signals to obtain M autocorrelation peaks, and send the M autocorrelation peaks to the phase ambiguity removal module, wherein the autocorrelation peaks include a real peak value peaki and an imaginary peak value peakq;

[0010] The delay module is used to delay the M data stream signals to ensure the synchronization of the M data stream signals with the M autocorrelation peaks, and output the delayed M data stream signals to the phase ambiguity resolution module;

[0011] The phase ambiguity removal module is configured to determine, based on the M autocorrelation peaks, the position of the frame header in the M parallel code streams, and intercept the delayed M data stream signals according to the frame header to obtain intercepted data information;

[0012] The phase ambiguity resolution module is further configured to calculate phase ambiguity information based on the M autocorrelation peaks, and perform phase ambiguity correction on the intercepted data information according to the phase ambiguity information.

[0013] Optionally, the data frame includes a conjugate sequence, the conjugate sequence is a synchronization sequence with an autocorrelation characteristic, the autocorrelation calculation module includes P autocorrelation calculation submodules, and the number of the autocorrelation calculation submodules is consistent with the number of paths of the data stream signal and corresponds one-to-one;

[0014] The autocorrelation calculation submodule is configured to perform complex multiplication calculation on the data stream signal and the conjugate sequence to obtain a complex multiplication result, and perform accumulation calculation on the complex multiplication result to obtain an autocorrelation value;

[0015] The autocorrelation calculation submodule is further used to separate the imaginary part and the real part of the autocorrelation value to obtain the real part peaki and the imaginary part peakq;

[0016] The calculation formula of the autocorrelation value is: Sig(p) is the data stream signal, and conj(Seq(p)) is the conjugate sequence.

[0017] Optionally, the phase ambiguity resolution module includes a threshold judgment submodule and a frame header interception submodule;

[0018] The threshold judgment submodule is used to calculate the peak energy according to the real peak value peaki and the imaginary peak value peakq, and if the peak energy is not less than the energy threshold, determine that the frame header is located at the position of the M parallel code streams;

[0019] The frame header interception submodule is used to intercept data information of a preset length from the delayed M-channel data stream signals according to the frame header;

[0020] The peak energy calculation formula is: power = peaki 2 +peakq 2 , power is the peak energy, peaki is the real peak, and peakq is the imaginary peak.

[0021] Optionally, the phase ambiguity resolution module further includes a phase ambiguity resolution submodule;

[0022] a phase ambiguity resolution submodule, configured to calculate a phase ambiguity value according to the real peak value peaki and the imaginary peak value peakq, and perform phase ambiguity correction on the intercepted data information according to a ambiguity correction formula based on the phase ambiguity value;

[0023] Wherein, the blur correction formula is: Sig_dufuzzed is the corrected signal, and Sig_out is the intercepted data information.

[0024] In a second aspect, an embodiment of the present application further proposes a frame synchronization method including:

[0025] Delaying and intercepting the received M parallel code streams to generate at least one M data stream signal;

[0026] Performing sliding convolution calculation on the M data stream signals to obtain M autocorrelation peaks, wherein the autocorrelation peaks include a real peak value peaki and an imaginary peak value peakq;

[0027] Delaying the M data stream signals to ensure synchronization between the M data stream signals and the M autocorrelation peaks;

[0028] Determining the position of the frame header in the M parallel code streams according to the M autocorrelation peaks, and intercepting the delayed M data stream signals according to the frame header to obtain intercepted data information;

[0029] Phase ambiguity information is calculated based on the M autocorrelation peaks, and phase ambiguity correction is performed on the intercepted data information according to the phase ambiguity information.

[0030] Optionally, the data frame includes a conjugate sequence, the conjugate sequence is a synchronization sequence with an autocorrelation characteristic, and the step of performing sliding convolution calculation on the M data stream signals to obtain M autocorrelation peaks includes:

[0031] Performing complex multiplication calculation on the data stream signal and the conjugate sequence to obtain a complex multiplication result, and accumulating the complex multiplication result to obtain an autocorrelation value;

[0032] Separating the imaginary part and the real part of the autocorrelation value to obtain the real part peaki and the imaginary part peakq;

[0033] The calculation formula of the autocorrelation value is: Sig(p) is the data stream signal, and conj(Seq(p)) is the conjugate sequence.

[0034] Optionally, the step of determining, based on the M autocorrelation peaks, the position of the frame header in the M parallel code streams, and intercepting the delayed M data stream signals according to the frame header to obtain intercepted data information includes:

[0035] Calculating peak energy according to a real peak value peaki and an imaginary peak value peakq, and determining that the frame header is located at a position of the M parallel code streams if the peak energy is not less than an energy threshold;

[0036] intercepting data information of a preset length from the delayed M-channel data stream signals according to the frame header;

[0037] The peak energy calculation formula is: power = peaki 2 +peakq 2 , power is the peak energy, peaki is the real peak, and peakq is the imaginary peak.

[0038] Optionally, the step of performing phase ambiguity correction on the intercepted data information according to the phase ambiguity information includes:

[0039] Calculating a phase ambiguity value according to the real peak value peaki and the imaginary peak value peakq, and performing phase ambiguity correction on the intercepted data information according to a ambiguity correction formula according to the phase ambiguity value;

[0040] Wherein, the blur correction formula is: Sig_dufuzzed is the corrected signal, and Sig_out is the intercepted data information

[0041] The above-mentioned main scheme of the present application and its further options can be freely combined to form multiple schemes, all of which are schemes that can be adopted and protected by the present invention; and in this application, (each non-conflicting option) can also be freely combined with each other and with other options. After understanding the scheme of the present invention, those skilled in the art will understand that there are many combinations based on the existing technology and common knowledge, all of which are technical schemes to be protected by the present invention, and they are not exhaustive here.

[0042] The beneficial effects of the present invention are:

[0043] (1) Using a parallel method to process parallel code streams can improve the data processing speed compared to the existing technology of processing code streams in a serial manner.

[0044] (2) The autocorrelation peak is obtained by sliding convolution calculation to determine the position of the frame header in the parallel code stream. This can complete the frame synchronization operation under low signal-to-noise ratio conditions, improve the frame synchronization accuracy, and is suitable for more encoding and decoding algorithms, with better applicability.

[0045] (3) The phase ambiguity information is calculated by the autocorrelation peak, and the phase of the data stream signal is compensated, which solves the phase ambiguity problem existing in the digital communication receiver and further improves the frame synchronization accuracy.

[0046] (4) Successfully used digital communication receivers and passed relevant digital communication system tests, and was able to accurately complete frame synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A structural diagram of a frame synchronization device provided in an embodiment of the present application is shown.

[0048] Figure 2 Schematic diagram showing the sliding convolution calculation in the autocorrelation calculation module

[0049] Figure 3 A schematic diagram showing intercepted data information provided by an embodiment of the present application

[0050] Figure 4 A schematic flow chart of a frame synchronization method provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0052] Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of the present invention.

[0053] In the prior art, frame synchronization involves inserting a dedicated synchronization bit sequence before the information segment. After receiving the information data at a high-speed receiver, the receiver, after completing basic digital communication steps such as timing synchronization, gain compensation, and carrier synchronization, uses hard decision to obtain the bit information. The receiver then calculates the Hamming distance between the bit information and the synchronization sequence to determine whether the frame header has been reached, thereby achieving frame synchronization. However, because this method requires hard decisioning of the modulated signal, when a low signal-to-noise ratio (SNR) is encountered, the hard decision operation is likely to result in errors, causing errors in the bit information and Hamming distance, thereby affecting the accuracy of frame synchronization. Furthermore, the algorithm used for frame synchronization is incompatible with some error-correcting code algorithms (LDPC decoding algorithms). The bit information obtained through hard decisioning cannot meet the input requirements of the LDPC decoding algorithm.

[0054] Existing parallel frame synchronization methods for transmission applications first convert the serial bit stream into a parallel bit stream. The parallel bit stream is then processed serially to search for a frame header. Only after the correct frame header is found can subsequent synchronization be performed. While this method can meet the requirements of high-speed communication, it is time-consuming and cannot meet the transmission needs of high-speed applications.

[0055] Since the frame header position is not fixed, the non-fixed frame header will affect the frame synchronization accuracy of the parallel signal transmission system. However, a carrier synchronization algorithm based on a phase-locked loop is used to solve the problem of frame synchronization accuracy. Due to the existence of the signal local oscillator, the signal may also have phase ambiguity. Therefore, how to correct the phase ambiguity and complete frame synchronization has become an urgent problem that people in this field need to solve.

[0056] In response to the above problems, an embodiment of the present application proposes a frame synchronization device, which determines the frame header position by the autocorrelation peak obtained by sliding autocorrelation calculation to ensure frame synchronization accuracy, and performs phase compensation by calculating the fuzzy phase value through the autocorrelation peak, thereby solving the phase ambiguity problem existing in the digital receiver system. The combination of the two further improves the frame synchronization accuracy, which is introduced in detail below.

[0057] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a frame synchronization device provided in an embodiment of the present application is shown. The frame synchronization device includes a signal flow processing module, an autocorrelation calculation module, a delay module, and a phase ambiguity resolution module. The signal flow processing module is connected to the autocorrelation calculation module and the delay module, respectively, and the phase ambiguity resolution module is also connected to the autocorrelation calculation module and the delay module, respectively.

[0058] The signal stream processing module delays and intercepts the received M parallel code streams to generate at least one M data stream signal, and outputs the M data stream signals to the delay module and the autocorrelation calculation module, where the parallel code stream includes a data frame and a frame header corresponding to the data frame, and the value of M is an integer greater than zero.

[0059] Next, each module will be described in detail by taking the input of a parallel code stream with an M value of 8 as an example.

[0060] The data frame in the parallel code stream consists of two parts, one part is a synchronization sequence, the length of a single synchronization sequence is 64 bits (bit), and the number of synchronization sequences can be multiple. The other part is the information bit. The information bit length selected in the embodiment of the present application is 1408 bits, and the length of the information bit obtained by the encoder algorithm is 1664 bits. In addition, the number of information bits can also be set to multiple. It is worth noting that if the number of synchronization sequences is set to N and the number of information bits is set to M, then the total length of the entire data frame is: (N*64+M*1664) bits. In a possible embodiment, taking N as 1 and M as 1 as an example, the total length of the entire data frame is 1728 bits.

[0061] The serial code stream output by the demodulator can be converted from serial to parallel and adjusted in sequence to obtain 8 parallel code streams, which are input into the signal stream processing module. The parallel code streams are transmitted in parallel. Since the subsequent autocorrelation calculation module needs to perform sliding convolution on the data stream signal to obtain the autocorrelation peak, the frame header corresponding to the data frame needs to be aligned with the autocorrelation sequence to calculate the correct autocorrelation peak. However, since the position of the frame header in the 8 parallel code streams cannot be determined, the parallel code streams cannot be directly used as input for autocorrelation peak calculation. Therefore, the signal stream processing module is required to delay and intercept the received 8 parallel code streams to make them more suitable for the calculation of the autocorrelation peak.

[0062] The steps of delayed interception are: first delay the 8 parallel code streams, the delay length can be one clock length, and then any one of the 8 parallel code streams is used as the interception point to intercept the parallel code stream, and at least one M-way data stream signal can be obtained, wherein delayed interception can change the starting position of the data, but does not change the arrangement position of the data.

[0063] The autocorrelation calculation module receives the M-channel data stream signals sent by the signal stream processing module, performs sliding convolution calculation on the data stream signals to obtain the autocorrelation peak, and sends it to the phase ambiguity resolution module.

[0064] The delay module receives the M-channel data stream signals sent by the signal stream processing module, delays the M-channel data stream signals to ensure the synchronization of the M-channel data stream signals with the autocorrelation peak, and outputs the delayed M-channel data stream signals to the phase ambiguity resolution module.

[0065] Because the autocorrelation calculation module consumes a certain amount of time to perform sliding convolution calculation on the data stream signal, if the M-channel data stream signals output by the signal stream processing module are directly input into the phase ambiguity removal module, the autocorrelation peak will be delayed in being input into the phase ambiguity removal module. In this way, the synchronization between the M-channel data stream signals and the autocorrelation peak cannot be guaranteed, and it cannot be guaranteed that the output flags during frame synchronization correspond to the useful information. This will affect the subsequent phase ambiguity removal module's determination of the specific position of the frame header in the M-channel parallel code stream based on the autocorrelation peak. Therefore, the synchronization between the M-channel data stream signals and the autocorrelation peak must be guaranteed.

[0066] In a possible implementation, the delay time of the delay module is directly related to the length of the synchronization sequence in the data frame, and the relationship between the two is: P=2 K , P is the length of the synchronization sequence, K is the cumulative calculation delay. It is worth noting that the delay time of the delay module can also be determined by the delay of the complex multiplier and the delay generated by the data stream. The embodiment of the present application does not impose any limitation on this.

[0067] The phase ambiguity resolution module determines the position of the frame header in the M-channel parallel code stream according to the autocorrelation peak, intercepts the delayed M-channel data stream signal according to the frame header to obtain intercepted data information, calculates the phase ambiguity information, and performs phase ambiguity correction on the intercepted data information according to the phase ambiguity information.

[0068] The phase ambiguity resolution module has two functions. The first function is to determine the position of the frame header. By intercepting the data information based on the frame header position, the parallel frame synchronization operation can be completed. The second function is to calculate the phase ambiguity information and then compensate for the ambiguous phase to solve the phase ambiguity problem. The combination of the two improves the accuracy of frame synchronization.

[0069] Next, a detailed description of the internal submodules of the autocorrelation calculation module and the phase ambiguity resolution module is given.

[0070] The autocorrelation calculation module includes P autocorrelation calculation submodules, which correspond one-to-one to the data stream signals. That is, the number of autocorrelation calculation submodules is the same as the number of parallel code streams or data stream signals received (P=M). Each data stream signal will enter an independent autocorrelation calculation submodule, so the autocorrelation calculation submodule can process the input data stream signals in parallel.

[0071] The autocorrelation calculation submodule performs complex multiplication on the data stream signal and the conjugate sequence to obtain the complex multiplication result, and accumulates the complex multiplication result to obtain the autocorrelation value. The imaginary part and the real part of the autocorrelation value are then separated to obtain the real part peaki and the imaginary part peakq.

[0072] The calculation formula of the autocorrelation value is: Sig(p) is the data stream signal, conj(Seq(p)) is the conjugate sequence in the synchronization sequence, the length of the conjugate sequence is P, wherein the autocorrelation value Corre(m) is in complex form. After obtaining the autocorrelation value Corre(m), the imaginary part and the real part of the autocorrelation value Corre(m) are separated according to peaki=real(Corre) and peakq=imag(Corre) to obtain the real part peaki and the imaginary part peakq.

[0073] like Figure 2 As shown, Figure 2 The diagram shows a sliding convolution calculation in the autocorrelation calculation module. In the figure, sig1-sig32 represent the data stream signals generated by the signal stream processing module, Corre represents the calculated autocorrelation value, and Cor_Seq1-Cor_Seq32 represent the conjugate sequences of the synchronization sequence. The conjugate sequence Cor_Seq1 first enters the complex multiplier and is complex-multiplied with the data stream signal sig1 to obtain a complex multiplication result, which is then sent to the accumulator. Similarly, the conjugate sequence Cor_Seq2 is complex-multiplied with the data stream signal sig2 to obtain a complex multiplication result, which is then sent to the accumulator until the loop is complete. The conjugate sequence must correspond to the data stream signal to calculate the correct complex multiplication result.

[0074] In addition, the phase ambiguity resolution module includes a threshold judgment submodule and a frame header interception submodule. The threshold judgment submodule can calculate the peak energy based on the real peak value peaki and the imaginary peak value peakq. If the peak energy is not less than the energy threshold, the frame header is determined to be located at the position of the M parallel code streams. The frame header interception submodule can intercept data information of a preset length from the delayed M data stream signals based on the frame header.

[0075] Since there is phase ambiguity between the real peak peaki and the imaginary peak peakq, if we directly compare the real peak peaki and the imaginary peak peakq, we cannot determine whether the autocorrelation peak has reached the preset threshold. Therefore, we introduce the threshold judgment submodule and calculate the peak energy through the formula: power = peaki 2 +peakq 2 The peak energy is calculated and the position of the frame header in the M parallel streams is determined by comparing the peak energy power with the energy threshold P_threshold. If the peak energy power is not less than the energy threshold, the output head_vld is high, indicating that the position of the frame header in the M parallel streams has been determined.

[0076] Taking the data stream signal with M=8 as an example, each of the 8 autocorrelation calculation submodules corresponding to the data stream signal will output a real peak value peaki and an imaginary peak value peakq to the threshold judgment submodule, so the threshold judgment submodule will receive the corresponding eight real peak values peaki and eight imaginary peak values peakq, and will also calculate eight peak energy powers through the peak energy calculation formula. However, only one of the eight peak energy powers is not less than the energy threshold. At this time, the output head_vld is a high level, and the remaining peak energy powers are all less than the energy threshold, and the output is a low level.

[0077] If the first autocorrelation calculation submodule sends the real peak value peaki and the imaginary peak value peakq to the threshold judgment submodule, the threshold judgment submodule calculates the peak energy. If the peak energy is not less than the energy threshold, it is determined that the frame header is located in the first of the M parallel code streams. If the peak energy is less than the energy threshold, it indicates that the frame header is not located in the first of the M parallel code streams. The peak energy is then calculated for the real peak value peaki and the imaginary peak value peakq sent by the second autocorrelation calculation submodule, and the cycle continues until the Mth autocorrelation calculation submodule is reached.

[0078] After the threshold judgment submodule determines that the frame header is located in the Mth channel, the corresponding Mth autocorrelation calculation submodule will send the flag bit head_vld of the frame header position to the frame header interception submodule. The frame header interception submodule starts from the flag bit head_vld and intercepts the preset length of intercepted data information for the delayed M-channel data stream signal, where the flag bit head_vld indicates the frame header position.

[0079] Figure 3The schematic diagram of intercepting data information provided by the embodiment of the present application is shown. As shown in the figure, the length of a single synchronization sequence is 64 bits. The synchronization sequence is first modulated by QPSK to obtain iq data. At this time, the M-channel data stream signal after delay is also iq data. At this time, if all clock sequences are to be obtained, 4 clocks are required. However, since the position of the frame header is not fixed, the delay will continue to be one clock, so that the total length of the synchronization sequence reaches 80 bits. Figure 3 The frame header in the signal is located in the 4th data stream signal after the delay, and the 4th data stream signal after the delay is taken as an example for description.

[0080] Among them, Seq1 to Seq32 represent the synchronization sequences after QPSK modulation, and the rest represent other non-synchronous sequences. The delayed 4th data stream signal is intercepted after 4 delayed synchronization sequences (64 bits). At the same time, the delayed data stream signals of other channels are also intercepted according to 4 delayed synchronization sequences (64 bits). The data stream signals after interception are still 8 channels. It is worth noting that the Mth data stream signal where the frame header is located after interception can also be placed in the first channel.

[0081] In addition, the phase ambiguity resolution module also includes a phase ambiguity resolution submodule, which can calculate the phase ambiguity value based on the real peak value peaki and the imaginary peak value peakq, and then perform phase ambiguity compensation on the intercepted data information according to the ambiguity correction formula based on the phase ambiguity value to solve the phase ambiguity problem existing in the digital receiver system and further improve the synchronization accuracy of frame synchronization.

[0082] The blur correction formula is: Sig_dufuzzed is the corrected signal, Sig_out is the intercepted data information, where the phase fuzzy value is in the fuzzy correction formula

[0083]

[0084] It is worth noting that in the frame synchronization process, the entire frame synchronization device is implemented through FPGA, where the FPGA selects the xc7vx690tffg1972-2 chip of Xlinx company, and the development tool selects Vivado2017.4.

[0085] Furthermore, the embodiments of the present application have been successfully applied to digital communication receivers and have passed relevant digital communication system tests.

[0086] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0087] (1) Using a parallel method to process parallel code streams can improve the data processing speed compared to the existing technology of processing code streams in a serial manner.

[0088] (2) The autocorrelation peak is obtained by sliding convolution calculation to determine the position of the frame header in the parallel code stream. This can complete the frame synchronization operation under low signal-to-noise ratio conditions, improve the frame synchronization accuracy, and is suitable for more encoding and decoding algorithms, with better applicability.

[0089] (3) The phase ambiguity information is calculated by the autocorrelation peak, and the phase of the data stream signal is compensated, which solves the phase ambiguity problem existing in the digital communication receiver and further improves the frame synchronization accuracy.

[0090] (4) Successfully used digital communication receivers and passed relevant digital communication system tests, and was able to accurately complete frame synchronization.

[0091] Please refer to the following Figure 4 , Figure 4 A schematic flow chart of a frame synchronization method provided by an embodiment of the present invention is shown. The frame synchronization method includes the following steps:

[0092] S110 , delaying and intercepting the received M parallel code streams to generate at least one M data stream signal, wherein the parallel code streams include data frames and frame headers corresponding to the data frames.

[0093] S120 , performing sliding convolution calculation on the M data stream signals to obtain M autocorrelation peaks, where the autocorrelation peaks include a real part peaki and an imaginary part peakq.

[0094] S130 , delaying the M data stream signals to ensure synchronization between the M data stream signals and the M autocorrelation peaks.

[0095] S140 , determining the position of the frame header in the M parallel code streams according to the M autocorrelation peaks, and intercepting the delayed M data stream signals according to the frame header to obtain intercepted data information.

[0096] S150. Calculate phase ambiguity information based on the M autocorrelation peaks, and perform phase ambiguity correction on the intercepted data information according to the phase ambiguity information.

[0097] The above frame synchronization method is a specific step performed by the above frame synchronization device and is performed by a specific module in the frame synchronization device. Since the frame synchronization device has been described in detail above, the embodiment of the present application will not be repeated here.

[0098] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A frame synchronization device, characterized in that: The device comprises: a signal flow processing module, an autocorrelation calculation module, a delay module and a phase ambiguity resolution module, wherein: The signal stream processing module is configured to delay and intercept the received M parallel code streams to generate at least one M data stream signal, and output the M data stream signal to the delay module and the autocorrelation calculation module, wherein the parallel code stream includes a data frame and a frame header corresponding to the data frame; The autocorrelation calculation module is used to perform sliding convolution calculation on the M data stream signals to obtain M autocorrelation peaks, and send the M autocorrelation peaks to the phase ambiguity removal module, wherein the autocorrelation peaks include a real peak value peaki and an imaginary peak value peakq; The delay module is used to delay the M data stream signals to ensure the synchronization of the M data stream signals with the M autocorrelation peaks, and output the delayed M data stream signals to the phase ambiguity resolution module; The phase ambiguity removal module is configured to determine, based on the M autocorrelation peaks, the position of the frame header in the M parallel code streams, and intercept the delayed M data stream signals according to the frame header to obtain intercepted data information; The phase ambiguity resolution module is further configured to calculate phase ambiguity information based on the M autocorrelation peaks, and perform phase ambiguity correction on the intercepted data information according to the phase ambiguity information.

2. The frame synchronization device according to claim 1, wherein: The data frame includes a conjugate sequence, which is a synchronization sequence with autocorrelation characteristics. The autocorrelation calculation module includes P autocorrelation calculation submodules, and the number of autocorrelation calculation submodules is consistent with the number of paths of the data stream signal and corresponds one to one. The autocorrelation calculation submodule is configured to perform complex multiplication calculation on the data stream signal and the conjugate sequence to obtain a complex multiplication result, and perform accumulation calculation on the complex multiplication result to obtain an autocorrelation value; The autocorrelation calculation submodule is further used to separate the imaginary part and the real part of the autocorrelation value to obtain the real part peaki and the imaginary part peakq; The calculation formula of the autocorrelation value is: Sig(p) is the data stream signal, and conj(Seq(p)) is the conjugate sequence.

3. The frame synchronization device according to claim 1, wherein: The phase ambiguity resolution module includes a threshold judgment submodule and a frame header interception submodule; The threshold judgment submodule is used to calculate the peak energy according to the real peak value peaki and the imaginary peak value peakq, and if the peak energy is not less than the energy threshold, determine that the frame header is located at the position of the M parallel code streams; The frame header interception submodule is used to intercept data information of a preset length from the delayed M-channel data stream signals according to the frame header; The peak energy calculation formula is: power = peaki 2 +peakq 2 , power is the peak energy, peaki is the real peak, and peakq is the imaginary peak.

4. The frame synchronization device according to claim 1, wherein: The phase ambiguity resolution module also includes a phase ambiguity resolution submodule; a phase ambiguity resolution submodule, configured to calculate a phase ambiguity value according to the real peak value peaki and the imaginary peak value peakq, and perform phase ambiguity correction on the intercepted data information according to a ambiguity correction formula based on the phase ambiguity value; Wherein, the blur correction formula is: Sig_dufuzzed is the corrected signal, and Sig_out is the intercepted data information.

5. A frame synchronization method, characterized in that: include: Delaying and intercepting the received M parallel code streams to generate at least one M data stream signal, wherein the parallel code streams include data frames and frame headers corresponding to the data frames; Performing sliding convolution calculation on the M data stream signals to obtain M autocorrelation peaks, wherein the autocorrelation peaks include a real peak value peaki and an imaginary peak value peakq; Delaying the M data stream signals to ensure synchronization between the M data stream signals and the M autocorrelation peaks; Determining the position of the frame header in the M parallel code streams according to the M autocorrelation peaks, and intercepting the delayed M data stream signals according to the frame header to obtain intercepted data information; Phase ambiguity information is calculated based on the M autocorrelation peaks, and phase ambiguity correction is performed on the intercepted data information according to the phase ambiguity information.

6. The frame synchronization method according to claim 5, wherein: The data frame includes a conjugate sequence, which is a synchronization sequence with an autocorrelation characteristic. The step of performing sliding convolution calculation on the M data stream signals to obtain M autocorrelation peaks includes: Performing complex multiplication calculation on the data stream signal and the conjugate sequence to obtain a complex multiplication result, and accumulating the complex multiplication result to obtain an autocorrelation value; Separating the imaginary part and the real part of the autocorrelation value to obtain the real part peaki and the imaginary part peakq; The calculation formula of the autocorrelation value is: Sig(p) is the data stream signal, and conj(Seq(p)) is the conjugate sequence.

7. The frame synchronization method according to claim 5, wherein: The step of determining, based on the M autocorrelation peaks, the position of the frame header in the M parallel code streams, and intercepting the delayed M data stream signals according to the frame header to obtain intercepted data information includes: Calculating peak energy according to a real peak value peaki and an imaginary peak value peakq, and determining that the frame header is located at a position of the M parallel code streams if the peak energy is not less than an energy threshold; intercepting data information of a preset length from the delayed M-channel data stream signals according to the frame header; The peak energy calculation formula is: power = peaki 2 +peakq 2 , power is the peak energy, peaki is the real peak, and peakq is the imaginary peak.

8. The frame synchronization method according to claim 5, wherein: The step of performing phase ambiguity correction on the intercepted data information according to the phase ambiguity information includes: Calculating a phase ambiguity value according to the real peak value peaki and the imaginary peak value peakq, and performing phase ambiguity correction on the intercepted data information according to a ambiguity correction formula according to the phase ambiguity value; Wherein, the blur correction formula is: Sig_dufuzzed is the corrected signal, and Sig_out is the intercepted data information.

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