A row data scanning readout circuit for an image sensor
By designing a row data scanning and reading circuit in the image sensor, and using the signal generation module and the sensitive amplifier to compare the data bus voltage difference of the opposite output, the problem of large pixel array area and long data bus traces is solved, and the accurate reading of data is achieved And reduces area and power consumption.
Patent Information
- Application Number
- CN202211581100.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-07
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2042-12-07
AI Technical Summary
When the pixel array area is large and the data bus trace is too long, the line scanning circuit of the image sensor is difficult to ensure the accurate output of data, and the common line scanning circuit cannot meet the requirements of accurately reading data, resulting in unstable data reading and errors, accompanied by increased area power consumption and complex timing.
A row data scanning and reading circuit for image sensor is designed, including a pixel array, an electrical signal conversion module, a row data latch, a row scan reading module and a sensitive amplifier. The row data is connected through the input end of the row scan reading module. The output end of the latch uses the signal generation module to generate a precharge reset signal and a line scan selection signal to control the readout unit, and compare the voltage difference between the first data bus and the second data bus outputted oppositely to achieve accurate reading of data.
The circuit structure is simple, reducing the requirements of output driving capabilities, reducing the pixel array area and power consumption during long-distance transmission of large arrays, ensuring accurate data reading and avoiding errors during data transmission.
Smart Images
Figure CN115942141B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of image sensors, and in particular to a row data scanning and reading circuit of an image sensor. Background Art
[0002] The image sensor is provided with a row scanning circuit, and data is read out through the row scanning circuit. For image sensors with a large pixel array area, when the data bus is too long, the parasitic resistance and capacitance on the data bus will increase sharply, and errors will occur when the data is read and output. At the same time, with the increase in power consumption and area of the row scanning circuit, and the complexity of the timing, the common row scanning circuit can no longer meet the requirements of accurate data reading. Therefore, when the pixel array circuit area of the row scanning circuit in the image sensor is too large and the data bus line is too long, it will cause unstable data reading and errors, while also increasing area power consumption and complicating the timing. Summary of the invention
[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a row data scanning and reading circuit for an image sensor, which can ensure accurate data output when the pixel array is too large and the data bus line is too long.
[0004] To achieve the above-mentioned object and other related objects, the present invention provides a row data scanning and reading circuit of an image sensor, comprising:
[0005] A pixel array, the pixel array comprising a plurality of pixel units, and the pixel array outputs an electrical signal;
[0006] An electrical signal conversion module, wherein an input end of the electrical signal conversion module is electrically connected to an output end of the pixel unit, and the electrical signal conversion module outputs digital image data;
[0007] A row data latch, wherein an input end of the row data latch is electrically connected to an output end of the electrical signal conversion module, and the row data latch outputs in-phase readout data and inverted readout data;
[0008] a row scanning readout module, the row scanning readout module comprising a plurality of readout units, and an input end of the readout unit is electrically connected to an output end of the row data latch; and
[0009] A sense amplifier, wherein the output end of the readout unit is electrically connected to the non-inverting input end of the sense amplifier through a first data bus, and is electrically connected to the inverting input end of the sense amplifier through a second data bus, and the voltage difference between the first data bus and the second data bus is compared through the sense amplifier.
[0010] In an embodiment of the present invention, the row scanning readout module further includes a signal generating module, and an output end of the signal generating module is electrically connected to an input end of the readout unit.
[0011] In an embodiment of the present invention, the signal generation module outputs a row scan selection signal and a precharge reset signal.
[0012] In one embodiment of the present invention, the read-out unit includes a first selection transfer transistor, a source of the first selection transfer transistor is electrically connected to the in-phase data output terminal of the row data latch, a drain of the first selection transfer transistor is electrically connected to the first data bus, and a gate of the first selection transfer transistor is electrically connected to the row scan selection signal output terminal of the signal generating module.
[0013] In one embodiment of the present invention, the read-out unit also includes a second selection transfer transistor, the source of the second selection transfer transistor is electrically connected to the inverting data output terminal of the row data latch, the drain of the second selection transfer transistor is electrically connected to the second data bus, and the gate of the second selection transfer transistor is electrically connected to the row scan selection signal output terminal of the signal generating module.
[0014] In one embodiment of the present invention, the read-out unit also includes a first pre-charge reset transistor, the source of the first pre-charge reset transistor is connected to a voltage power supply, the drain of the first pre-charge reset transistor is electrically connected to the first data bus, and the gate of the first pre-charge reset transistor is electrically connected to the pre-charge reset signal output terminal of the signal generating module.
[0015] In one embodiment of the present invention, the read-out unit also includes a second pre-charge reset transistor, the source of the second pre-charge reset transistor is connected to a voltage power supply, the drain of the second pre-charge reset transistor is electrically connected to the second data bus, and the gate of the second pre-charge reset transistor is electrically connected to the pre-charge reset signal output terminal of the signal generating module.
[0016] In an embodiment of the present invention, the signal generating module includes a plurality of triggers, and the output terminals of the triggers are electrically connected to the input terminals of the AND gates.
[0017] In one embodiment of the present invention, the sensitive amplifier includes an amplifier stage and a latch stage, the in-phase input terminal of the amplifier stage is electrically connected to the first data bus, the inverting input terminal of the amplifier stage is electrically connected to the second data bus, and the output terminal of the amplifier stage is electrically connected to the input terminal of the latch stage.
[0018] In one embodiment of the present invention, the sensitive amplifier includes an amplifier stage and a latch stage, the in-phase input terminal of the amplifier stage is electrically connected to the first data bus, the inverting input terminal of the amplifier stage is electrically connected to the second data bus, and the output terminal of the amplifier stage is electrically connected to the input terminal of the latch stage.
[0019] In one embodiment of the present invention, the amplifier stage includes a first reset tube, a source of the first reset tube is electrically connected to the first data bus, a drain of the first reset tube is electrically connected to the second data bus, and a gate of the first reset tube is connected to a pre-charge reset signal.
[0020] In one embodiment of the present invention, the amplifier stage also includes a second reset tube and a third reset tube, the source of the second reset tube and the third reset tube is connected to a voltage power supply, the gate of the second reset tube and the third reset tube is connected to a pre-charge reset signal, and the drain of the second reset tube is electrically connected to the first data bus, and the drain of the third reset tube is electrically connected to the second data bus.
[0021] The present invention provides an image sensor, comprising the row data scanning readout circuit of the image sensor mentioned above.
[0022] As described above, the present invention provides a row data scanning readout circuit of an image sensor, which is electrically connected to the output end of a row latch through the input end of a row scanning readout module, so as to read digital signal data. The row scanning readout module includes a plurality of readout units, and the readout units sequentially read the in-phase readout data and the inverted readout data output by the corresponding column row data latch. The row scanning readout module also includes a signal generation module, which generates a precharge reset signal and a row scanning selection signal through the signal generation module, and controls the readout unit circuit to reset the data bus and read out the data. Finally, the voltage difference between the first data bus and the second data bus with opposite outputs is compared by a sensitive amplifier to complete the accurate output of the read data. In this embodiment, by setting the first data bus and the second data bus with opposite outputs, the voltage difference between the first data bus and the second data bus is compared to achieve accurate data reading, thereby reducing the requirements for output drive capability. The circuit structure is simple, and when a large array is transmitted over a long distance, the consumption of pixel array area and power consumption is reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.
[0024] Figure 1Shown is a schematic structural diagram of a row data scanning readout circuit of an image sensor;
[0025] Figure 2 Shown is a structural schematic diagram of a row data scanning readout circuit of an image sensor of the present invention;
[0026] Figure 3 Shown is a schematic structural diagram of a readout unit of the present invention;
[0027] Figure 4 Shown is a schematic diagram of the connection structure of the signal generating module of the present invention;
[0028] Figure 5 Shown is a circuit operation timing principle diagram of the signal generating module of the present invention;
[0029] Figure 6 The display is a schematic diagram of the circuit operation timing of the present invention;
[0030] Figure 7 Shown is a schematic structural diagram of an amplifier stage of a sensitive amplifier of the present invention;
[0031] Figure 8 Shown is a schematic structural diagram of a latch stage of a sense amplifier of the present invention;
[0032] Fig. 9 Shown is a circuit operation timing principle diagram of the sense amplifier of the present invention. DETAILED DESCRIPTION
[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0034] See also Figure 1As shown, the row scanning circuit of the image sensor includes a pixel array 10, and the pixel array 10 includes a plurality of pixel units 11. The pixel units 11 are arranged orthogonally in the pixel array 10, the pixel units 11 arranged in the horizontal direction form a row, each row includes M pixel units 11, and the pixel units 11 arranged in the vertical direction form a column, each column includes N pixel units 11, so the total number of pixel units 11 in the pixel array 10 is M×N. The exposure performed in the pixel array 10 starts and ends by row, that is, the pixel units 11 are exposed to all columns of the same row at the same time, so that the pixel array 10 generates a photoelectric effect, and converts the photoelectrons generated by the external light input into an electrical signal. The output end of the pixel array 10 is electrically connected to the input end of the current source load (CSL), and the electrical signal converted by the pixel units 11 in each column is input to the CSL. The output of the CSL is electrically connected to the input of a programmable gain amplifier (PGA), and the output of the PGA is electrically connected to an analog-to-digital converter (ADC). After the electrical signal is amplified by the PGA, it is processed by the ADC and converted into digital signal data for output.
[0035] See also Figure 1As shown, the row scanning circuit of the image sensor also includes a row data latch 20 and a row scanning circuit 30. The input end of the row data latch 20 is electrically connected to the output end of the ADC, and the output end of the row data latch 20 is electrically connected to the input end of the row scanning circuit 30. The converted digital signal data is latched by the row data latch 20, and the digital image data corresponding to the pixel unit 11 converted is input into the row scanning circuit 30 one by one by column. The digital image data is, for example, D[0]<11:0> to D[N-1]<11:0>. After the pixel array 10 is exposed for the first time and the electrical signal conversion is processed, D[0]<11:0> is the digital image data corresponding to the conversion of the pixel unit 11 in the first row and the first column, D[1]<11:0> is the digital image data corresponding to the conversion of the pixel unit 11 in the first row and the second column, and so on to the digital image data D[N]<11:0> corresponding to the conversion of the pixel unit 11 in the first row and the Nth column. The row scanning circuit 30 includes a plurality of buffers 31, a plurality of switches 32 and a trigger 33, wherein the trigger 33 is, for example, a D trigger. The buffer 31 is electrically connected to the data bus through the switch 32, and the digital image data opens the switch 32 one by one by column to output the data to the data bus. The plurality of triggers 33 are electrically connected, and are connected to the row scanning clock signal HCLK through the clock interface CK. The input terminal D of the first trigger 33 is connected to the row scanning trigger signal HTRIG, and the output terminal Q is electrically connected to the input terminal D of the second trigger 33, thereby electrically connecting the input terminals and output terminals of the plurality of triggers 33, so that the trigger signal HTRIG controls the trigger 33 to output a continuous selection signal. The continuous selection signal, for example, HSEL <0> ~HSEL <n-1>Among them, HSEL <0> HSEL is the continuous selection signal output by the trigger corresponding to the first column pixel unit 11. <1> is the continuous selection signal HSEL output by the trigger corresponding to the pixel unit 11 in the second column, and so on, the continuous selection signal HSEL output by the trigger corresponding to the pixel unit 11 in the Nth column <n-1>By controlling multiple switches 32 one by one through continuous selection signals, the digital image data in the row data latch 20 is connected to the data bus one by one through the buffer 31, so that the data is read out to the interface circuit and sent to the outside of the image sensor. However, when the bus length is large and the data transmission is fast, it is easy to cause a sharp increase in parasitics and loads, causing errors in the data transmission process.
[0036] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the row data scanning readout circuit of the image sensor includes a pixel array 100, and the pixel array 100 includes a plurality of pixel units 110. The pixel units 110 are arranged orthogonally in the pixel array 100, and the pixel units 110 arranged in the horizontal direction constitute a row, each row includes M pixel units 110, and the pixel units 110 arranged in the vertical direction constitute a column, each column includes N pixel units 110, so the total number of pixel units 110 of the pixel array 100 is M×N. When external light irradiates the pixel array 100, a photoelectric effect occurs in the pixel array 100, and the pixel units 110 complete exposure and convert the accumulated photoelectrons into electrical signals. Among them, the exposure performed in the pixel array 100 starts and ends by row, that is, the pixel units 110 are exposed in sequence in the same row and different columns. Specifically, the N columns of pixel units 110 in the first row are exposed in sequence, and the corresponding photoelectrons are converted into electrical signals for output, and the final data readout is completed. At this time, the pixel units 110 in the second row and N columns are exposed in sequence, the corresponding photoelectrons are converted into electrical signals for output, and the final data readout is completed. This process is repeated in this way until the pixel units 110 in the Mth row and N columns are exposed in sequence, the corresponding photoelectrons are converted into electrical signals for output, and the final data readout is completed.
[0037] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the row data scanning readout circuit of the image sensor also includes an electrical signal conversion module 200, the input end of the electrical signal conversion module 200 is electrically connected to the output end of the pixel array 100, and the electrical signal generated by the pixel array 100 in columns is input to the electrical signal conversion module 200. The electrical signal conversion module 200 includes a CSL, a PGA, and an ADC. The output end of the pixel array 100 is electrically connected to the input end of the CSL, and the electrical signal converted by each column of pixel units 110 is input to the CSL, that is, the electrical signal converted by N columns of pixel units 110 is input to the CSL. The output end of the CSL is electrically connected to the input end of the PGA, and the output end of the PGA is electrically connected to the input end of the ADC. After the electrical signal is amplified by the PGA, it is processed by the ADC to convert the electrical signal into a digital signal, that is, the digital signal data is finally output through the ADC.
[0038] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the row data scanning readout circuit of the image sensor also includes a row data latch 300, and the input end of the row data latch 300 is electrically connected to the output end of the electrical signal conversion module 200, that is, the input end of the row data latch 300 is electrically connected to the ADC. The digital signal data converted by the ADC is latched by the row data latch 300, that is, the digital signal data corresponding to the N-column pixel unit 110. Among them, after the first row of pixel units 110 are exposed for the first time, the generated electrical signal is converted by the electrical signal conversion module 200 to generate digital image data, and the digital image data corresponding to the first row of pixel units 110 is input to the row data latch 300. In this embodiment, the ADC is 12 bits, so the data latched by the row data latch 300 is 12 bits. Specifically, the data latched by the row data latch 300 is the digital signal data D[0]<11:0>~D[N-1]<11:0>. Among them, after the first exposure and electrical signal conversion processing of the pixel array 100, D[0]<11:0> is the 12-bit digital signal data correspondingly converted and generated by the pixel units 110 of the first row and the first column, D[1]<11:0> is the 12-bit digital signal data correspondingly converted and generated by the pixel units 110 of the first row and the second column, and so on to the 12-bit digital signal data D[N-1]<11:0> correspondingly converted and generated by the pixel units 110 of the first row and the Nth column. At the same time, after the exposure of the first row of pixel units 110 and the final data readout, the data latched by the row data latch 300 is the 12-bit digital signal data correspondingly converted by the other N-1 rows of pixel units 110. In this embodiment, after the row data latch 300 latches the digital signal data, it outputs the corresponding in-phase readout data DB and inverted readout data DN. Specifically, the in-phase read data DB is, for example, D[0]<11:0>B to D[N-1]<11:0>B, and the inverted read data DN is, for example, D[0]<11:0>N to D[N-1]<11:0>N. D[0]<11:0>B and D[0]<11:0>N are the read data and inverted read data corresponding to the digital signal data D[0]<11:0>, D[1]<11:0>B and D[1]<11:0>N are the read data and inverted read data corresponding to the digital signal data D[1]<11:0>, and so on, D[N-1]<11:0>B and D[N-1]<11:0>N are the in-phase read data and inverted read data corresponding to the digital signal data D[N-1]<11:0>.
[0039] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the row data scanning readout circuit of the image sensor also includes a row scanning readout module 400, the input end of the row scanning readout module 400 is electrically connected to the output end of the row data latch 300, and the output end of the row scanning readout module 400 is electrically connected to the interface circuit, and the scanned data is output to the outside of the image sensor. The row scanning readout module 400 includes a plurality of readout units 401, and the plurality of readout units 401 are electrically connected to the data bus. The input end of the readout unit 401 is electrically connected to the output end of the data latch 300. Since the width of the data bus is related to the ADC resolution, in this embodiment, the ADC is 12 bits, and the row data latch 300 latches and outputs 12 bits of digital signal data. Then, the corresponding row scanning readout module 400 has a 12-bit readout unit 401 connected to the 12-bit digital signal data, and each bit of digital signal data latched and output by each column of pixel units 110 through the row latch 300 has a corresponding readout unit 401 connected to read.
[0040] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, wherein the row data scanning readout circuit of the image sensor includes a sense amplifier 402, and a readout unit 401 is electrically connected to the input end of the sense amplifier 402 through a data bus. In this embodiment, the data bus includes a first data bus BL and a second data bus BLB, and the outputs of the first data bus BL and the second data bus BLB are opposite. The output end of the readout unit 401 is electrically connected to the non-inverting input end of the sense amplifier 402 through the first data bus BL, and the output end of the readout unit 401 is electrically connected to the inverting input end of the sense amplifier 402 through the second data bus BLB. The readout unit 401 inputs the read digital signal data to the non-inverting input end of the sense amplifier 402 through the first data bus BL, and inputs the read digital signal data to the inverting input end of the sense amplifier 402 through the second data bus BLB, and finally the digital signal data is correctly read out by the sense amplifier 402. In this embodiment, the number of bits of the ADC conversion output corresponding to the single pixel unit 110 is consistent with the number of the single column readout units 401 , and is consistent with the number of bits of the first data bus BL and the second data bus BLB, respectively.
[0041] See also Figure 2 As shown, the present invention provides a row data scanning readout circuit of an image sensor, the row scanning readout module 400 also includes a signal generating module 403, the input end of the signal generating module 403 is connected to the row scanning trigger signal HTRIG and the row scanning clock signal HCLK, and the output end of the signal generating module 403 is electrically connected to the input end of the readout unit 401, and the row scanning selection signal HSEL and the pre-charge reset signal PREC are generated by the signal generating module 403 to control the data reading of the readout unit 401, thereby controlling the accurate output of the data.
[0042] See also Figure 3 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the readout unit 401 includes a first selection transmission tube N1 and a second selection transmission tube N2. In this embodiment, the first selection transmission tube N1 and the second selection transmission tube N2 are set as NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) transistors. The source of the NMOS transistor N1 is electrically connected to the in-phase data output end of the row data latch 300, that is, the in-phase readout data DB is connected to the source of the first field effect transistor N1 after output. The source of the NMOS transistor N2 is electrically connected to the inverted data output end of the row data latch 300, that is, the inverted readout data DN is connected to the source of the NMOS transistor N2 after output. The gates of the NMOS transistor N1 and the NMOS transistor N2 are electrically connected to the row scan selection signal output end of the signal generation module 403, and are connected to the row scan selection signal HSEL, and the switches of the NMOS transistor N1 and the NMOS transistor N2 are controlled by the row scan selection signal HSEL. The drain of the NMOS transistor N1 is electrically connected to the first data bus BL, and the drain of the NMOS transistor N2 is electrically connected to the second data bus BLB, so that the in-phase readout data DB and the inverse readout data DN are read and output through the first data bus BL and the second data bus BLB respectively. It should be understood that, since there are multiple readout units 401, the row scan readout module 400 includes multiple NMOS transistors N1 and multiple NMOS transistors N2, and the output end of the NMOS transistor N1 is electrically connected to the first data bus BL, and the output end of the NMOS transistor N2 is electrically connected to the second data bus BLB.
[0043] See also Figure 3 As shown, the present invention provides a row data scanning readout circuit of an image sensor, and the readout unit 401 also includes a first pre-charge reset transistor P1 and a second pre-charge reset transistor P2. In this embodiment, the first pre-charge reset transistor P1 and the second pre-charge reset transistor P2 are set as (positive channel Metal Oxide Semiconductor, P-type metal oxide semiconductor) transistors. The source of the PMOS transistor P1 and the PMOS transistor P2 is connected to the power supply voltage VDD. The drain of the PMOS transistor P1 is electrically connected to the first data bus BL, the drain of the PMOS transistor P2 is electrically connected to the second data bus BLB, and the gates of the PMOS transistor P1 and the PMOS transistor P2 are electrically connected to the pre-charge reset signal output end of the signal generation module 403, and the pre-charge reset signal PREC is connected to control the reset of the first data bus BL and the second data bus BLB through the pre-charge reset signal PREC. In this embodiment, the pre-charge reset signal connected to each read-out unit 401 is the same, and the pre-charge reset signal will turn on the PMOS transistor P1 and the PMOS transistor P2 in the read-out unit when the row scan clock signal HCLK is at a low level in each cycle, so that the first data bus BL and the second data bus BLB are reset to the power supply voltage VDD.
[0044] See also Figure 3 As shown, the present invention provides a row data scanning readout circuit of an image sensor. If the in-phase readout data DB is, for example, 0 and the inverted readout data DN is, for example, 1, after any readout unit 401 is reset, if the row scan selection signal HSEL jumps to a high level, the NMOS transistor N1 is turned on and the NMOS transistor N2 is turned off. At this time, the voltage of the first data bus BL will gradually pull down to ground, and the second data bus BLB will continue to maintain the voltage at the time of reset. After the sensitive amplifier 402 compares the voltages of the first data bus BL and the second data bus BLB, the output is 0. If the in-phase readout data DB is, for example, 1 and the inverted readout data DN is, for example, 0, after any readout unit 401 is reset, if the row scan selection signal HSEL jumps to a high level, the NMOS transistor N1 is turned off and the NMOS transistor N2 is turned on. At this time, the voltage of the first data bus BL continues to maintain the voltage at the time of reset, and the second data bus BLB will gradually pull down to ground. After the sensitive amplifier 402 compares the voltages of the first data bus BL and the second data bus BLB, the output is 1. By comparing the output voltage of the data bus by the sense amplifier 402, accurate data reading is completed.
[0045] See also Figure 4 As shown, the present invention provides a row data scanning readout circuit of an image sensor, the signal generating module 403 includes a plurality of triggers DFF, and the plurality of triggers DFF are electrically connected, that is, the signal generating module 403 adopts a DFF chain, and the front stage output is connected to the rear stage input. Figure 4 As shown, in this embodiment, the input terminal D of the first flip-flop DFF0 is connected to the row scan trigger signal HTRIG, the clock interface terminal is connected to the row scan clock signal HCLK, the output terminal Q is electrically connected to the input terminal D of the second flip-flop DFF1 and the input terminal of the first AND gate 4031, and the output terminal Q of the first flip-flop DFF0 outputs Q1. The input terminal D of the second flip-flop DFF1 is connected to Q1, the clock interface terminal is connected to the row scan clock signal HCLKB, the output terminal Q is electrically connected to the input terminal D of the third flip-flop DFF2 and the input terminal of the first AND gate 4031, and the output terminal Q of the second flip-flop DFF1 outputs Q2. The input terminal D of the third flip-flop DFF2 is connected to Q2, the clock interface terminal is connected to the row scan clock signal HCLK, the output terminal Q is electrically connected to the input terminal D of the fourth flip-flop DFF4 and the input terminal of the second AND gate 4032, and the output terminal Q of the third flip-flop DFF2 outputs Q3. The input terminal D of the fourth trigger DFF3 is connected to Q3, the clock interface terminal is connected to the row scan trigger signal HCLK, the output terminal is electrically connected to the input terminal of the second AND gate 4032 and the input terminal D of the next level trigger, and the output terminal Q of the fourth trigger DFF3 outputs Q4. By analogy, the electrical connection and data transmission between multiple triggers DFF are realized. Among them, the row scan clock signals input by two adjacent triggers DFF are inverted, and the pre-charge reset signal PREC uses one of the row scan clock signals, that is, the inverted row scan clock signal HCLK is the row scan clock signal HCLKB, and the pre-charge reset signal PREC uses the row scan clock signal HCLKB. Specifically, the pre-charge reset signal PREC is, for example, PREC <0> ~PREC <n-1>The output ends of two adjacent flip-flops DFF are electrically connected to the input ends of the same AND gate, and the row scan selection signal HSEL is output through the AND gate. Specifically, Q1 and Q2 are input to the first AND gate 4031, and the row scan selection signal HSEL is output through the first AND gate 4031. <0> Q3 and Q4 are input into the second AND gate 4032, and the row scan selection signal HSEL is output through the second AND gate 4032. <1> By analogy, multiple row scan selection signals HSEL are generated, for example, HSEL <0> ~HSEL <n-1>.
[0046] See also Figure 5 As shown, the present invention provides a row data scanning readout circuit of an image sensor, which generates a row scanning selection signal HCLKB and a precharge reset signal PREC through a signal generation module 403, thereby controlling the readout unit 401 to read data. In this embodiment, the time interval between generating adjacent scanning selection signals HSEL is half a cycle, such as Figure 5 As shown, when the row scan trigger signal HTRIG jumps to a low level, and the row scan clock signal HCLK and the row scan trigger signal HCLKB successively jump to a high level, Q1 and Q2 are output, and at this time, HSEL is output through the first AND gate 4031. <0> After half a cycle, the row scan clock signal HCLK and the row scan trigger signal HCLKB jump to high level again, Q3 and Q4 are output, and HSEL is output through the second AND gate 4032. <1> And so on, until the output HSEL <n-1>Multiple row scan selection signals HSEL select each column readout unit 401 in turn, that is, the row scan selection signal HSEL <0> ~HSEL <n-1>The readout unit 401 is controlled to read data in sequence through the row scan selection signal HSEL.
[0047] See also Figure 6 As shown, the present invention provides a row data scanning readout circuit of an image sensor. When the row scanning clock signal HCLKB is at a low level, the precharge reset signal PREC is at a low level, and the data bus is reset, that is, the first data bus BL and the second data bus BLB corresponding to the 1-bit digital signal data converted and output by the ADC are reset. At this time, the row scanning selection signal HSEL input to the first column readout unit 401 is reset. <0> When the enable signal SAEN connected to the gate of the sense amplifier 402 is at a high level, the first data bus BL voltage V BL and the second data bus BLB voltage V BLB If V BL Greater than V BLB , then the sense amplifier 402 outputs D0, and D0 is high level 1. <0> When the enable is completed and the signal HSEL is changed to a low level, the first data bus BL and the second data bus BLB are reset to a high level. <1> When the enable signal SAEN connected to the gate of the sense amplifier 402 is high, the voltage of the first data bus BL is compared with the voltage V BL and the second data bus BLB voltage V BLB If V BL Less than V BLB , the sense amplifier 402 outputs D1, and D1 is low level 0. <1> When the enable is completed and the signal HSEL is changed to a low level, the first data bus BL and the second data bus BLB are reset to a high level. <2> When the enable signal SAEN connected to the gate of the sense amplifier 402 is at a high level, the first data bus BL voltage V BL and the second data bus BLB voltage V BLB If V BL Greater than V BLB , the sense amplifier 402 outputs D2, and D2 is high level 1. Similarly, the readout unit 401 inputs different row scan selection signals to read data, and compares the voltage difference between the first data bus BL and the second data bus BLB to complete accurate data reading.
[0048] See also Figure 7 As shown, the present invention provides a row data scanning readout circuit of an image sensor, wherein a sensitive amplifier 402 includes an amplifier stage, wherein the in-phase input terminal of the amplifier stage is electrically connected to the first data bus BL, and the inverting input terminal of the amplifier stage is electrically connected to the second data bus BLB. The amplifier stage of the sensitive amplifier 402 includes a first reset tube PM0, a second reset tube PM1, and a third reset tube PM4. The gate of the first reset tube PM0 is connected to a precharge reset signal PREC, the source of the first reset tube PM0 is electrically connected to the first data bus BL, and the drain of the first reset tube PM0 is electrically connected to the second data bus BLB. The gate of the second reset tube PM1 is connected to the precharge reset signal PREC, the source of the second reset tube PM1 is connected to the power supply voltage VDD, and the drain of the second reset tube PM1 is electrically connected to the first data bus BL. The gate of the third reset tube PM4 is connected to the precharge reset signal PREC, the source of the third reset tube PM4 is connected to the power supply voltage VDD, and the drain of the third reset tube PM4 is electrically connected to the second data line BLB. When the precharge reset signal PREC is at a low level, the first data bus BL and the second data bus BLB are reset to the power supply voltage VDD. The gate of transistor PM2 is connected to the enable signal SA_EN, the source of transistor PM2 is electrically connected to the connection point Q, and the drain of transistor PM2 is electrically connected to the first data bus BL. The gate of transistor PM3 is connected to the enable signal SA_EN, the source of transistor PM3 is electrically connected to the connection point QN, and the drain of transistor PM3 is electrically connected to the second data bus BLB. The amplification stage of the sense amplifier 402 also includes a positive feedback structure, which includes a transistor PM5, a transistor PM6, a transistor NM1, and a transistor NM2. The gate of transistor PM5 is electrically connected to the gate of transistor NM1, the source of transistor PM5 is electrically connected to the power supply voltage VDD, and the drain of transistor PM5 is electrically connected to the source of transistor NM1. The gate of transistor PM6 is electrically connected to the gate of transistor NM2, the source of transistor PM6 is connected to the power supply voltage VDD, and the drain of transistor PM6 is electrically connected to the source of transistor NM2. The gate of transistor NM0 is connected to the enable signal SA_EN, the source of transistor NM0 is electrically connected to the sources of transistors NM1 and NM2, and the drain of transistor NM0 is grounded.
[0049] See also Figure 8 As shown, the present invention provides a row data scanning readout circuit of an image sensor, wherein the sensitive amplifier 402 further includes a latch stage, and the input end of the latch stage is electrically connected to the output end of the amplifier stage. The latch stage of the sensitive amplifier 402 includes a transistor PM0, a transistor PM3, a transistor NM0, and a transistor NM3. The gates of the transistor PM0 and the transistor NM0 are connected to the latch output Q, and the gates of the transistor PM3 and the transistor NM3 are connected to the latch output QN. The latch stage of the sensitive amplifier 402 includes a strong positive feedback structure, and the strong positive feedback structure includes a transistor PM1, a transistor PM2, a transistor NM1, and a transistor NM2. The drain of PM0 is electrically connected to the drain DOUTN of the transistor PM1 and the transistor NM1, and the drain of the transistor PM3 is electrically connected to the drain DOUT of the transistor PM2 and the transistor NM2. The source of the transistor PM1 and the transistor PM2 is connected to the power supply voltage VDD, and the source of the transistor NM0 and the transistor NM3 is grounded.
[0050] See also Fig. 9 As shown, the present invention provides a row data scanning readout circuit of an image sensor. After the enable signal SA_EN of the sensitive amplifier 402 arrives, the voltage of the first data bus BL and the second data bus BLB is amplified by the amplifier stage. In this embodiment, when the voltage difference between the first data bus BL and the second data bus BLB is, for example, 200mv, the sensitive amplifier 402 can accurately amplify and read the data. At the same time, the data output by the amplifier stage is latched by the latch stage, so that when the amplifier stage is reset, the sensitive amplifier 402 can keep the data read output. Figure 7 As shown, when the enable signal SA_EN is at a low level, transistors PM2 and PM3 are turned on, and the voltage at the connection point Q and the voltage at the connection point QN follow the changes of the voltage of the first data bus BL and the voltage of the second data bus BLB, respectively. When the enable signal SA_EN jumps to a high level, transistors PM2 and PM3 are cut off and disconnected, transistor NM0 is turned on, and the source voltages of transistors NM1 and NM2 are pulled down to ground. At this time, positive feedback of transistors PM5, PM6, NM1, and NM2 is established, and the voltage at the connection point QN is quickly pulled down to ground. The latch stage receives the output of the amplifier stage, such as Figure 8 As shown, at this time, the latch stage input Q is 1 and the input QN is 0. Transistor NM0 and transistor PM3 are turned on, DOUT is pulled up to a high level, and DOUTN is pulled down to a low level, that is, DOUT is 1 and QOUTN is 0. At the same time, after comparing the voltage difference between the first data bus BL and the second data bus BLB, the read data is accurately output through the latch 402. Subsequently, when the precharge reset signal PREC jumps to a low level, the data bus and the sense amplifier 402 are reset, and the voltages of the first data bus BL and the second data bus BLB jump to a high level. At this time, the enable signal SA_EN is at a low level, as shown in FIG. Figure 7 As shown, transistor PM2 and transistor PM3 are turned on, and the voltages at connection points Q and QN are high. The latch stage receives the output of the amplifier stage, such as Figure 8 As shown, transistors NM0 and NM3 are turned on, strong positive feedback of transistors PM1, PM2, NM1 and NM2 is established, and DOUT and DOUTN remain unchanged, that is, DOUT is 1 and QOUTN is 0. In this embodiment, the reset can be completed on the first data bus BL and the second data bus BLB without the participation of the readout unit 401. After the reset is completed, the next cycle data reading is continued. By analogy, the voltage values of the first data bus BL and the second data bus BLB are compared, and finally the read data is accurately output through the output end of the sense amplifier 402.
[0051] In summary, the row data scanning readout circuit of an image sensor provided by the present invention includes a row scanning readout module 400, and the input end of the row scanning readout module 400 is electrically connected to the output end of the row latch 300, so as to read the digital signal data. Among them, the row scanning readout module 400 includes a plurality of readout units 401, and the readout unit 401 sequentially reads the in-phase readout data DB and the inverse readout data DN output by the row data latch 300 of the corresponding column. The row scanning readout module 400 includes a signal generation module 403, and the precharge reset signal PREC and the row scanning selection signal HSEL are generated by the signal generation module 403, and the generated signals are sequentially input into the readout unit 401 of the corresponding column, so as to control the readout unit 401 to output the voltage through the first data bus BL and the second data bus BLB. Finally, the voltage difference between the first data bus BL and the second data bus BLB with opposite outputs is compared by the sensitive amplifier 402, and the accurate output of the read data is completed. In this embodiment, since the first data bus BL and the second data bus BLB with opposite outputs are provided, it is not necessary for the data waveform on the bus to reach the swing of the power supply and the ground and have a good rise and fall time, and only the voltage difference between the first data bus BL and the second data bus BLB needs to be compared to realize accurate data reading. At the same time, the circuit structure is simple, and the chip area and power consumption are reduced when transmitting over a large array and a long distance.
[0052] In the description of this specification, the description with reference to the terms "this embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0053] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A row data scanning readout circuit of an image sensor, characterized in that: include: A pixel array, the pixel array comprising a plurality of pixel units, and the pixel array outputs an electrical signal; An electrical signal conversion module, wherein an input end of the electrical signal conversion module is electrically connected to an output end of the pixel unit, and the electrical signal conversion module outputs digital image data; A row data latch, wherein an input end of the row data latch is electrically connected to an output end of the electrical signal conversion module, and the row data latch outputs in-phase readout data and inverted readout data; A row scanning readout module, wherein the row scanning readout module comprises a plurality of readout units, and an input end of the readout unit is electrically connected to an output end of the row data latch; as well as A sense amplifier, wherein the output end of the readout unit is electrically connected to a non-inverting input end of the sense amplifier through a first data bus, and is electrically connected to an inverting input end of the sense amplifier through a second data bus, and a voltage difference between the first data bus and the second data bus is compared through the sense amplifier; The sensitive amplifier comprises an amplifier stage and a latch stage, the in-phase input terminal of the amplifier stage is electrically connected to the first data bus, the inverting input terminal of the amplifier stage is electrically connected to the second data bus, and the output terminal of the amplifier stage is electrically connected to the input terminal of the latch stage; The amplifier stage includes a first reset tube, a second reset tube and a third reset tube, the source of the first reset tube is electrically connected to the first data bus, the drain of the first reset tube is electrically connected to the second data bus, the gate of the first reset tube is connected to a precharge reset signal, the sources of the second reset tube and the third reset tube are connected to a voltage power supply, the gates of the second reset tube and the third reset tube are connected to a precharge reset signal, the drain of the second reset tube is electrically connected to the first data bus, and the drain of the third reset tube is electrically connected to the second data bus.
2. The row data scanning readout circuit of an image sensor according to claim 1, characterized in that: The row scanning readout module further includes a signal generating module, and an output end of the signal generating module is electrically connected to an input end of the readout unit.
3. The row data scanning readout circuit of an image sensor according to claim 2, characterized in that: The signal generation module outputs a row scanning selection signal and a precharge reset signal.
4. The row data scanning readout circuit of an image sensor according to claim 3, characterized in that: The read-out unit includes a first selection transfer transistor, a source of the first selection transfer transistor is electrically connected to the in-phase data output terminal of the row data latch, a drain of the first selection transfer transistor is electrically connected to the first data bus, and a gate of the first selection transfer transistor is electrically connected to the row scan selection signal output terminal of the signal generating module.
5. The row data scanning readout circuit of an image sensor according to claim 3, characterized in that: The read-out unit also includes a second selection transfer transistor, a source of the second selection transfer transistor is electrically connected to the inverting data output terminal of the row data latch, a drain of the second selection transfer transistor is electrically connected to the second data bus, and a gate of the second selection transfer transistor is electrically connected to the row scan selection signal output terminal of the signal generating module.
6. The row data scanning readout circuit of an image sensor according to claim 3, characterized in that: The read-out unit also includes a first pre-charge reset transistor, a source of the first pre-charge reset transistor is connected to a voltage power supply, a drain of the first pre-charge reset transistor is electrically connected to the first data bus, and a gate of the first pre-charge reset transistor is electrically connected to a pre-charge reset signal output terminal of the signal generating module.
7. The row data scanning readout circuit of an image sensor according to claim 3, characterized in that: The read-out unit also includes a second pre-charge reset transistor, a source of the second pre-charge reset transistor is connected to a voltage power supply, a drain of the second pre-charge reset transistor is electrically connected to the second data bus, and a gate of the second pre-charge reset transistor is electrically connected to a pre-charge reset signal output terminal of the signal generating module.
8. The row data scanning and reading circuit of an image sensor according to claim 2, characterized in that: The signal generating module includes a plurality of triggers, and the output ends of the triggers are electrically connected to the input ends of the AND gates.
9. An image sensor, characterized in that: A row data scanning readout circuit comprising the image sensor as claimed in claim 1.