A flash memory unit structure and manufacturing method thereof
By forming isolation trenches and separating source lines in the flash memory cell structure, and controlling the floating gate conductive layer with different word lines, the problem of chip miniaturization is solved, and the size reduction and storage effect of the flash memory cell are achieved.
Patent Information
- Application Number
- CN202111139233.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-26
- Publication Date
- 2025-08-22
- Estimated Expiration
- 2041-09-26
AI Technical Summary
In the existing flash memory cell structure, the chip is difficult to shrink, resulting in limited storage capacity and the shared source line causing the chip size to be larger.
The isolation trench is formed in the substrate and the isolation layer is filled, the separating source lines are independent first source lines and second source lines, and the first floating gate conductive layer and the second floating gate conductive layer are controlled respectively through different word lines to improve space utilization efficiency.
The flash memory unit structure is miniaturized, the chip size is reduced, the storage effect is improved, and the space utilization is improved.
Smart Images
Figure CN115942745B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing and relates to a flash memory unit structure and a manufacturing method thereof. Background Art
[0002] With technological advancements, the requirements for storage capacity and read / write speeds in various mobile devices are becoming increasingly stringent, making the disadvantages of conventional memory increasingly apparent. Flash memory (Flash Memory) has gained popularity among users due to its fast read / write speeds, large storage capacity, compact size, light weight, low power consumption, and resistance to damage.
[0003] A flash memory cell typically consists of a word line, a floating gate (FG), a source line, and a bit line. Writing and erasing the flash memory is accomplished by controlling the floating gate in conjunction with the word line, source line, and bit line. Even in the absence of power, the floating gate allows the flash memory to store data for a long time.
[0004] Existing flash memory cell structures usually share source lines, which makes chip miniaturization difficult. This results in a larger chip size during integration, greatly limiting the storage capacity of the flash memory chip per unit area.
[0005] Therefore, there is an urgent need to find a method for manufacturing a flash memory cell that can be miniaturized and smaller in size under existing processes. Summary of the Invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a flash memory cell structure and a manufacturing method thereof, so as to solve the problem in the prior art that the chip is difficult to miniaturize and has a large size.
[0007] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing a flash memory cell structure, comprising the following steps:
[0008] Providing a substrate, and forming a gate dielectric layer, a floating gate conductive layer, and a first mask layer on the substrate in order from bottom to top;
[0009] forming an isolation trench, wherein the isolation trench vertically penetrates the first mask layer, the floating gate conductive layer, and the gate dielectric layer and extends into the substrate;
[0010] forming an isolation layer in the isolation trench, and forming a first opening and a second opening in the first mask layer, wherein the first opening and the second opening are located on opposite sides of the isolation layer and expose sidewalls of the isolation layer;
[0011] forming a first insulating layer at the bottom of the first opening, and forming a second insulating layer at the bottom of the second opening;
[0012] removing the first mask layer and removing the portion of the floating gate conductive layer not blocked by the first insulating layer and the second insulating layer to obtain a first floating gate conductive layer and a second floating gate conductive layer located on opposite sides of the isolation layer;
[0013] forming a word line conductive layer covering the first insulating layer, the second insulating layer and the isolation layer, and patterning the word line conductive layer to obtain at least two word lines;
[0014] A first source line and a second source line are formed in the substrate, wherein the first source line and the second source line are located at opposite sides of the isolation layer and contact the sidewall of the isolation layer.
[0015] Optionally, forming the isolation trench includes the following steps:
[0016] forming an anti-reflective layer and a first photoresist layer on the first mask layer in sequence from bottom to top, patterning the first photoresist layer, and patterning the first mask layer based on the patterned first photoresist layer;
[0017] The first photoresist layer and the anti-reflection layer are removed in sequence, and the isolation trench is formed based on the patterned first mask layer.
[0018] Optionally, forming the first opening and the second opening in the first mask layer includes the following steps:
[0019] forming a second photoresist layer on the first mask layer, and patterning the second photoresist layer;
[0020] The first mask layer is etched based on the patterned second photoresist layer until the floating gate conductive layer is exposed to form the first opening and the second opening, and the top surface of the isolation layer is still higher than the top surface of the first mask layer.
[0021] Optionally, the method further includes forming an isolation sidewall, wherein the isolation sidewall is located on a side of the first floating gate conductive layer away from the isolation layer and a side of the second floating gate conductive layer away from the isolation layer, and the word line conductive layer also covers the side of the isolation sidewall.
[0022] Optionally, the first source line and the second source line are formed by using a patterned photoresist layer as a mask and performing ion implantation and annealing after resist stripping.
[0023] Optionally, the method further includes forming a first bit line and a second bit line in the substrate, wherein the first bit line and the first source line are located on the same side of the isolation layer and are spaced apart, and the second bit line and the second source line are located on the same side of the isolation layer and are spaced apart.
[0024] Optionally, the first bit line and the second bit line are formed by ion implantation and annealing after resist stripping using a patterned photoresist layer as a mask layer.
[0025] Optionally, patterning the word line conductive layer includes: forming a word line opening in the word line conductive layer, the word line opening simultaneously exposing the first insulating layer, the isolation layer and the second insulating layer; or forming at least two word line openings in the word line conductive layer, one word line opening exposing the first insulating layer, and the other word line opening exposing the second insulating layer; or forming at least three word line openings in the word line conductive layer, wherein the three word line openings respectively expose the first insulating layer, the isolation layer and the second insulating layer.
[0026] The present invention also provides a flash memory unit structure, comprising:
[0027] substrate;
[0028] an isolation layer, wherein a bottom portion of the isolation layer is embedded in the substrate and a top surface of the isolation layer is higher than a top surface of the substrate;
[0029] a gate dielectric layer, located on the upper surface of the substrate;
[0030] a first floating gate conductive layer and a second floating gate conductive layer, located on the gate dielectric layer and distributed on opposite sides of the isolation layer, and the first floating gate conductive layer and the second floating gate conductive layer are in contact with two side walls of the isolation layer respectively;
[0031] A first insulating layer and a second insulating layer are respectively located on the first floating gate conductive layer and the second floating gate conductive layer;
[0032] The first source line and the second source line are located in the substrate and distributed on two opposite sides of the isolation layer, and the first source line and the second source line are respectively in contact with two side walls of the isolation layer.
[0033] The word line conductive layer includes at least two word lines, at least one of the word lines contacts the first insulating layer, and at least one of the word lines contacts the second insulating layer.
[0034] Optionally, isolation sidewalls are provided on a side of the first floating gate conductive layer and a side of the second floating gate conductive layer away from the isolation layer, and the word line conductive layer covers the isolation sidewalls.
[0035] Optionally, the first insulating layer includes a LOCOS oxide layer, and the second insulating layer includes a LOCOS oxide layer.
[0036] Optionally, the flash memory cell structure further includes a first bit line and a second bit line located in the substrate, the first bit line and the first source line are located on the same side of the isolation layer and are spaced apart, and the second bit line and the second source line are located on the same side of the isolation layer and are spaced apart.
[0037] Optionally, the first floating gate conductive layer and the second floating gate conductive layer are respectively controlled by different word lines.
[0038] As described above, a flash memory cell structure and a manufacturing method thereof of the present invention form an isolation trench in a substrate and fill an isolation gate dielectric layer so that the source line becomes two independent source lines, a first source line and a second source line. At the same time, through the design of the word line, different word lines can separately control the first floating gate conductive layer and the second floating gate conductive layer, thereby improving space utilization efficiency and reducing the size of the flash memory cell, thereby miniaturizing the flash memory chip and making the chip smaller, which has high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 Shown is a schematic diagram of the cross-sectional structure of a flash memory cell.
[0040] Figure 2 Shown is a flow chart of a method for manufacturing a flash memory cell structure according to the present invention.
[0041] Figure 3 A schematic diagram illustrating patterning a first photoresist layer in a method for fabricating a flash memory cell structure according to the present invention is shown.
[0042] Figure 4 A schematic diagram showing the formation of isolation trenches in the method for manufacturing a flash memory cell structure according to the present invention is shown.
[0043] Figure 5 It is a schematic diagram showing the removal of the first photoresist layer and the anti-reflective layer in the method for manufacturing the flash memory cell structure of the present invention.
[0044] Figure 6 It is a schematic diagram showing the formation of an isolation layer in the method for manufacturing a flash memory cell structure of the present invention.
[0045] Figure 7 A schematic diagram showing patterning of the second photoresist layer in the method for manufacturing a flash memory cell structure of the present invention is shown.
[0046] Figure 8 A schematic diagram showing a method for fabricating a flash memory cell structure of the present invention, wherein a first opening and a second opening are formed in a first mask layer.
[0047] Figure 9 It is a schematic diagram showing the formation of the first insulating layer and the second insulating layer in the method for manufacturing the flash memory cell structure of the present invention.
[0048] Figure 10 It is a schematic diagram showing the formation of a first floating gate conductive layer and a second floating gate conductive layer in the method for manufacturing a flash memory cell structure of the present invention.
[0049] Figure 11 It is a schematic diagram showing the method for manufacturing a flash memory cell structure of the present invention to form a word line conductive layer.
[0050] Figure 12 A schematic diagram showing a word line structure formed by the method for manufacturing a flash memory cell structure of the present invention is shown.
[0051] Figure 13 A schematic diagram showing another word line structure formed by the method for manufacturing a flash memory cell structure of the present invention is shown.
[0052] Figure 14 A schematic diagram showing a third word line structure formed by the method for manufacturing a flash memory cell structure of the present invention is shown.
[0053] Component number description
[0054] 11 substrate
[0055] 111 Source line
[0056] 112 bit lines
[0057] 12 Gate dielectric layer
[0058] 121 insulation layer
[0059] 13 Floating Gate
[0060] 14-character line
[0061] Steps S1 to S7
[0062] 21 substrate
[0063] 211 Isolation Trench
[0064] 2111 Isolation Layer
[0065] 2121 First source line
[0066] 2122 Second source line
[0067] 2131 First Line
[0068] 2132 Second bit line
[0069] 22 Gate dielectric layer
[0070] 23 floating gate conductive layer
[0071] 231 First Opening
[0072] 232 Second Opening
[0073] 2331 First floating gate conductive layer
[0074] 2332 second floating gate conductive layer
[0075] 2341 First Insulation Layer
[0076] 2342 Second insulation layer
[0077] 235 Isolation Side Wall
[0078] 24 First mask layer
[0079] 25 Anti-reflective layer
[0080] 26 First photoresist layer
[0081] 27 Second photoresist layer
[0082] 28 word line conductive layer
[0083] 281 word line opening
[0084] 282 word lines DETAILED DESCRIPTION
[0085] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0086] See also Figures 1 to 14 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.
[0087] like Figure 1 FIG. 1 is a schematic diagram showing a cross-sectional structure of a flash memory cell, which includes a substrate 11, a source line 111, a bit line 112, a gate dielectric layer 12, a floating gate 13, an insulating layer 121 and a word line 14. Figure 1Flash memory cells share a single source line, resulting in a large structure and difficulty in miniaturizing the integrated flash memory chip. Consequently, the flash memory chip integrated with the flash memory cells is relatively large. To address this problem, the present invention improves it through a novel process flow design. The technical solution of the present invention is illustrated below through specific embodiments.
[0088] Example 1
[0089] This embodiment provides a method for manufacturing a flash memory cell structure. Figure 2 , which is a flow chart showing a method for manufacturing the flash memory cell structure, comprising the following steps:
[0090] S1: providing a substrate, and forming a gate dielectric layer, a floating gate conductive layer, and a first mask layer on the substrate in order from bottom to top;
[0091] S2: forming an isolation trench, wherein the isolation trench vertically penetrates the first mask layer, the floating gate conductive layer, and the gate dielectric layer and extends into the substrate;
[0092] S3: forming an isolation layer in the isolation trench, and forming a first opening and a second opening in the first mask layer, wherein the first opening and the second opening are located on opposite sides of the isolation layer and expose sidewalls of the isolation layer;
[0093] S4: forming a first insulating layer at the bottom of the first opening, and forming a second insulating layer at the bottom of the second opening;
[0094] S5: removing the first mask layer and removing the portion of the floating gate conductive layer not blocked by the first insulating layer and the second insulating layer to obtain a first floating gate conductive layer and a second floating gate conductive layer located on opposite sides of the isolation layer;
[0095] S6: forming a word line conductive layer covering the first insulating layer, the second insulating layer and the isolation layer, and patterning the word line conductive layer to obtain at least two word lines;
[0096] S7: forming a first source line and a second source line in the substrate, wherein the first source line and the second source line are located on opposite sides of the isolation layer and contact sidewalls of the isolation layer.
[0097] First see Figures 3 to 5 , perform step S1 and step S2: provide a substrate 21, and form a gate dielectric layer 22, a floating gate conductive layer 23 and a first mask layer 24 on the substrate 21 from bottom to top; form an isolation trench 211, and the isolation trench 211 vertically penetrates the first mask layer 24, the floating gate conductive layer 23 and the gate dielectric layer 22, and extends into the substrate 21.
[0098] Specifically, the method of forming the gate dielectric layer 22 includes one of chemical vapor deposition and thermal oxidation or other suitable methods; the method of forming the floating gate conductive layer 23 includes chemical vapor deposition or other suitable methods; the method of forming the first mask layer 24 includes chemical vapor deposition or other suitable methods, wherein the material of the gate dielectric layer 22 may include silicon oxide, the material of the floating gate conductive layer may include polysilicon, and the material of the first mask layer may include silicon nitride.
[0099] As an example, forming the isolation trench 211 includes the following steps:
[0100] like Figure 3 As shown, an anti-reflection layer 25 and a first photoresist layer 26 are sequentially formed on the first mask layer 24 from bottom to top, and the first photoresist layer 26 is patterned to obtain an opening pattern defining the isolation trench. The anti-reflection layer 25 includes an organic anti-reflection layer or an inorganic anti-reflection layer, or may be other suitable anti-reflection layers. The anti-reflection layer 25 may be formed by spin coating or other suitable methods; the first photoresist layer 26 may be formed by spin coating or other suitable methods.
[0101] like Figure 4 As shown, the anti-reflective layer 25 and the first mask layer 24 are patterned in sequence based on the patterned first photoresist layer 26, and the floating gate conductive layer 23, the gate dielectric layer 22, and the substrate 21 are etched in sequence based on the patterned first mask layer 24 to form the isolation trench 211, with the bottom of the isolation trench 211 located in the substrate 21. The method of patterning the first mask layer 24, etching the floating gate conductive layer, etching the gate dielectric layer 22, and etching the substrate 21 includes dry etching or other suitable methods.
[0102] Specifically, such as Figure 5 As shown, the first photoresist layer 26 and the anti-reflection layer 25 are removed in sequence.
[0103] Specifically, after removing the anti-reflection layer 25 , the upper surface of the first mask layer 24 needs to be wet cleaned to remove the residue of the anti-reflection layer 25 and other contaminants on the surface of the first mask layer 24 .
[0104] Then see Figures 6 to 8 , perform step S3: form an isolation layer 2111 in the isolation trench 211, and form a first opening 231 and a second opening 232 in the first mask layer 24, the first opening 231 and the second opening 232 are located on opposite sides of the isolation layer 2111 and expose the sidewalls of the isolation layer 2111.
[0105] As an example, a method of forming the isolation layer 2111 includes chemical vapor deposition or other suitable methods.
[0106] Specifically, such as Figure 6 As described above, the isolation layer 2111 is formed in the isolation groove 211, and after the isolation layer 2111 is formed, the isolation layer 2111 on the upper surface of the first mask layer 24 needs to be removed, wherein the method of removing the isolation layer 2111 on the upper surface of the first mask layer 24 includes chemical mechanical polishing or other suitable methods.
[0107] As an example, forming the first opening 231 and the second opening 232 in the first mask layer 24 includes the following steps:
[0108] like Figure 7 As shown, a second photoresist layer 27 is formed on the first mask layer 24 and the second photoresist layer 27 is patterned. The method of forming the second photoresist layer 27 includes spin coating or other suitable methods.
[0109] like Figure 8 As shown, the first mask layer 24 is etched based on the patterned second photoresist layer 27, and the isolation layer 2111 is retained until the floating gate conductive layer 23 is exposed to form the first opening 231 and the second opening 232. The method for removing the first mask layer 24 includes wet etching or other suitable methods.
[0110] Specifically, the first opening 231 and the second opening 232 are opened vertically upwards, that is, the sidewall of the first opening 231 is perpendicular to the bottom surface of the first opening 231 , and the sidewall of the second opening 232 is perpendicular to the bottom surface of the second opening 232 .
[0111] As an example, the bottom surfaces of the first opening 231 and the second opening 232 both expose the floating gate conductive layer 23 .
[0112] Then see Figure 9 , performing step S4: forming a first insulating layer 2341 at the bottom of the first opening 231 , and forming a second insulating layer 2342 at the bottom of the second opening 232 .
[0113] Specifically, the method of forming the first insulating layer 2341 at the bottom of the first opening 231 includes a local oxidation isolation method of silicon. Silicon, referred to as LOCOS) or other suitable methods; the method of forming the second insulating layer 2342 at the bottom of the second opening 232 includes LOCOS or other suitable methods.
[0114] Then see Figure 10 , perform step S5: remove the first mask layer 24, and remove the portion of the floating gate conductive layer 23 that is not blocked by the first insulating layer 2341 and the second insulating layer 2342 to obtain a first floating gate conductive layer 2331 and a second floating gate conductive layer 2332 located on opposite sides of the isolation layer 211.
[0115] Specifically, the method of removing the first mask layer 24 includes wet etching or other suitable methods.
[0116] Specifically, a self-alignment process or other suitable methods are used to remove the portion of the floating gate conductive layer 23 that is not blocked by the first insulating layer 2341 and the second insulating layer 2342 .
[0117] See also Figures 11 to 14 , perform step S6 and step S7: form a word line conductive layer 28 covering the first insulating layer 2341, the second insulating layer 2342 and the isolation layer 2111, and pattern the word line conductive layer 28 to obtain at least two word lines 282; form a first source line 2121 and a second source line 2122 in the substrate 21, and the first source line 2121 and the second source line 2122 are located on opposite sides of the isolation layer 2111 and contact the side wall of the isolation layer 2111.
[0118] Specifically, such as Figure 11 As shown, it also includes a step of forming an isolation sidewall 235, wherein the isolation sidewall 235 is located on a side of the first floating gate conductive layer 2331 away from the isolation layer 2111 and a side of the second floating gate conductive layer 2332 away from the isolation layer 2111, and the word line conductive layer 28 also covers the side of the isolation sidewall 235.
[0119] Specifically, the method of forming the isolation spacer 235 includes thermal oxidation or other suitable methods.
[0120] Specifically, the word line conductive layer 28 is formed by chemical vapor deposition or other suitable methods. In this embodiment, the word line conductive layer 28 also covers the isolation spacer 235 .
[0121] As an example, a patterned photoresist layer (not shown) is used as a mask layer to form the first source line 2121 and the second source line 2122 through ion implantation and subsequent annealing after stripping. In this embodiment, a patterned photoresist layer covering the word line conductive layer 28, the gate dielectric layer 22, and the surface of the substrate 21 is used as a mask layer to implant ions into the substrate 21, strip the photoresist layer, and then perform annealing to form the first source line 2121 and the second source line 2122. The first source line 2121 and the second source line 2122 are located at the lateral edges (not shown) of the word line conductive layer 28.
[0122] As an example, the step of forming a first bit line 2131 and a second bit line 2132 in the substrate 21 is also included, the first bit line 2131 and the first source line 2121 are located on the same side of the isolation layer 2111 and are spaced apart, and the second bit line 2132 and the second source line 2122 are located on the same side of the isolation layer 2111 and are spaced apart.
[0123] As an example, the first bit line 2131 and the second bit line 2132 may be formed in the same manner as the first source line and the second source line 2122, that is, the first bit line 2131 and the second bit line 2132 are formed by ion implantation and annealing after de-bonding using a patterned photoresist layer as a mask layer, wherein the first bit line 2131 and the second bit line 2132 are formed synchronously, and the first source line 2121 and the second source line 2122 are formed synchronously, and the bit lines and source lines may be formed successively.
[0124] As an example, Figure 12 As shown, patterning the word line conductive layer 28 to obtain at least two word lines includes forming a word line opening 281 in the word line conductive layer 28 , wherein the word line opening 281 simultaneously exposes the first insulating layer 2341 , the isolation layer 2111 and the second insulating layer 2342 .
[0125] As an example, Figure 13 As shown, in another embodiment, patterning the word line conductive layer 28 to obtain at least two word lines includes: forming at least two word line openings 281 in the word line conductive layer 28, one word line opening 281 exposing the first insulating layer 2341, and the other word line opening 281 exposing the second insulating layer 2342.
[0126] As an example, in another embodiment, patterning the word line conductive layer 28 to obtain at least two word lines includes: forming at least three word line openings 281 in the word line conductive layer 28, wherein the three word line openings 281 respectively expose the first insulating layer 2341, the isolation layer 2111 and the second insulating layer 2342.
[0127] In the method for manufacturing a flash memory cell of the present embodiment, the process steps for manufacturing the flash memory cell are redesigned to form the isolation trench 211 in the substrate 21, fill the isolation layer 2111 in the isolation trench 211, and implant doping particles on both sides of the isolation layer 2111 to form an independent first source line 2121 and an independent second source line 2122.
[0128] Example 2
[0129] This embodiment provides a flash memory unit structure, see Figures 12 to 14 , showing three cases of the cross-sectional structural schematic diagram of the structure, including a substrate 21, an isolation layer 2111, a gate dielectric layer 22, a first floating gate conductive layer 2331, a second floating gate conductive layer 2332, a first insulating layer 2341, a second insulating layer 2342, a first source line 2121, a second source line 2122 and a word line conductive layer 28, wherein the bottom of the isolation layer 211 is embedded in the substrate 21, and the top surface of the isolation layer 2111 is higher than the top surface of the substrate 21; the gate dielectric layer 22 is located on the upper surface of the substrate 21; the first floating gate conductive layer 2331 and the second floating gate conductive layer 2332 are located on the gate dielectric layer 22 and distributed on opposite sides of the isolation layer 2111, and the first floating gate conductive layer 2331 and the second floating gate conductive layer 2332 are in contact with the two side walls of the isolation layer 2111 respectively; the first insulating layer 2341 and the second insulating layer 2342 are respectively located on the first floating gate conductive layer 2331 and the second floating gate conductive layer 2332; the first source line 2121 and the second source line 2122 are located in the substrate 21 and distributed on the opposite sides of the isolation layer 2111, and the first source line 2121 and the second source line 2122 are in contact with the two side walls of the isolation layer 2111 respectively; the word line conductive layer 28 includes at least two word lines 282, at least one of the word lines is in contact with the first insulating layer 2341, and at least one of the word lines is in contact with the second insulating layer 2342.
[0130] As an example, the first floating gate conductive layer 2331 and the second floating gate conductive layer 2332 are both provided with the isolation spacer 235 on one side away from the isolation layer, and the word line conductive layer 28 also covers the isolation spacer 235 .
[0131] As an example, the first insulating layer 2341 includes a LOCOS oxide layer or other suitable isolation layers, and the second insulating layer 2342 includes a LOCOS oxide layer or other suitable isolation layers.
[0132] As an example, the flash memory cell structure also includes a first bit line 2131 and a second bit line 2132 located in the substrate, the first bit line 2131 and the first source line 2121 are located on the same side of the isolation layer 2111 and are spaced apart, and the second bit line 2132 and the second source line 2122 are located on the same side of the isolation layer 2111 and are spaced apart.
[0133] Specifically, the word line conductive layer 28 also extends above the first bit line 2131 and the second bit line 2132 .
[0134] As an example, the first floating gate conductive layer 2331 and the second floating gate conductive layer 2332 are respectively controlled by different word lines 282. In this embodiment, the first floating gate conductive layer 2331 and the second floating gate conductive layer 2332 are respectively controlled by different word lines 282 to improve space utilization efficiency and reduce the size of the flash memory cell. By coordinating the voltage values of the word line 282, the first source line 2121, the second source line, the first bit line 2131, and the second bit line 2132, the writing and erasing of information in the flash memory chip are better controlled.
[0135] In the flash memory unit structure of this embodiment, the isolation layer 211 is set on the substrate 21 to separate the source line into the first source line 2121 and the second source line 2122, and then the word line 282 controls the first floating gate conductive layer 2331 and the second floating gate conductive layer 2332 separately, so as to improve the space utilization efficiency, enhance the storage effect of the flash memory unit, and reduce the size of the flash memory unit.
[0136] In summary, the flash memory cell structure and fabrication method of the present invention redesign the flash memory cell structure and fabrication method. An isolation layer is formed in the substrate to isolate the source lines, thereby separating the source lines into independent first and second source lines. Word line openings are then formed in the word line conductive layer, allowing the formed word lines to independently control the first and second floating gate conductive layers. This improves space utilization efficiency, reduces the size of the flash memory cell, and achieves the goal of reducing the size of the flash memory chip while maintaining the same capacity. This also improves the storage efficiency of the flash memory cell. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0137] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A method for manufacturing a flash memory cell structure, characterized in that: The following steps are involved: Providing a substrate, and forming a gate dielectric layer, a floating gate conductive layer, and a first mask layer on the substrate in order from bottom to top; forming an isolation trench, wherein the isolation trench vertically penetrates the first mask layer, the floating gate conductive layer, and the gate dielectric layer and extends into the substrate; forming an isolation layer in the isolation trench, and forming a first opening and a second opening in the first mask layer, wherein the first opening and the second opening are located on opposite sides of the isolation layer and expose sidewalls of the isolation layer; forming a first insulating layer at the bottom of the first opening, and forming a second insulating layer at the bottom of the second opening; removing the first mask layer and removing the portion of the floating gate conductive layer not blocked by the first insulating layer and the second insulating layer to obtain a first floating gate conductive layer and a second floating gate conductive layer located on opposite sides of the isolation layer; forming a word line conductive layer covering the first insulating layer, the second insulating layer and the isolation layer, and patterning the word line conductive layer to obtain at least two word lines; A first source line and a second source line are formed in the substrate, wherein the first source line and the second source line are located at opposite sides of the isolation layer and contact the sidewall of the isolation layer.
2. The method for manufacturing a flash memory cell structure according to claim 1, wherein: Forming the isolation trench comprises the following steps: forming an anti-reflective layer and a first photoresist layer on the first mask layer in sequence from bottom to top, patterning the first photoresist layer, and patterning the first mask layer based on the patterned first photoresist layer; The first photoresist layer and the anti-reflection layer are removed in sequence, and the substrate is etched based on the patterned first mask layer to form the isolation trench.
3. The method for manufacturing a flash memory cell structure according to claim 1, wherein: Forming the first opening and the second opening in the first mask layer includes the following steps: forming a second photoresist layer on the first mask layer, and patterning the second photoresist layer; The first mask layer is etched based on the patterned second photoresist layer until the floating gate conductive layer is exposed to form the first opening and the second opening, and the top surface of the isolation layer is still higher than the top surface of the first mask layer.
4. The method for manufacturing a flash memory cell structure according to claim 1, wherein: The method further includes forming an isolation sidewall, wherein the isolation sidewall is located on a side of the first floating gate conductive layer away from the isolation layer and a side of the second floating gate conductive layer away from the isolation layer, and the word line conductive layer also covers the side of the isolation sidewall.
5. The method for manufacturing a flash memory cell structure according to claim 1, wherein: The first source line and the second source line are formed by using the patterned photoresist layer as a mask layer through ion implantation and annealing after resist stripping.
6. The method for manufacturing a flash memory cell structure according to claim 1, wherein: The method further includes forming a first bit line and a second bit line in the substrate, wherein the first bit line and the first source line are located on the same side of the isolation layer and are spaced apart, and the second bit line and the second source line are located on the same side of the isolation layer and are spaced apart.
7. The method for manufacturing a flash memory cell structure according to claim 6, wherein: The first bit line and the second bit line are formed by using the patterned photoresist layer as a mask layer through ion implantation and annealing after resist stripping.
8. The method for manufacturing a flash memory cell structure according to claim 1, wherein: Patterning the word line conductive layer includes: forming a word line opening in the word line conductive layer, wherein the word line opening simultaneously exposes the first insulating layer, the isolation layer, and the second insulating layer; or forming at least two word line openings in the word line conductive layer, wherein one word line opening exposes the first insulating layer, and the other word line opening exposes the second insulating layer; or forming at least three word line openings in the word line conductive layer, wherein the three word line openings respectively expose the first insulating layer, the isolation layer, and the second insulating layer.
9. A flash memory cell structure, characterized in that: include: substrate; an isolation layer, wherein a bottom portion of the isolation layer is embedded in the substrate and a top surface of the isolation layer is higher than a top surface of the substrate; a gate dielectric layer, located on the upper surface of the substrate; a first floating gate conductive layer and a second floating gate conductive layer, located on the gate dielectric layer and distributed on opposite sides of the isolation layer, and the first floating gate conductive layer and the second floating gate conductive layer are in contact with two side walls of the isolation layer respectively; A first insulating layer and a second insulating layer are respectively located on the first floating gate conductive layer and the second floating gate conductive layer; A first source line and a second source line are located in the substrate and distributed on opposite sides of the isolation layer, and the first source line and the second source line are respectively in contact with two side walls of the isolation layer; The word line conductive layer includes at least two word lines, at least one of the word lines is in contact with the first insulating layer, and at least one of the word lines is in contact with the second insulating layer. The flash memory cell structure also includes a first bit line and a second bit line located in the substrate. The first bit line and the first source line are located on the same side of the isolation layer and are spaced apart. The second bit line and the second source line are located on the same side of the isolation layer and are spaced apart.
10. The flash memory cell structure according to claim 9, wherein: Isolation sidewalls are provided on the side of the first floating gate conductive layer and the second floating gate conductive layer away from the isolation layer, and the word line conductive layer covers the isolation sidewalls.
11. The flash memory cell structure according to claim 9, wherein: The first insulating layer includes a LOCOS oxide layer, and the second insulating layer includes a LOCOS oxide layer.
12. The flash memory cell structure according to claim 9, wherein: The first floating gate conductive layer and the second floating gate conductive layer are respectively controlled by different word lines.
Citation Information
Patent Citations
Non-volatile semiconductor memory devices with control gates overlapping pairs of floating gates
US6486508B1