Pixel circuit and driving method thereof, display substrate and display device

Abstract

A pixel circuit (100) and a driving method thereof, a display substrate (20) and a display device (40). The pixel circuit (100) comprises a driving subcircuit (122), a data writing subcircuit (126), a compensation subcircuit (128), a first switch subcircuit (124) and a first light emitting control subcircuit (170). The driving subcircuit (122) includes a control terminal (122a) connected to the first node (N1), a first terminal (122b) connected to the second node (N2), and a second terminal (122c) connected to the third node (N3), and is configured to control a driving signal from the first node (N1) to the third node (N3) and used to drive the light-emitting element (120) according to the voltage of the first node (N1); the first switch subcircuit (124) is configured to control the conduction of the driving signal between the third node (N3) and the fourth node (N4) in response to the first switch control signal (SW1); the first light-emitting control subcircuit (170) is connected to the first electrode (134) of the light-emitting element (120) through the fifth node (N5), and is configured to control the conduction of the driving signal between the fourth node (N4) and the fifth node (N5) in response to the first light-emitting control signal (EM1). The pixel circuit (100) can effectively improve display uniformity.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a pixel circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0002] At present, the display screens of display devices are developing in the direction of large screens and full screens. Usually, display devices (such as mobile phones, tablet computers, etc.) have a camera device (or imaging device), which is usually arranged on a side outside the display area of ​​the display screen. However, since the installation of the camera device requires a certain space, it is not conducive to the full-screen and narrow-frame design of the display screen. For example, the camera device can be combined with the display area of ​​the display screen, and a position can be reserved for the camera device in the display area to maximize the display area of ​​the display screen. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a pixel circuit, including a driving subcircuit, a data writing subcircuit, a compensation subcircuit, a first switch subcircuit, and a first light emitting control subcircuit. The driving subcircuit includes a control terminal connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third node, and the driving subcircuit is configured to control a driving signal from the first node to the third node and used to drive the light-emitting element according to the voltage of the first node; the data writing subcircuit is connected to the second node and configured to write a data signal to the second node in response to a first scanning signal; the compensation subcircuit is connected to the first node and the third node, and is configured to conduct the first node and the third node in response to a second scanning signal, thereby controlling the driving subcircuit to write a compensation voltage to the first node based on the data signal written to the second node; the first switch subcircuit is configured to control the conduction of the driving signal between the third node and the fourth node in response to the first switch control signal and based on the voltage of the third node; the first light-emitting control subcircuit is connected to the fourth node and the fifth node, and is connected to the first electrode of the light-emitting element through the fifth node, and the first light-emitting control subcircuit is configured to control the conduction of the driving signal between the fourth node and the fifth node in response to the first light-emitting control signal, so that the driving signal can be applied to the light-emitting element.

[0004] In some examples, the pixel circuit further includes a first reset subcircuit connected to the fifth node and configured to write a first reset voltage to the fifth node in response to a first reset control signal.

[0005] In some examples, the pixel circuit further includes a first reset subcircuit connected to the fourth node and configured to write a first reset voltage to the fourth node in response to a first reset control signal.

[0006] In some examples, the pixel circuit also includes a first reset subcircuit and a second switch subcircuit, the first reset subcircuit is connected to a sixth node and is connected to the second switch subcircuit through the sixth node, the first reset subcircuit is configured to write a first reset voltage to the sixth node in response to a first reset control signal; the second switch subcircuit is connected to the fourth node and the sixth node, and is configured to control conduction of the fourth node and the sixth node in response to a second switch control signal, so that the first reset voltage from the first reset subcircuit can be written to the fourth node.

[0007] In some examples, the pixel circuit also includes a second light-emitting control subcircuit, which is connected to the second node and the first power supply voltage terminal and is configured to write the first power supply voltage from the first power supply voltage terminal to the second node in response to a second light-emitting control signal.

[0008] In some examples, the pixel circuit further includes a storage subcircuit, the storage subcircuit includes a first terminal and a second terminal, and the first terminal and the second terminal of the storage subcircuit are respectively connected to the first power supply voltage terminal and the first node.

[0009] In some examples, the pixel circuit further includes a second reset subcircuit connected to the first node and configured to write a second reset voltage to the first node in response to a second reset control signal.

[0010] In some examples, the pixel circuit also includes a first capacitor, the first capacitor includes a first electrode and a second electrode, the first electrode of the first capacitor is connected to the fourth node, and the second electrode of the first capacitor is configured to apply the same voltage as the second electrode of the light-emitting element.

[0011] In some examples, the pixel circuit further includes a second capacitor, wherein a first electrode of the second capacitor is connected to the fourth node, and a first electrode of the light-emitting element serves as a second electrode of the second capacitor.

[0012] At least one embodiment of the present disclosure further provides a display substrate, comprising a base substrate and a plurality of sub-pixels distributed in an array along a first direction and a second direction on the base substrate. The plurality of sub-pixels include a first sub-pixel, the first sub-pixel includes the pixel circuit provided in any of the above embodiments and the light-emitting element; the display substrate includes a first display area and a second display area, the first display area at least partially surrounds the second display area; the driving sub-circuit and the first switch sub-circuit of the pixel circuit are both located in the first display area, and the first light-emitting control sub-circuit of the pixel circuit and the light-emitting element are located in the second display area.

[0013] In some examples, the display substrate further includes a connecting wire, one end of which is electrically connected to the first light-emitting control subcircuit, and the other end of which extends to the first display area to be electrically connected to the first switch subcircuit; the material of the connecting wire is a transparent conductive material.

[0014] In some examples, in a direction perpendicular to the base substrate, the connecting line at least partially overlaps with the first electrode of the light-emitting element.

[0015] In some examples, the first light-emitting control subcircuit includes a light-emitting control transistor; a first electrode of the light-emitting control transistor is electrically connected to the connecting line through a first via hole; and a second electrode of the light-emitting control transistor is electrically connected to a first electrode of the light-emitting element through a second via hole.

[0016] In some examples, the display substrate further includes a first connecting electrode, the first connecting electrode is located on a side of the connecting line close to the base substrate, and the first electrode of the light emitting control transistor is electrically connected to the connecting line through the first connecting electrode.

[0017] In some examples, an orthographic projection of the first electrode of the light-emitting element on the base substrate covers an orthographic projection of the first connecting electrode on the base substrate.

[0018] In some examples, the first electrode of the light-emitting element includes an electrode main body and an electrode protrusion protruding from the electrode main body, the electrode main body is used to contact the light-emitting layer of the light-emitting element, and the electrode protrusion is electrically connected to the second electrode of the light-emitting control transistor through the second via hole; the orthographic projection of the second via hole on the substrate is farther away from the orthographic projection of the electrode main body on the substrate than the orthographic projection of the first via hole on the substrate.

[0019] In some examples, the display substrate further includes a light emitting control line located in the second display area, wherein the material of the light emitting control line is a transparent conductive material; the light emitting control line is electrically connected to the gate of the light emitting control transistor to provide the first light emitting control signal.

[0020] In some examples, in a direction perpendicular to the base substrate, the light emitting control line is located on a side of the connecting line close to the first electrode of the light emitting element.

[0021] In some examples, when the pixel circuit further includes a second switch subcircuit, the second switch subcircuit is located in the first display area, the display substrate further includes an auxiliary light-emitting control line located in the first display area, and the second switch subcircuit is connected to the auxiliary light-emitting control line to receive the second switch control signal; the auxiliary light-emitting control line is electrically connected to the light-emitting control line.

[0022] At least one embodiment of the present disclosure further provides a display device, comprising the display substrate provided by any of the above embodiments.

[0023] In some examples, the display device also includes a sensor, the display substrate has a first side for display and a second side opposite to the first side; the sensor is disposed on the second side of the display substrate and is configured to receive light from the first side of the display substrate and through the second display area for sensing.

[0024] At least one embodiment of the present disclosure also provides a driving method for a pixel circuit, which is used to drive the pixel circuit provided by any of the above embodiments, and the driving method includes: in the data writing and compensation stage, turning on the data writing subcircuit and turning off the first switch subcircuit and the first light-emitting control subcircuit, so that the data signal is written to the second node, and the driving subcircuit is compensated; in the pre-charging stage, turning on the first switch subcircuit and turning off the first light-emitting control subcircuit to charge the fourth node so that the potential of the fourth node reaches a predetermined value; in the light-emitting stage, turning on the first switch subcircuit and the first light-emitting control subcircuit, applying the potential of the fourth node to the fifth node, and applying the driving signal to the light-emitting element to make the light-emitting element emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0026] Figure 1A A schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

[0027] Figure 1B for Figure 1A A circuit diagram of a specific implementation example of the pixel circuit shown;

[0028] Figure 1C A timing signal diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

[0029] Figure 2A Schematic diagram of pixel circuits provided for other embodiments of the present disclosure;

[0030] Figure 2B for Figure 2A A circuit diagram of a specific implementation example of the pixel circuit shown;

[0031] Figure 3A A schematic diagram of a pixel circuit provided for still further embodiments of the present disclosure;

[0032] Figure 3B for Figure 3A A circuit diagram of a specific implementation example of the pixel circuit shown;

[0033] Figure 4A One of the schematic diagrams of a display substrate provided by at least one embodiment of the present disclosure;

[0034] Figure 4B A second schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0035] Figure 5A A third schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0036] Figure 5B for Figure 5A A cross-sectional view along section line II';

[0037] Figure 5C for Figure 5A A cross-sectional view along section line II-II';

[0038] Figure 6 A fourth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0039] Fig. 7A A fifth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0040] Figure 7B A sixth schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0041] Fig. 8A A seventh schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0042] Figure 8B An eighth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0043] Fig. 9AA ninth schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0044] Fig. 9B A tenth schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0045] Fig. 10A A schematic diagram of a display device provided for at least one embodiment of the present disclosure; and

[0046] Fig. 10B for Fig. 10A Sectional view along section line CC'. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0048] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] In a display device integrated with an imaging element, the imaging element is arranged in the display area of ​​the display device, which helps to increase the proportion of the display screen, for example, to achieve a full-screen display. Since a display device is made in the display area, it will affect the light transmittance reaching the imaging element and thus affect the sensing effect. For example, the light-emitting element in the sub-pixel, the opaque wiring, etc. may block the light captured by the imaging element and thus affect the imaging quality. For example, the light transmittance of the area can be improved by reducing the arrangement of the pixel circuit structure in the display area where the imaging element is arranged. The display area where the imaging element is arranged is, for example, called a translucent display area. For example, the pixel circuit connected to the light-emitting element in the translucent display area can be arranged in a display area outside the translucent display area, that is, the light-emitting element connected to a part of the pixel circuit is moved to the translucent display area instead of emitting light in situ, thereby improving the display uniformity while improving the light transmittance of the translucent display area.

[0050] For example, one implementation method is to form the light-transmitting display area by reducing the number of pixel circuits without changing the size of the pixel circuits. For example, the pixel circuits originally located in the light-transmitting display area are directly removed. Since the number of pixel circuits corresponds to the number of light-emitting elements driven by them, the number of light-emitting elements needs to be reduced accordingly. For example, the setting density of effective light-emitting elements in the light-transmitting display area can be reduced. This method will reduce the uniformity of display brightness.

[0051] For example, one way is not to change the number of pixel circuits, but to compress the size of the pixels to leave space for the light-transmitting display area. For example, the size of the pixel circuit is compressed in the horizontal direction (row direction) and remains unchanged in the vertical direction (column direction). In this way, sufficient pixel circuits can be provided to drive a constant number of light-emitting elements, so that the setting density of the light-emitting elements is not affected. For example, the light-emitting elements have a consistent density in the display area. This method can further improve the display uniformity and reduce the impact of the setting of the light-transmitting display area on the display effect.

[0052] The pixel electrode of the light-emitting element usually needs to be connected to the pixel circuit driving the light-emitting element through a connecting wire or a connecting electrode. The inventors have found that the parasitic capacitance generated between the connecting wire or the connecting electrode and other conductive structures will have an adverse effect on the display effect of the light-emitting element. For example, the parasitic capacitance will increase the charging time of the pixel electrode, thereby delaying the lighting time of the light-emitting element and shortening the light-emitting time.

[0053] For example, the light-emitting element located in the light-transmitting display area needs to be connected to the pixel circuit structure driving the light-emitting element outside the light-transmitting display area through a longer connecting line, which causes a larger parasitic capacitance at the pixel electrode, thereby prolonging the charging time required for the pixel electrode during the light-emitting stage. For example, during the light-emitting stage, the time for the potential of the pixel electrode to charge to the light-emitting element's lighting voltage is longer (for example, compared with the sub-pixel that emits light in situ in the display area outside the light-transmitting display area), so the light-emitting time is shortened, ultimately causing uneven brightness. In addition, in the light-transmitting display area, the difference in length, shape or position of the connecting line connected to the pixel electrode of the light-emitting element will also cause different parasitic capacitances, resulting in inconsistent lighting times of the light-emitting element during the light-emitting stage, resulting in uneven display.

[0054] At least one embodiment of the present disclosure provides a pixel circuit, including a driving subcircuit, a data writing subcircuit, a compensation subcircuit, a first switch subcircuit and a first light emitting control subcircuit. The driving subcircuit includes a control terminal connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third node, and the driving subcircuit is configured to control a driving signal from the first node to the third node and used to drive the light-emitting element according to the voltage of the first node; the data writing subcircuit is connected to the second node and is configured to write a data signal to the second node in response to a first scanning signal; the compensation subcircuit is connected to the first node and the third node, and is configured to conduct the first node and the third node in response to a second scanning signal, thereby controlling the driving subcircuit to write a compensation voltage to the first node based on the data signal written to the second node; the first switch subcircuit is configured to control the conduction of the driving signal between the third node and the fourth node in response to a first switch control signal and based on the voltage of the third node; the first light-emitting control subcircuit is connected to a fifth node and is connected to the first electrode of the light-emitting element through the fifth node, and the first light-emitting control subcircuit is configured to control the conduction of the driving signal between the fourth node and the fifth node in response to the first light-emitting control signal, so that the driving signal can be applied to the light-emitting element.

[0055] For example, the driving signal may be a driving voltage or a driving current for driving the light emitting element.

[0056] The pixel circuit provided by the embodiment of the present disclosure is separated from the fifth node N5 directly connected to the light-emitting element by setting the fourth node N4 where the first light-emitting control subcircuit is prone to generate parasitic capacitance, and the first light-emitting control subcircuit can control the conduction between the fourth node N4 and the fifth node N5, and can charge the fourth node in advance before the light-emitting stage arrives, for example, providing sufficient time to charge the fourth node before the start of the light-emitting stage, so that after the circuit enters the light-emitting stage, the influence of the parasitic capacitance at the fourth node on the light-emitting element is reduced, and the display uniformity is improved. For example, in the light-emitting stage, the first light-emitting control subcircuit is turned on in response to the first light-emitting control signal, so that the driving signal is turned on at the fourth node and the fifth node, and the potential of the fourth node is copied to the fifth node connected to the light-emitting element. Since the fourth node has been charged in advance, the potential of the fifth node can quickly reach the light-emitting voltage of the light-emitting element, so that the light-emitting time is no longer affected by the parasitic capacitance at the fourth node N4.

[0057] Figure 1A Schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure. Figure 1A As shown, the pixel circuit includes a driving subcircuit 122 , a data writing subcircuit 126 , a compensation subcircuit 128 , a first switch subcircuit 124 and a first light emitting control subcircuit 170 .

[0058] The driving subcircuit 122 includes a control terminal 122a connected to the first node N1, a first terminal 122b connected to the second node N2, and a second terminal 122c connected to the third node N3. The driving subcircuit 122 is configured to control a driving signal from the first node N1 to the third node N3 and used to drive the light emitting element 120 according to the voltage of the first node N1. For example, the driving signal can be a driving voltage or a driving current used to drive the light emitting element.

[0059] The data writing subcircuit 126 is connected to the second node N2 and is configured to write the data signal Vd into the second node N2 in response to the first scanning signal Ga1. For example, the data writing subcircuit 126 includes a control terminal 126a, a first terminal 126b, and a second terminal 126c, wherein the control terminal 126a is configured to receive the first scanning signal Ga1, the first terminal 126b is configured to receive the data signal Vd, and the second terminal 126c is connected to the second node N2. For example, in the data writing and compensation stage, the data writing subcircuit 126 can be turned on in response to the first scanning signal Ga1, so that the data signal can be written into the first terminal 122b (the second node N2) of the driving subcircuit 122, and the data signal can be stored, so that a driving signal for driving the light-emitting element 120 to emit light can be generated according to the data signal in the light-emitting stage.

[0060] The compensation sub-circuit 128 is connected to the first node N1 and the third node N3, and is configured to conduct the first node N1 and the third node N3 in response to the second scan signal Ga2, thereby controlling the driving sub-circuit 122 to write a compensation voltage to the first node N1 based on the data signal Vd written to the second node N2. For example, the compensation sub-circuit 128 includes a control terminal 128a, a first terminal 128b, and a second terminal 128c, wherein the control terminal 128a is configured to receive the second scan signal Ga2, the first terminal 128b is connected to the third node N3, and the second terminal 128c is connected to the first node N1.

[0061] For example, the first scan signal Ga1 may be the same as the second scan signal Ga2. For example, the first scan signal Ga1 may be connected to the same signal output terminal as the second scan signal Ga2. For example, the first scan signal Ga1 may be transmitted through the same scan line as the second scan signal Ga2.

[0062] In some other examples, the first scanning signal Ga1 may be different from the second scanning signal Ga2. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be connected to different signal output terminals. For example, the first scanning signal Ga1 and the second scanning signal Ga2 may be transmitted through different scanning lines.

[0063] The first switch subcircuit 124 is configured to respond to the first switch control signal SW1 and control the conduction of the driving signal between the third node N3 and the fourth node N4 based on the voltage of the third node N3. For example, the first switch subcircuit 124 includes a control terminal 124a, a first terminal 124b, and a second terminal 124c, the control terminal 124a is configured to receive the first switch control signal SW1, and the first terminal 124b and the second terminal 124c are connected to the third node N3 and the fourth node N4, respectively.

[0064] The first light-emitting control subcircuit 170 is connected to the fifth node N5 and connected to the first electrode 134 of the light-emitting element 120 through the fifth node N5. The first light-emitting control subcircuit 170 is configured to control the conduction of the driving signal between the fourth node N4 and the fifth node N5 in response to the first light-emitting control signal EM1, so that the driving signal can be applied to the light-emitting element 120. For example, the first light-emitting control subcircuit 170 includes a control terminal 170a, a first terminal 170b, and a second terminal 170c. The control terminal 170a is configured to receive the first light-emitting control signal EM1, and the first terminal 170b and the second terminal 170c are connected to the fourth node N4 and the fifth node N5, respectively.

[0065] The first light-emitting control subcircuit 170 is spaced between the fourth node N4 and the pixel electrode (i.e., the first electrode 134 of the light-emitting element), avoiding the fourth node N4 from being directly connected to the pixel electrode, thereby effectively reducing the influence of the parasitic capacitance Cp (an example of the second capacitance of the present disclosure) that may exist at the fourth node N4 on the pixel electrode. For example, before the light-emitting stage arrives, the first switch subcircuit 124 can be turned on and the first light-emitting control subcircuit 170 can be turned off, so that the fourth node N4 can be pre-charged (for example, charged to the light-on voltage of the light-emitting element); and in the light-emitting stage, the first switch subcircuit 124 and the first light-emitting control subcircuit 170 are turned on at the same time, and under the action of the driving current, the potential prepared on the fourth node N4 is quickly copied to the fifth node N5, thereby avoiding the display unevenness (Mura) phenomenon caused by the charging time required for the parasitic capacitance squeezing out the light-emitting time, and improving the uniformity of light emission.

[0066] For example, in the light-emitting stage, the first light-emitting control subcircuit 170 is turned on in response to the first light-emitting control signal EM1 provided by the first light-emitting control terminal EM1, and the first switch subcircuit 124 is also turned on, so that the driving subcircuit 122 can be electrically connected to the light-emitting element 120 through the first switch subcircuit 124 and the first light-emitting control subcircuit 170, thereby driving the light-emitting element 120 to emit light under the control of the driving signal; and in the non-light-emitting stage, the first light-emitting control subcircuit 170 is turned off in response to the first light-emitting control signal EM1, thereby preventing current from flowing through the light-emitting element 120 to cause it to emit light, which can improve the contrast of the corresponding display device.

[0067] For example, the parasitic capacitor Cp includes a first electrode Cpa and a second electrode Cpb, the first electrode Cpa is connected to the fourth node, and the second electrode Cpb can be, for example, the first electrode 134 of the light-emitting element 120 or other signal wiring, that is, the parasitic capacitor Cp is formed between the second end 170b of the first light-emitting control subcircuit 170 and the first electrode 134 of the light-emitting element 120 or other signal wiring.

[0068] For example, the pixel circuit may further include an analog capacitor Cm (an example of the first capacitor of the present disclosure). The analog capacitor Cm includes a first electrode Cma and a second electrode Cmb, the first electrode Cma being connected to the fourth node, and the second electrode Cmb being configured to apply the same voltage as the second electrode 135 of the light-emitting element 120, such as the second power supply voltage VSS. Thus, the analog capacitor Cm can simulate the capacitance of the light-emitting element 120 itself, thereby constructing an environment for the fourth node N4 that is the same as or similar to the fifth node N5, so as to facilitate rapid copying of the potential of the fourth node N4 to the fifth node N5 during the light-emitting stage.

[0069] For example, the pixel circuit may further include a first reset sub-circuit 129 connected to the fifth node N5 and configured to write a first reset voltage Init1 to the fourth node N4 in response to a first reset control signal Rst1 .

[0070] For example, the pixel circuit may further include a second reset sub-circuit 125 , which is connected to the first node N1 and configured to write a second reset voltage Init2 into the first node N1 in response to a second reset control signal Rst2 .

[0071] For example, the pixel circuit may further include a second light emitting control subcircuit 123, the second light emitting control subcircuit 123 is connected to the first power supply voltage terminal VDD and the second node N2, and is configured to write the first power supply voltage VDD from the first power supply voltage terminal VDD into the second node N2 in response to the second light emitting control signal EM2. For example, the second light emitting control signal and the first switch control signal SW1 may be the same signal or different signals.

[0072] For another example, during the initialization phase, the second light emitting control sub-circuit 124 may also be turned on in response to the second light emitting control signal, so that the reset circuit may be combined to perform a reset operation on the driving sub-circuit 122 and the light emitting element 120 .

[0073] For example, the first reset voltage Init1 and the second reset voltage Init2 may be the same voltage signal or different voltage signals. For example, the first reset control signal Rst1 and the second reset control signal Rst2 may be the same signal or different signals.

[0074] For example, the first reset sub-circuit 129 and the second reset sub-circuit 125 can be turned on in response to the first reset control signal Rst1 and the second reset control signal Rst2, respectively, so that the first reset voltage Init1 can be applied to the first electrode 134 of the light-emitting element 120 and the second reset voltage Init2 can be applied to the first node N1, respectively, so that the driving sub-circuit 122, the compensation sub-circuit 128 and the light-emitting element 120 can be reset to eliminate the influence of the previous light-emitting stage.

[0075] For example, the pixel circuit may further include a storage subcircuit 127, the storage subcircuit 127 including a first terminal 127a and a second terminal 127b, the first terminal 127a and the second terminal 127b being connected to the first power supply voltage terminal VDD and the first node N1, respectively. For example, in the data writing and compensation stage, the compensation subcircuit 128 may be turned on in response to the second scanning signal Ga2, so that the data signal written by the data writing subcircuit 126 may be stored in the storage subcircuit 127; at the same time, the compensation subcircuit 128 may conduct the first node N1 and the third node N3, that is, the control terminal 122a and the second terminal 122c of the driving subcircuit 122 are electrically connected, so that the relevant information of the threshold voltage of the driving subcircuit 122 is also stored in the storage subcircuit accordingly, so that, for example, in the light emitting stage, the stored data signal and the threshold voltage may be used to control the driving subcircuit 122, so that the driving subcircuit 122 is compensated.

[0076] For example, the light emitting element 120 includes a first electrode 134 and a second electrode 135 . The first electrode 134 of the light emitting element 120 is configured to be connected to the second terminal 122 c of the driving subcircuit 122 , and the second electrode 135 of the light emitting element 120 is configured to be connected to the second power supply voltage terminal VSS.

[0077] It should be noted that in the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node as well as the sixth node appearing later do not necessarily represent actual existing components, but represent the meeting points of related circuit connections in the circuit diagram.

[0078] It should be noted that in the description of the embodiments of the present disclosure, the symbol Vd can represent both the data signal terminal and the level of the data signal. Similarly, the symbols Ga1 and Ga2 can represent both the first scan signal and the second scan signal, and can also represent the first scan signal terminal and the second scan signal terminal. EM1 and EM2 can represent both the first light-emitting control signal and the second light-emitting control signal, and can also represent the first light-emitting control terminal and the second light-emitting control terminal. Rst1 and Rst2 can represent both the first reset control signal and the second reset control signal, and can also represent the first reset control terminal and the second reset control terminal. The symbols Init1 and Init2 can represent both the first reset voltage terminal and the second reset voltage terminal, and can also represent the first reset voltage and the second reset voltage. The symbol VDD can represent both the first power supply voltage terminal and the first power supply voltage. The symbol VSS can represent both the second power supply voltage terminal and the second power supply voltage. The following embodiments are the same as this and will not be repeated.

[0079] Figure 1B Shows Figure 1A A circuit diagram of a specific implementation example of the circuit shown. Figure 1B As shown, the pixel circuit includes first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8 and a storage capacitor Cst.

[0080] For example, Figure 1B As shown, the driving subcircuit 122 can be implemented as a first transistor T1 (i.e., a driving transistor). The gate of the first transistor T1 serves as a control terminal 122a of the driving subcircuit 122 and is connected to the first node N1; the first electrode of the first transistor T1 serves as a first terminal 122b of the driving subcircuit 122 and is connected to the second node N2; the second electrode of the first transistor T1 serves as a second terminal 122c of the driving subcircuit 122 and is connected to the third node N3.

[0081] For example, Figure 1B As shown, the data writing subcircuit 126 can be implemented as a second transistor T2. The gate of the second transistor T2 is connected to the first scan line (first scan signal terminal Ga1) to receive the first scan signal, the first electrode of the second transistor T2 is connected to the data line (data signal terminal Vd) to receive the data signal, and the second electrode of the second transistor T2 is connected to the first terminal 122b (second node N2) of the driving subcircuit 122.

[0082] For example, Figure 1B As shown, the compensation sub-circuit 128 can be implemented as a third transistor T3 (i.e., a compensation transistor). The gate, the first electrode, and the second electrode of the third transistor T3 serve as the control terminal 128a, the first terminal 128b, and the second terminal 128c of the compensation sub-circuit, respectively. The gate of the third transistor T3 is configured to be connected to the second scan line (the second scan signal terminal Ga2) to receive the second scan signal, the first electrode of the third transistor T3 is connected to the second terminal 122c (the third node N3) of the driving sub-circuit 122, and the second electrode of the third transistor T3 is connected to the control terminal 122a (the first node N1) of the driving sub-circuit 122.

[0083] For example, Figure 1B As shown, the first light-emitting control subcircuit 170 can be implemented as an eighth transistor T8 (an example of the light-emitting control transistor of the present disclosure). The gate of the eighth transistor T8 is connected to the first light-emitting control line (first light-emitting control terminal EM1) to receive the first light-emitting control signal EM1, the first electrode of the eighth transistor T8 is connected to the fourth node N4, and the second electrode of the eighth transistor T8 is connected to the fifth node N5.

[0084] For example, Figure 1BAs shown, the second light emitting control subcircuit 123 can be implemented as a fourth transistor T4. The gate of the fourth transistor T4 is connected to the second light emitting control line (the second light emitting control terminal EM2) to receive the second light emitting control signal EM2, the first electrode of the fourth transistor T4 is connected to the first power supply voltage terminal VDD to receive the first power supply voltage VDD, and the second electrode of the fourth transistor T4 is connected to the first terminal 122b (the second node N2) of the driving subcircuit 122.

[0085] For example, Figure 1B As shown, the first switch subcircuit 124 can be implemented as a fifth transistor T5, and the gate, the first electrode and the second electrode of the fifth transistor T5 respectively serve as the control terminal 124a, the first terminal 124b and the second terminal 124c of the first switch subcircuit 124. For example, the second light-emitting control signal EM2 also serves as the first switch control signal SW1. In this case, the second light-emitting control line or the second light-emitting control terminal is also connected to the gate of the fifth transistor T5 to provide the first switch control signal SW1, the first electrode of the fifth transistor T5 is connected to the second terminal 122c (the third node N3) of the driving subcircuit 122, and the second electrode of the fifth transistor T5 is connected to the first terminal 170b (the fourth node N4) of the first light-emitting control subcircuit 170.

[0086] For example, Figure 1B As shown, the storage subcircuit 127 can be implemented as a storage capacitor Cst, which includes a first capacitor electrode Ca and a second capacitor electrode Cb. The first capacitor electrode Ca is connected to the first power supply voltage terminal VDD, and the second capacitor electrode Cb is connected to the control terminal 122a of the driving subcircuit 122.

[0087] For example, the first reset subcircuit 129 may be implemented as a seventh transistor T7, and the second reset subcircuit 125 may be implemented as a sixth transistor T6. The gate of the seventh transistor T7 is configured to be connected to the first reset control terminal Rst1 to receive the first reset control signal Rst1, the first electrode of the seventh transistor T7 is connected to the first reset voltage terminal Init1 to receive the first reset voltage Init1, and the second electrode of the seventh transistor T7 is configured to be connected to the fifth node N5. The gate of the sixth transistor T6 is configured to be connected to the second reset control terminal Rst2 to receive the second reset control signal Rst2, the first electrode of the sixth transistor T6 is connected to the second reset voltage terminal Init2 to receive the second reset voltage Init2, and the second electrode of the sixth transistor T6 is configured to be connected to the first node N4. For example, the first reset voltage terminal Init1 and the second reset voltage terminal Init2 may be the same voltage terminal.

[0088] For example, the light-emitting element 120 is specifically implemented as a light-emitting diode (LED), for example, an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED) or an inorganic light-emitting diode, for example, a micro light-emitting diode (Micro LED) or a micro OLED. For example, the light-emitting element 120 can be a top emission structure, a bottom emission structure or a double-sided emission junction. The light-emitting element 120 can emit red light, green light, blue light or white light, etc. The embodiments of the present disclosure do not limit the specific structure of the light-emitting element. For example, the light-emitting element 120 includes a first electrode 134, a second electrode 135, and a light-emitting layer sandwiched between the first electrode 134 and the second electrode 135.

[0089] For example, the first electrode 134 (also called pixel electrode, for example, an anode) of the light emitting element 120 is connected to the fourth node N4 and is configured to be connected to the second terminal 122c of the driving subcircuit 122 through the second light emitting control subcircuit 124, and the second electrode 135 (for example, a cathode) of the light emitting element 120 is configured to be connected to the second power supply voltage terminal VSS to receive the second power supply voltage VSS, and the circuit that flows from the second terminal 122c of the driving subcircuit 122 into the light emitting element 120 determines the brightness of the light emitting element. For example, the second power supply voltage terminal can be grounded, that is, VSS can be 0V. For example, the second power supply voltage VSS can also be a negative voltage.

[0090] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are described by taking thin film transistors as examples. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one pole is directly described as the first pole and the other pole is directly described as the second pole.

[0091] In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). For example, the transistors (T1-T9) used in at least some embodiments of the present disclosure are all P-type transistors, such as low-temperature polysilicon thin film transistors. However, the embodiments of the present disclosure do not limit the type of transistors. When the type of transistor changes, the connection relationship in the circuit can be adjusted accordingly.

[0092] The following combination Figure 1C The signal timing diagram shown is Figure 1B The working principle of the pixel circuit shown in FIG. Figure 1C As shown, the display process of each frame of image includes four stages, namely initialization stage 1, data writing and compensation stage 2, pre-charging stage 3 and light emitting stage 4.

[0093] like Figure 1C As shown, in this embodiment, the first scanning signal Ga1 and the second scanning signal Ga2 use the same signal, the first switch control signal SW1 and the second light-emitting control signal EM2 use the same signal; and the first reset control signal Rst1 and the first scanning signal Ga1 / the second scanning signal Ga2 have the same waveform, that is, the second reset control signal Rst2 and the first scanning signal Ga1 / the second scanning signal Ga2 can use the same signal; the second reset signal Rst2 of the sub-pixel in this row has the same waveform as the first scanning signal Ga1 / the second scanning signal Ga2 of the sub-pixel in the previous row, that is, the same signal is used. However, this is not a limitation to the present disclosure, and in other embodiments, different signals can be used as the first scanning signal Ga1, the second scanning signal Ga2, the first reset control signal Rst1, and the second reset control signal Rst2, and different signals can be used as the first switch control signal SW1 and the second light-emitting control signal EM2.

[0094] In the initialization phase 1, the second reset control signal Rst2 is input to turn on the sixth transistor T6, and the second reset voltage Init2 is applied to the gate of the first transistor T1, thereby resetting the first node N1.

[0095] In the data writing and compensation stage 2, the first scanning signal Ga1, the second scanning signal Ga2 and the data signal Vd are input, the second transistor T2 and the third transistor T3 are turned on, the data signal Vd is written into the second node N2 by the second transistor T2, and the first node N1 is charged through the first transistor T1 and the third transistor T3 until the potential of the first node N1 changes to Vd+Vth, and the first transistor T1 is turned off, where Vth is the threshold voltage of the first transistor T1. The potential of the first node N1 is stored in the storage capacitor Cst and maintained, that is, the voltage information with the data signal and the threshold voltage Vth is stored in the storage capacitor Cst, so as to provide grayscale display data and compensate the threshold voltage of the first transistor T1 itself in the subsequent light-emitting stage.

[0096] In the data writing and compensation phase 2, the first reset control signal Rst1 may be input to turn on the seventh transistor T7, and the first reset voltage Init1 may be applied to the fifth node N5, thereby resetting the fifth node N5. For example, the fifth node N5 may also be reset in the initialization phase 1, for example, the first reset control signal Rst1 and the second reset control signal Rst2 may be the same. The embodiments of the present disclosure are not limited to this.

[0097] In the pre-charging stage 3, the first switch control signal SW1, the second light-emitting control signal EM2 and the first light-emitting control signal EM1 are input to respectively turn on the fifth transistor T5 and the fourth transistor T4 and turn off the eighth transistor T8, so as to charge the fourth node N4 so that the potential of the fourth node N4 reaches a predetermined value, for example, reaching the light-on voltage V0 of the light-emitting element 120. For example, the voltage difference between the light-on voltage V0 and the voltage of the second terminal 135 of the light-emitting element 120 (for example, the second power supply voltage VSS) is the turn-on voltage of the light-emitting element 120. For example, the turn-on voltage is the voltage difference between the two ends when the light-emitting element emits light with a brightness of 1 cd / m2. When the second terminal 135 of the light-emitting element 120 is grounded, the light-on voltage V0 is equal to the turn-on voltage of the light-emitting element. For example, the duration of the pre-charging stage 3 is related to the size of the parasitic capacitance Cp at the fourth node N4. The larger the capacitance of the parasitic capacitance Cp, the longer the duration of the pre-charging stage 3.

[0098] In the light-emitting stage 4, the first switch control signal SW1, the second light-emitting control signal EM2 and the first light-emitting control signal EM1 are input to turn on the fifth transistor T5, the fourth transistor T4 and the eighth transistor T8 respectively, and the eighth transistor T8 applies the potential of the fourth node N4 to the fifth node, and applies the driving current to the OLED to make it emit light. Since the potential of the fourth node N4 has been pre-charged, the voltage difference across the OLED can quickly reach the turn-on voltage of the light-emitting element, thereby lighting the light-emitting element 120. The value of the driving current I flowing through the OLED can be obtained according to the following formula:

[0099] I=K(VGS-Vth) 2 =K[(Vdata+Vth-VDD)-Vth] 2 =K(Vdata-VDD) 2 , where K is the conductivity coefficient of the first transistor.

[0100] In the above formula, Vth represents the threshold voltage of the first transistor T1, VGS represents the voltage between the gate and the source (here, the first electrode) of the first transistor T1, and K is a constant value related to the first transistor T1 itself. It can be seen from the above calculation formula of I that the driving current I flowing through the OLED is no longer related to the threshold voltage Vth of the first transistor T1, thereby achieving compensation for the pixel circuit, solving the problem of threshold voltage drift caused by the process and long-term operation of the driving transistor (the first transistor T1 in the embodiment of the present disclosure), eliminating its influence on the driving current I, and thus improving the display effect of the display device using it.

[0101] Figure 2A Schematic diagram of a pixel circuit provided by another embodiment of the present disclosure. Figure 1A The main difference of the pixel circuit shown is that the first reset subcircuit 129 is connected to the fourth node N4 and is configured to write the first reset voltage Init1 to the fourth node N4 in response to the first reset control signal. This is because when the first light emitting control subcircuit 170 is turned on, the potential of the fourth node N4 can be quickly copied to the fifth node N5, so resetting the fourth node N4 is equivalent to resetting the fifth node N5. For example, referring to Figure 1C In the data writing and compensation phase 2, the first reset sub-circuit 129 responds to the first reset control signal Rst1 to reset the fourth node N4, and at the same time, the first light-emitting control sub-circuit 170 responds to the first light-emitting control signal EM1 to turn on the potential of the fourth node N4 to the fifth node N5, thereby resetting the fifth node N5.

[0102] Figure 2B Shows Figure 2A A circuit diagram of a specific implementation example of the circuit shown in FIG. Figure 1B The description is not repeated here.

[0103] Figure 3A A schematic diagram of a pixel circuit provided by another embodiment of the present disclosure. Figure 1A The main difference of the pixel circuit shown is that the pixel circuit further includes a second switch subcircuit 180 connected to the fourth node N4, and the first reset subcircuit 129 is connected to the sixth node N6 and to the second switch subcircuit 180 through the sixth node N6.

[0104] The first reset sub-circuit 129 is configured to write the first reset voltage Init1 to the sixth node in response to the first reset control signal Rst1; the second switch sub-circuit 180 is configured to control the conduction of the fourth node N4 and the sixth node N6 in response to the second switch control signal SW2, so that the first reset voltage Init1 from the first reset sub-circuit 129 can be written to the fourth node N4, thereby resetting the fourth node N4.

[0105] For example, the second switch control signal SW2 and the first light emitting control signal EM1 may be the same signal. Figure 1C In the data writing and compensation phase 2, the first light emitting control signal EM1 / the second switch control signal SW2 is an on signal, and the second switch subcircuit 180 is turned on. Therefore, the second switch subcircuit 180 does not affect the reset operation of the first reset subcircuit 129 on the fourth node N4.

[0106] In the actual circuit layout of the display substrate, the second switch sub-circuit 180 can be used as an auxiliary sub-circuit to improve the uniformity of the display substrate in terms of process (for example, etching uniformity).

[0107] Figure 3B Shows Figure 3A A circuit diagram of a specific implementation example of the circuit shown, for example, Figure 3B As shown, the second switch subcircuit 180 can be implemented as a ninth transistor T9, the gate of the ninth transistor T9 is configured to receive the second switch control signal SW2, and the first electrode and the second electrode of the ninth transistor T9 are respectively connected to the fourth node N4 and the sixth node N6. Figure 1B The description is not repeated here.

[0108] At least one embodiment of the present disclosure also provides a driving method for a pixel circuit, which is used to drive the pixel circuit provided by any of the above embodiments. The driving method at least includes: in the data writing and compensation stage, turning on the data writing subcircuit and turning off the first switch subcircuit and the first light-emitting control subcircuit, so that the data signal is written to the second node, and the driving subcircuit is compensated; in the pre-charging stage, turning on the first switch subcircuit and turning off the first light-emitting control subcircuit to charge the fourth node so that the potential of the fourth node reaches a predetermined value; in the light-emitting stage, turning on the first switch subcircuit and the first light-emitting control subcircuit, applying the potential of the fourth node to the fifth node, and applying the driving signal to the light-emitting element to make the light-emitting element emit light. The specific description can be referred to above, and will not be repeated here. For example, the driving signal can be a driving voltage or a driving current for driving the light-emitting element.

[0109] At least one embodiment of the present disclosure further provides a display substrate, comprising the pixel circuit provided by any of the above embodiments.

[0110] Figure 4A This is one of the planar schematic diagrams of a display substrate provided in an embodiment of the present disclosure, Figure 4A FIG. 4 shows the layout of the display area of ​​the display substrate. Figure 4A As shown, the display area 101 of the display substrate 20 is divided into a main display area 21 and a related area of ​​a photosensitive element (such as a camera). For example, the related area includes a first display area 22 and a second display area 23, and the first display area at least partially or completely surrounds the second display area 23. For example, the photosensitive element is arranged corresponding to the second display area 23.

[0111] Figure 4B The second schematic plan view of the display substrate provided in the embodiment of the present disclosure is as follows. Figure 4B FIG. 2 shows a pixel layout diagram of the display substrate. Figure 4B As shown, the display substrate 20 includes a plurality of pixel circuits 100 located in a display area 101. Figure 4B The pixel circuit 100 is schematically shown by a rectangular block. For example, each pixel circuit 100 may adopt the pixel circuit provided by any embodiment of the present disclosure. For example, according to the different regions where the pixel circuit 100 is located, the structure of the pixel circuit 100 may be adjusted accordingly.

[0112] like Figure 4B As shown, the plurality of pixel circuits 100 are arranged in a plurality of rows and columns along a first direction D1 and a second direction D2; the first direction D1 and the second direction D2 are different, for example, they are orthogonal. For example, the pixel rows and the pixel columns do not necessarily extend strictly along a straight line, but may also extend along a curve (for example, a broken line), and the curve generally extends along the first direction D1 or the second direction D2. For example, the density of the pixel circuits in the first display area 22 and the main display area 21 is the same, thereby improving the uniformity of the process.

[0113] For example, in the main display area 21, the connection line between the pixel circuit of each sub-pixel and the light-emitting element it drives is relatively short. For example, the pixel circuit and the light-emitting element of the sub-pixel are both located in the main display area, and in-situ light emission can be achieved. Figure 1A-1B or Figure 2A-2B The pixel circuit shown.

[0114] For example, there is no complete pixel circuit structure in the second display area 23, but there may be a partial pixel circuit structure, which is to improve the light transmittance of the second display area 23, thereby improving the photosensitivity of the photosensitive element. For example, in order to improve display uniformity, a light-emitting element is provided in the second display area 23, but the main structure of the pixel circuit driving the light-emitting element is provided in the first display area 21 around the second display area 23. Figure 4B The light emitting elements in the second display area 23 are schematically shown as circles, and the light emitting elements are connected by connecting lines (such as Figure 4B The second display area 23 is connected to the pixel circuit structure or signal line in the first display area 21. When a photosensitive element is provided on the side of the display substrate opposite to the display side, the light to be detected mainly reaches the photosensitive element via the second display area 23, which will be described in detail later.

[0115] For example, in the first display area 22, the pixel circuits of some sub-pixels are used to drive the light-emitting elements located in the second display area 23. For the convenience of description, these sub-pixels are hereinafter referred to as first sub-pixels.

[0116] For example, the size of the pixel circuits in the first display area 22 is compressed in the first direction D1, so the number of pixel circuits is greater than the number of light-emitting elements. Figure 3A-3B For example, some sub-pixels that emit light in situ also exist in the first display area 22 .

[0117] For example, the driving subcircuit 122 and the first switching subcircuit 124 of the first sub-pixel are located in the first display area 22, the first light-emitting control subcircuit 170 and the light-emitting element 120 are located in the second display area 23, the second end of the first light-emitting control subcircuit is electrically connected to the first electrode of the light-emitting element 120, and the first end of the first light-emitting subcircuit is electrically connected to the first switching subcircuit located in the first display area 22 via a connecting line (corresponding to the fourth node N4).

[0118] For example, the connecting line extends from the second display area 23 to the first display area 22, and it is easy to form parasitic capacitance with other conductive structures during the extension process. By setting the first light-emitting control subcircuit 170 in the second display area, that is, at one end of the connecting line close to the light-emitting element, the connecting line can be effectively separated from the light-emitting element, avoiding the direct connection of the connecting line to the light-emitting element, thereby effectively reducing the adverse effect of the parasitic capacitance existing at the connecting line on the light emission. For example, before the light-emitting stage arrives, the first switch subcircuit 124 can be turned on and the first light-emitting control subcircuit 170 can be turned off, so that the connecting line can be pre-charged (for example, charged to the light-emitting voltage of the light-emitting element); and in the light-emitting stage, the first switch subcircuit 124 and the first light-emitting control subcircuit 170 are turned on at the same time, and under the action of the driving signal, the potential prepared on the connecting line is quickly copied to the pixel electrode, thereby avoiding the display unevenness (Mura) phenomenon caused by the charging time required for the parasitic capacitance crowding out the light-emitting time, and improving the uniformity of light emission.

[0119] like Figure 4B As shown, the display substrate includes a plurality of gate lines 11 and a plurality of data lines 12. For example, the gate lines 11 extend along a first direction D1, and the data lines 12 extend along a second direction D2. Figure 4B The figure only schematically shows the approximate positional relationship among the gate line 11 , the data line 12 and the pixel circuit 100 in the display substrate, and the specific positional relationship can be designed according to actual needs. Figure 4B Although it is shown that each gate line 11 and each data line 12 runs through the first display area 21 and the second display area 22, this is only for the convenience of drawing and is not intended to limit the present disclosure.

[0120] For example, Figure 4B As shown, the display substrate 20 includes a non-display area 102 outside the display area 101. The display substrate may also include a gate driving circuit 13 and a data driving circuit 14 located in the non-display area. The gate driving circuit 13 is connected to the pixel circuit unit 100 through the gate line 11 to provide various scanning signals and control signals, and the data driving circuit 14 is connected to the pixel circuit 100 through the data line 12 to provide a data signal Vd.

[0121] For example, the display substrate 20 may further include a control circuit (not shown). For example, the control circuit is configured to control the data drive circuit 14 to apply the data signal, and control the gate drive subcircuit to apply the scan signal. An example of the control circuit is a timing control circuit (T-con). The control circuit may be in various forms, such as including a processor and a memory, the memory including an executable code, and the processor runs the executable code to execute the above-mentioned detection method.

[0122] For example, the processor may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0123] For example, the storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may run the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium.

[0124] The following will use the first sub-pixel Figure 3A-3B As an example, the pixel circuit shown in FIG. Figures 5A-5C , Figure 6 , Figure 7A-7B , Figures 8A-8B , Figures 9A-9B The structure of the display substrate provided in at least one embodiment of the present disclosure is exemplarily described, but this does not limit the present disclosure.

[0125] Figure 5A A schematic diagram of a first sub-pixel in a display substrate 20 provided in at least one embodiment of the present disclosure, Figure 5B for Figure 5A Sectional view along section line II', Figure 5C for Figure 5A A cross-sectional view along section line II-II'. It should be noted that for the sake of clarity, Figure 5B and Figure 5C Some structures that do not have a direct electrical connection relationship at the cross-section lines are omitted.

[0126] like Figure 5A-5BAs shown, except for the first light-emitting control subcircuit (T8) in the pixel circuit of the first subpixel, the other subcircuits are all located in the first display area 22, and the first light-emitting control subcircuit and the light-emitting element 120 of the first subpixel are located in the second display area 23. The first light-emitting control subcircuit is connected to the pixel structure located in the first display area 22 through a connecting line 270. One end of the connecting line 270 is electrically connected to the first light-emitting control subcircuit through a via 352, and extends from the second display area 23 to the first display area 22 to be electrically connected to the first switch subcircuit and the second switch subcircuit. For example, the other end of the connecting line 270 is electrically connected to the second end (i.e., T5d) of the first switch subcircuit and the first end (i.e., T9s) of the second switch subcircuit through a via 351. For example, the material of the connecting line 270 is a transparent conductive material, which helps to improve the light transmittance of the second display area 23. Figure 5A Only the connection structures at both ends of the connection line 270 are shown, and the structure of the middle part of the connection line is schematically shown by a dotted line. The section line II′ extends from the first display area 22 to the second display area 23 along the connection line 270 .

[0127] Combination Figures 5A-5C It can be seen that the semiconductor layer 102, the first insulating layer 301, the first conductive layer 201, the second insulating layer 302, the second conductive layer 202, the third insulating layer 303, the third conductive layer 203, the fourth insulating layer 304, the fourth conductive layer 204, the fifth insulating layer 305, the fifth conductive layer 205, the sixth insulating layer 306, the sixth conductive layer 206, the seventh insulating layer 307 and the seventh conductive layer 207 are sequentially arranged on the base substrate 101, so as to form a Figure 5A The structure of the display substrate is shown.

[0128] Figure 6 Corresponds to Figure 5A The semiconductor layer 102 and the first conductive layer (gate layer) 201 of the transistors T1-T7 and T9 in the first display area 22 in the pixel circuit of the first sub-pixel are shown. Fig. 7A A second conductive layer 202 is shown, Figure 7B exist Figure 6 The second conductive layer 202 is shown on the basis of FIG. Fig. 8A A third conductive layer 203 is shown, Figure 8B exist Figure 7B The third conductive layer 203 is shown on the basis of FIG. Fig. 9A and 9B A fourth conductive layer 204 and a fifth conductive layer 205 are shown respectively.

[0129] For the convenience of explanation, in the following description, Tng, Tns, Tnd, and Tna are used to represent the gate, the first electrode, the second electrode, and the active layer of the nth transistor Tn, respectively, where n is 1-9.

[0130] It should be noted that the “same-layer arrangement” referred to in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process, and their materials may be the same or different. The “integrated structure” in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process and connected to each other, and their materials may be the same or different.

[0131] For example, Figure 6 As shown, the first conductive layer 201 includes the gate of each transistor and some scan lines and control lines. Figure 6 The gates T1g-T7g and T9g of the transistors T1-T7 and T9 in the first sub-pixel are shown in dashed boxes.

[0132] The semiconductor layer 102 includes active layers T1a-T7a and T9a of transistors T1-T7 and T9. Figure 6 As shown, the active layers of the transistors T1-T7 and T9 are connected to each other as an integrated structure. Figure 5C The first conductive layer further includes a gate T8g of an eighth transistor T8 located in the second display area 23, and the semiconductor layer 102 further includes an active layer T8a of the eighth transistor T8.

[0133] For example, the display substrate 20 adopts a self-alignment process and uses the first conductive layer 201 as a mask to perform conductorization treatment (such as doping treatment) on the semiconductor layer 102, so that the portion of the semiconductor layer 102 not covered by the first conductive layer 201 is conductorized, and thus the portion of the semiconductor layer located on both sides of the active layer (channel region) of each transistor is conductorized to form the first pole and the second pole of the transistor respectively.

[0134] The stability of the gate voltage of the driving transistor has an important influence on the display uniformity of the display substrate. For example, if the gate leakage of the driving transistor is serious, the gate voltage of the driving transistor will be insufficiently compensated in the threshold compensation stage, that is, the threshold voltage of the driving transistor cannot be fully compensated, so that the driving current in the light-emitting stage is still related to the threshold voltage Vth of the driving transistor, resulting in a decrease in the uniformity of the brightness of the display device.

[0135] For example, Figure 6As shown, the third transistor T3 and the sixth transistor T6 respectively adopt a dual-gate structure, which can improve the gate control ability of the transistor and reduce the leakage current. Since the third transistor T3 and the sixth transistor T6 are both transistors directly connected to the gate of the first transistor T1 (i.e., the driving transistor), the stability of the third transistor T3 and the sixth transistor T6 directly affects the stability of the gate (N1 node) voltage of the first transistor T1. The dual-gate structure is used to improve the gate control ability of the third transistor T3 and the sixth transistor T6, which helps to reduce the leakage current of the transistor and thus helps to maintain the voltage of the N1 node, so that in the compensation stage, the threshold voltage of the first transistor T1 helps to be fully compensated, thereby improving the display uniformity of the display substrate in the light-emitting stage.

[0136] For example, the first conductive layer 201 further includes a plurality of scan lines 210, a plurality of reset control lines 220 and a plurality of light emitting control lines 230 which are insulated from each other. Figure 6 As shown, each row of sub-pixels corresponds to a reset control line 220, a scan line 210, a second light-emitting control line 230, and a first light-emitting control line (280, 290).

[0137] The scan line 210 is electrically connected to the gate of the second transistor T2 in the corresponding row of sub-pixels (or is an integrated structure) to provide a first scan signal Ga1, the reset control line 220 is electrically connected to the gate of the sixth transistor T6 in the corresponding row of sub-pixels to provide a second reset control signal Rst2, and the second light-emitting control line 230 is electrically connected to the gate of the fourth transistor T4 in the corresponding row of sub-pixels to provide a second light-emitting control signal EM2.

[0138] For example, Figure 6 As shown, the scan line 210 is also electrically connected to the gate of the third transistor T3 to provide a second scan signal Ga2, that is, the first scan signal Ga1 and the second scan signal Ga2 can be the same signal; the light-emitting control line 230 is also electrically connected to the gate of the fifth transistor T5 to provide a first switch control signal SW1, that is, the first light-emitting control signal EM1 and the second light-emitting control signal EM2 are the same signal.

[0139] For reference Figure 5A and Figure 5C The first light-emitting control line includes a first light-emitting control line portion 280 (an example of the auxiliary light-emitting control line of the present disclosure) located in the first display area 22 and a second light-emitting control line portion 290 located in the second display area 23. The first light-emitting control line portion 280 and the second light-emitting control line portion 290 are electrically connected to each other (such as Figure 5AThe second light-emitting control line portion 290 is electrically connected to the gate of the eighth transistor T8 (an example of the light-emitting control transistor of the present disclosure) of the corresponding row of sub-pixels (or is an integrated structure) to provide the first light-emitting control signal EM1, and the first light-emitting control line portion 280 is electrically connected to the gate of the ninth transistor T9 of the corresponding row of sub-pixels (or is an integrated structure) to provide the second switch control signal SW2, that is, in the embodiment of the present disclosure, the first light-emitting control signal EM1 and the second switch control signal SW2 are the same signal, but this does not limit the present disclosure. For example, the material of the second light-emitting control line portion 290 is a transparent conductive material to improve the transmittance of the second display area 23.

[0140] For example, a second sub-pixel is provided in the main display area 21. For example, the second sub-pixel is an in-situ luminescent sub-pixel. All sub-circuits (transistors) in the pixel circuit of the second sub-pixel are located in the main display area 21. That is, the first luminescence control sub-circuit does not interact with other sub-circuits. Figure 5A For example, the pixel circuit of the second sub-pixel may not include the second switch sub-circuit, for example, Figure 1A-1B or Figure 2A-2B In this case, the first light emitting control subcircuit may be located as shown in FIG. Figure 5A The position of the second switch sub-circuit shown in FIG. 1 is where the eighth transistor T8 is located, that is, the position of the ninth transistor T9 is located, and Figure 5A The first light emitting control line portion 280 shown in FIG. 2 serves as the first light emitting control signal EM1 for controlling the first light emitting control sub-circuit.

[0141] Therefore, in Figure 5A In the pixel circuit shown, the provision of the second switch subcircuit (T9) and the first light emitting control line portion 280 helps to improve the uniformity of the arrangement of the pixel circuits in the second display area 23 and the first display area 21, thereby improving the process uniformity in the manufacturing process.

[0142] For example, the gate of the seventh transistor T7 of the pixel circuit in this row is electrically connected to the reset control line 220 corresponding to the pixel circuit in the next row (i.e., the pixel circuit row where the scan line that is sequentially turned on after the scan line in this row according to the scan order of the scan lines) to receive the first reset control signal Rst1.

[0143] For example, Figure 7A-7BAs shown, the second conductive layer 202 includes a first capacitor electrode Ca. The first capacitor electrode Ca overlaps with the gate T1g of the first transistor T1 in a direction perpendicular to the substrate 101 to form a storage capacitor Cst, that is, the gate T1g of the first transistor T1 serves as the second capacitor electrode Cb of the storage capacitor Cst. For example, the first capacitor electrode Ca includes an opening 222, and the opening 222 exposes at least a portion of the gate T1g of the first transistor T1, so that the gate T1g is electrically connected to other structures.

[0144] For example, the second conductive layer 202 may further include a plurality of reset voltage lines 240 extending along the first direction D1, the plurality of reset voltage lines 240 being connected one-to-one with a plurality of rows of sub-pixels. The reset voltage line 240 is electrically connected to the first electrode of the sixth transistor T6 in a corresponding row of sub-pixels to provide a second reset voltage Init2.

[0145] For example, combined with reference Figure 7B and 8B , the first electrode of the seventh transistor T7 in the sub-pixel of this row is electrically connected to the reset voltage line 240 corresponding to the sub-pixel of the next row to receive the first reset voltage Init1.

[0146] For example, Figure 7A-7B As shown, the second conductive layer 202 may further include a shielding electrode 221. For example, the shielding electrode 221 overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the base substrate 101, thereby protecting the signal in the first electrode T2s of the second transistor T2 from interference by other signals. Since the first electrode T2s of the second transistor T2 is configured to receive a data signal Vd, and the data signal Vd determines the display grayscale of the sub-pixel, the shielding electrode 221 improves the stability of the data signal, thereby improving the display performance.

[0147] For example, combined with reference Figure 7B and Figure 6 The shielding electrode 221 also at least partially overlaps with the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the substrate 101 to improve the stability of the signal on the second electrode T6d, thereby improving the stability of the sixth transistor T6 and further stabilizing the gate voltage of the first transistor T1.

[0148] For example, the shielding electrode 221 and the first electrode T2s of the second transistor T2 and the second electrode T6d of the sixth transistor T6 that are directly opposite (overlapping) therewith form a stable capacitor. For example, the shielding electrode 221 is configured to load a fixed voltage. Since the voltage difference across the capacitor cannot change suddenly, the stability of the voltage on the first electrode T2s of the second transistor T2, the conductive area T3c of the third transistor T3, and the second electrode T6d of the sixth transistor T6 is improved. For example, the shielding electrode 221 is electrically connected to the power line 250 in the third conductive layer 203 to load the first power supply voltage VDD.

[0149] For example, Figure 7A-7B As shown, the shielding electrode 221 is L-shaped or V-shaped, and includes a first branch 221a and a second branch 221b extending in different directions. The first branch 221a at least partially overlaps with the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the substrate 101; the second branch 221b at least partially overlaps with the first electrode T2s of the second transistor T2 in a direction perpendicular to the substrate 101. For example, the first branch 221a extends along the second direction D2, and the second branch 221b extends along the first direction D1.

[0150] For example, Figures 8A-8B As shown, the third conductive layer 203 includes a plurality of power lines 250 extending along the second direction D2. For example, the plurality of power lines 250 are electrically connected to a plurality of columns of sub-pixels one by one to provide a first power supply voltage VDD. Figure 6 The power line 250 is electrically connected to the first capacitor electrode Ca in the corresponding column of sub-pixels through the via 342, and is electrically connected to the first electrode T4d of the fourth transistor T4 through the via 343. For example, the power line 250 is also electrically connected to the shielding electrode 221 through the via 341, so that the shielding electrode 221 has a fixed potential, thereby improving the shielding ability of the shielding electrode. For example, the via 342 and the via 341 both penetrate the third insulating layer 303, and the via 343 penetrates the first insulating layer 301, the second insulating layer 302 and the third insulating layer 303.

[0151] For example, the third conductive layer 203 further includes a plurality of data lines 12 extending along the second direction D2. For example, the plurality of data lines 12 are electrically connected to a plurality of columns of sub-pixels one by one to provide data signals. For example, the data line 12 is electrically connected to a first electrode T2s of a second transistor T2 in a corresponding column of sub-pixels through a via 346 to provide the data signal. For example, the via 346 passes through the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303.

[0152] For example, the data line 12 includes a data line main body extending along the second direction D2, and the line width of the data line main body is relatively small. In order to facilitate the setting of the via hole, the data line 12 also includes a data line protrusion 121 extending from its data line main body, and the data line protrusion 121 at least partially overlaps with the via 346 in a direction perpendicular to the base substrate.

[0153] For example, combined with Figure 5A-5B , Figures 8A-8B As shown, the third conductive layer 203 further includes a connecting electrode 231, one end of which is electrically connected to the gate T1g of the first transistor T1, i.e., the second capacitor electrode Cb, through the opening 222 in the first capacitor electrode Ca and the via 344 in the insulating layer, and the other end is electrically connected to the second electrode T3d of the third transistor T3 through the via 345, thereby electrically connecting the second capacitor electrode Cb to the second electrode T3d of the third transistor T3. For example, the via 344 penetrates the second insulating layer 302 and the third insulating layer 303. For example, the via 345 penetrates the first insulating layer 301, the second insulating layer 302 and the third insulating layer 303.

[0154] For example, combined with Figure 5A-5B , Figure 6 , Figures 8A-8B As shown, the third conductive layer 203 further includes a connecting electrode 232, which is electrically connected to the second electrode T5d of the fifth transistor T5 through a via hole 349, and is also electrically connected to the connecting line 270 through a via hole 351. For example, the via hole 349 penetrates the first insulating layer 301, the second insulating layer 302, and the third insulating layer 303. The via hole 351 penetrates the fourth insulating layer 304 and the fifth insulating layer 305.

[0155] For example, Figures 8A-8B As shown, the third conductive layer 203 further includes a connecting electrode 233, one end of which is electrically connected to the reset voltage line 240 through a via 348, and the other end of which is electrically connected to the first electrode T7s of the seventh transistor T7 through a via 347, so that the first electrode T7s of the seventh transistor T7 can receive the first reset voltage Init1 from the reset voltage line 240. For example, the via 348 penetrates the third insulating layer 303. For example, the via 347 penetrates the first insulating layer 301, the second insulating layer 302 and the third insulating layer 303.

[0156] For example, Figures 8A-8BAs shown, the third conductive layer 203 further includes a connecting electrode 234, and the connecting electrode 234 is electrically connected to the first electrode T9s of the ninth transistor T9 and the second electrode T7d of the seventh transistor through a via hole (not shown). The connection electrode 234 is provided to be consistent with the pattern of the third conductive layer 203 in the main display area 21 to improve etching uniformity. For example, in the main display area 21, the second electrode T7d of the seventh transistor is electrically connected to the first electrode of the light-emitting element through the connecting electrode 234.

[0157] For example, Figure 8B Two reset voltage lines 240 are shown. The reset voltage line 240 corresponding to the first electrode of the seventh transistor T7 in the previous row of sub-pixels is connected to the first end of the sixth transistor T6 of the current row of sub-pixels to provide a second reset voltage Init2. The reset voltage line 240 corresponding to the first electrode of the seventh transistor T7 in the current row of sub-pixels is connected to the sixth transistor T6 of the next row of sub-pixels to provide a second reset voltage Init2.

[0158] like Fig. 9A As shown, the fourth conductive layer 204 includes a connecting electrode 241 and a shielding electrode 242. Figure 3A , the connecting electrode 241 is electrically connected to the connecting electrode 234 through a via hole (not shown). The connection electrode 241 is provided to be consistent with the pattern of the fourth conductive layer 204 in the main display area 21 to improve etching uniformity. For example, in the main display area 21, the second electrode T7d of the seventh transistor is electrically connected to the first electrode of the light-emitting element through the connecting electrode 234 and the connecting electrode 241.

[0159] For example, in a direction perpendicular to the substrate, the shielding electrode 242 at least partially overlaps the connecting electrode 231 to shield the connecting electrode 231, thereby improving the stability of the gate signal of the first transistor T1 (i.e., the driving transistor). Fig. 9B The connecting line 270') is electrically connected to the first light-emitting control subcircuit in the second pixel area 23. The connecting line is likely to overlap with the connecting electrode 231 in a direction perpendicular to the substrate during the extension process, and the signal on the connecting line is likely to affect the gate signal on the connecting electrode 231. The stability of the gate signal of the driving transistor can be improved by providing the shielding electrode 242, thereby improving the display quality. For example, the shielding electrode 242 is electrically connected to the power line 250 through a via (not shown) to load the first power supply voltage VDD.

[0160] For example, the orthographic projection of the shielding electrode 242 on the base substrate covers the orthographic projection of the connecting electrode 231 on the base substrate, thereby improving the shielding effect.

[0161] For example, the shielding electrode 242 also at least partially overlaps with the second electrode T6d of the sixth transistor T6 in a direction perpendicular to the substrate 101 to improve the stability of the signal on the second electrode T6d, thereby improving the stability of the sixth transistor T6 and further stabilizing the gate voltage of the first transistor T1.

[0162] Fig. 9B FIG. 2 shows a pattern of the fifth conductive layer 205 corresponding to the position of the first sub-pixel. Fig. 9B As shown, the fifth conductive layer 205 includes, in addition to the bottom connection line 270 connected to the first sub-pixel, a plurality of connection lines 270' connected to other sub-pixels. The connection lines 270' pass through the location of the first sub-pixel during the extension process.

[0163] For example, reference Figure 5A and 5C The third conductive layer 203 may further include a connecting electrode 235 located in the second display area 23, and the fourth conductive layer 204 may further include a connecting electrode 243 located in the second display area 23. The connecting electrode 235 and the connecting electrode 243 are provided corresponding to the eighth transistor T8. For example, the number of the connecting electrode 235 and the number of the connecting electrode 243 are two, respectively. The two connecting electrodes 235 and the two connecting electrodes 243 are provided correspondingly, and are provided correspondingly to the two ends of the gate T8g of the eighth transistor T8, respectively. The two ends of the gate T8g are electrically connected to the second light emitting control line portion 290 above through the corresponding connecting electrodes 235 and 243, respectively.

[0164] For example, reference Figures 5A-5CThe third conductive layer 203 may further include a connection electrode 236 (an example of the first connection electrode of the present disclosure) and a connection electrode 237 located in the second display area 23. The connection electrodes 236 and 237 are respectively arranged corresponding to the first electrode T8s and the second electrode T8d of the eighth transistor T8. The connection electrode 236 is electrically connected to the first electrode T8s of the eighth transistor T8 through a via hole 355 (an example of the first via hole of the present disclosure), and the connection electrode 237 is electrically connected to the second electrode T8d of the eighth transistor through a via hole 354 (an example of the second via hole of the present disclosure). The connection electrode 236 is also electrically connected to the upper connection line 270 through a via hole 352 (another example of the first via hole of the present disclosure), thereby electrically connecting the first electrode T8s of the eighth transistor T8 to the connection line 270. For example, the fourth conductive layer 204 may also include a connecting electrode 244, which is arranged corresponding to the connecting electrode 237 and is electrically connected to the connecting electrode 236 through a via 353 (another example of a second via in the present disclosure), and the connecting electrode 236 is electrically connected to the first electrode 134 of the light-emitting element above through a via 340, thereby electrically connecting the second electrode T8d of the eighth transistor T8 to the first electrode 134 of the light-emitting element.

[0165] The above-mentioned connecting electrodes 235, 236, 237, 243, and 244 all serve as transfer electrodes, which lead out the first electrode / second electrode of the transistor located below so as to be electrically connected to the conductive structure (signal line or electrode) above. This arrangement can avoid the situation in which the via hole directly penetrates in the direction perpendicular to the substrate, resulting in excessive filling depth of the conductive material, leading to poor connection, broken wires or unevenness. By setting the transfer electrodes, the depth of the via hole is reduced and the contact yield is improved.

[0166] like Figure 5B As shown, the vias 340 , 353 , and 354 at the second electrode of the eighth transistor T8 do not overlap in the direction perpendicular to the substrate.

[0167] refer to Figures 5A-5C The fifth conductive layer 205 includes a connecting line 270 extending from the first display area 22 to the second display area 23 to connect the circuit structure in the first display area 22 with the circuit structure in the second display area 23. One end of the connecting line 270 is electrically connected to the second electrode T5d of the fifth transistor T5 / the first electrode T9s of the ninth transistor T9 through the via hole 351, and the other end is electrically connected to the first electrode T8s of the eighth transistor T8 through the via hole 352.

[0168] refer to Figures 5A-5CThe sixth conductive layer 206 includes a second light-emitting control line portion 290. For example, the second light-emitting control line portion 290 is located in the second display area 23. The second light-emitting control line portion 290 is electrically connected to the connecting electrode 243 below through a via hole, thereby connecting to the gate T8g of the eighth transistor T8 to provide a first light-emitting control signal EM1.

[0169] refer to Figure 5A-5B , the seventh conductive layer 207 includes the first electrode 134 of the light emitting element 120 .

[0170] For example, refer to Figure 5A-5B , the display substrate 20 may further include a pixel defining layer 308 located on the first electrode of the light-emitting element. An opening is formed in the pixel defining layer 308 to expose at least part of the pixel electrode 134, thereby defining an opening area (i.e., an effective light-emitting area) 600 of each sub-pixel of the display substrate. The light-emitting layer 136 of the light-emitting element 120 is at least formed in the opening (the light-emitting layer 136 may also cover part of the surface of the pixel defining layer away from the first electrode of the light-emitting element), and the second electrode 135 is formed on the light-emitting layer 136 to form the light-emitting element 120. For example, the second electrode 135 is a common electrode, which is arranged in the display substrate 20 on its entire surface. For example, the pixel electrode 134 is the anode of the light-emitting element, and the second electrode 135 is the cathode of the light-emitting element.

[0171] Figure 5A The position of the opening area 600 is shown on the first electrode of the light-emitting element. For example, the first electrode 134 includes an electrode main body 134a and an electrode protrusion 134b, the electrode main body 134a is used to contact the light-emitting layer 136 of the light-emitting element, and the electrode protrusion 134b is electrically connected to the connection electrode 244 through the via 340; the electrode main body 134a and the via 340 do not overlap in a direction perpendicular to the substrate, thereby preventing the via 340 from affecting the flatness of the light-emitting layer in the opening area and thus affecting the light-emitting quality. For example, the shape of the electrode main body 134a is a polygon, such as a quadrilateral, a pentagon or a hexagon. For example, the electrode main body 134a has a symmetry axis extending along the second direction.

[0172] For example, Figure 5A-5B As shown, the orthographic projection of the first electrode 134 of the light-emitting element on the substrate completely covers the orthographic projection of the connecting electrode 236 on the substrate. This is because the connecting electrode 236 is usually a metal material with low light transmittance, so this arrangement can prevent the connecting electrode 236 from affecting the light transmittance of the second display area 23, and can also prevent the connecting electrode 236 from occupying the effective opening area, thereby improving the aperture ratio of the display substrate.

[0173] For example, Figure 5A-5BAs shown, the orthographic projection of the via 340 / 353 / 354 at the second electrode of the eighth transistor T8 on the substrate is farther away from the orthographic projection of the electrode main body 134a of the first electrode of the light-emitting element on the substrate than the orthographic projection of the via 352 / 355 at the first electrode of the eighth transistor T8 on the substrate.

[0174] Since there are a large number of vias at the second electrode of the eighth transistor T8 and the total depth is deep, the vias at the second electrode of the eighth transistor T8 have a greater impact on the flatness of the first electrode of the light-emitting element above. Therefore, setting the vias at the second electrode of the eighth transistor T8 away from the electrode main body 134a can prevent the vias from affecting the flatness of the electrode main body 134a and the light-emitting layer thereon, thereby affecting the light-emitting quality.

[0175] For example, refer to Figure 5A-5B In the direction perpendicular to the substrate, the connecting line 270 is likely to overlap at least partially with other conductive structures (such as the first electrode 134 of the light-emitting element of the first sub-pixel and / or the first electrode of the light-emitting element of other sub-pixels) during the extension process, thereby forming a parasitic capacitor Cp. By setting the eighth transistor T8 between the connecting line 270 and the first electrode of the light-emitting element, the connecting line 270 is prevented from being directly connected to the light-emitting element, thereby effectively reducing the adverse effect of the parasitic capacitance existing at the connecting line on the light emission. For example, the connecting line can be pre-charged before the light-emitting stage arrives (for example, charged to the light-on voltage of the light-emitting element); and after entering the light-emitting stage, the potential prepared on the connecting line 270 is quickly copied to the first electrode of the light-emitting element, thereby avoiding the display unevenness (Mura) phenomenon caused by the charging time required for the parasitic capacitance crowding out the light-emitting time, thereby improving the uniformity of light emission.

[0176] For example, refer to Figure 5A-5B , in a direction perpendicular to the substrate, the connection line 270 at least partially overlaps with the electrode main body of the first electrode of the light-emitting element; the second light-emitting control line portion 290 at least partially overlaps with the first electrode of the light-emitting element but does not overlap or almost does not overlap with the electrode main body 134a. For example, in a direction perpendicular to the substrate, the second light-emitting control line portion 290 is located on a side of the connection line 270 close to the first electrode 134 of the light-emitting element, thereby preventing the connection line 270 from affecting the flatness of the light-emitting layer in the opening area.

[0177] For example, the base substrate 101 can be a rigid substrate, such as a glass substrate, a silicon substrate, etc., or it can be formed of a flexible material with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyarylate, polyetherimide, polyethersulfone, polyethylene terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cycloolefin polymer (COP) and cycloolefin copolymer (COC), etc.

[0178] For example, the material of the semiconductor layer 102 includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.).

[0179] For example, the materials of the first to fourth conductive layers may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by combinations of the above metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0180] For example, the material of the fifth conductive layer 205 and the sixth conductive layer 206 is a transparent conductive material, such as a metal oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0181] For example, the light emitting element 120 is a top emission structure, the first electrode (i.e., pixel electrode) 134 is reflective and the second electrode 135 is transmissive or semi-transmissive. For example, the first electrode 134 is an anode and the second electrode 135 is a cathode. For example, the first electrode 134 is an ITO / Ag / ITO laminated structure, the transparent conductive material ITO is a material with a high work function, and direct contact with the light emitting material can improve the hole injection rate; the metal material Ag helps to improve the reflectivity of the first electrode. For example; the second electrode 135 is a material with a low work function to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0182] For example, the first insulating layer 301, the second insulating layer 302, the third insulating layer 303, the fourth insulating layer 304, the fifth insulating layer 305, and the sixth insulating layer 306 are, for example, inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxide, or aluminum oxide, titanium nitride, or other insulating materials including metal nitride oxides. For example, the seventh insulating layer 307 and the pixel defining layer 308 are respectively organic insulating materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), or other organic insulating materials. For example, the seventh insulating layer 307 is a planarization layer; for example, the material of the seventh insulating layer 307 is a photoresist material.

[0183] At least one embodiment of the present disclosure further provides a display device, which includes the display substrate 20 provided in any of the above embodiments and a sensor. Fig. 10A shows a schematic structural diagram of a display device 40 provided in some embodiments of the present disclosure, Fig. 10B for Fig. 10A Sectional view along section line CC'.

[0184] like Fig. 10A As shown, the sensor 401 is arranged corresponding to the second display area 23 of the display substrate 20 and is arranged on the side of the display substrate opposite to the display side, for example, it is arranged on the side of the base substrate 101 away from the light-emitting element. The sensor 401 is, for example, a photoelectric sensor, configured to receive light from the first side of the display substrate and convert the light into an electrical signal for forming an image. For example, the light reaches the sensor from the display side through the second display area 23, for example, the light is visible light or infrared light. For example, in a direction perpendicular to the base substrate, the sensor 401 at least partially overlaps with the first light-emitting control subcircuit (for example, the eighth transistor T8) of the first sub-pixel.

[0185] For example, the display device 40 also includes an encapsulation layer 208 and a cover plate 209 disposed on the display substrate 20, and the encapsulation layer 208 is configured to seal the light-emitting element in the display substrate 20 to prevent external moisture and oxygen from penetrating into the light-emitting element and the driving circuit and causing damage to the device. For example, the encapsulation layer 208 includes an organic film or a structure including an organic film and an inorganic film alternately stacked. For example, a water-absorbing layer (not shown) can also be disposed between the encapsulation layer 208 and the display substrate 20, configured to absorb residual water vapor or sol of the light-emitting element in the early production process. The cover plate 208 is, for example, a glass cover plate. For example, the cover plate 209 and the encapsulation layer 208 can be an integrated structure.

[0186] For example, the sensor 401 may be attached to the back side (the side opposite to the display surface) of the display substrate 20. Fig. 10BAs shown, the imaging element 401 is attached to a side of the substrate 101 away from the second electrode 136 of the light emitting element. The sensor 401 can be implemented as a camera, for example.

[0187] The display device can be, for example, a digital photo frame, a smart bracelet, a smart watch, a mobile phone, a tablet computer, a display, a laptop computer, a navigator, or any other product or component with a display function.

[0188] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

Claims

1. A pixel circuit, comprising: a driving subcircuit, comprising a control terminal connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third node, wherein the driving subcircuit is configured to control a driving signal from the first node to the third node and used to drive the light-emitting element according to a voltage of the first node; a data writing subcircuit connected to the second node and configured to write a data signal into the second node in response to a first scanning signal; a compensation subcircuit connected to the first node and the third node, and configured to conduct the first node and the third node in response to a second scan signal, thereby controlling the driving subcircuit to write a compensation voltage to the first node based on a data signal written to the second node; a first switch subcircuit configured to control conduction of the drive signal between the third node and the fourth node in response to a first switch control signal and based on a voltage of the third node; a first light-emitting control subcircuit connected to the fourth node and the fifth node, and connected to the first electrode of the light-emitting element through the fifth node, the first light-emitting control subcircuit being configured to control conduction of the drive signal between the fourth node and the fifth node in response to a first light-emitting control signal, so that the drive signal can be applied to the light-emitting element; as well as The first reset sub-circuit is connected to the fourth node and is configured to write a first reset voltage to the fourth node in response to a first reset control signal.

2. The pixel circuit according to claim 1, further comprising a second light emitting control subcircuit, in, The second light emitting control subcircuit is connected to the second node and the first power supply voltage terminal, and is configured to write the first power supply voltage from the first power supply voltage terminal into the second node in response to a second light emitting control signal.

3. The pixel circuit according to claim 2, further comprising a storage subcircuit, in, The storage sub-circuit includes a first terminal and a second terminal, and the first terminal and the second terminal of the storage sub-circuit are connected to the first power supply voltage terminal and the first node respectively.

4. The pixel circuit as claimed in claim 2, further comprising a second reset subcircuit, in, The second reset sub-circuit is connected to the first node and is configured to write a second reset voltage into the first node in response to a second reset control signal.

5. The pixel circuit according to claim 1, further comprising a first capacitor, in, The first capacitor includes a first electrode and a second electrode. The first electrode of the first capacitor is connected to the fourth node. The second electrode of the first capacitor is configured to apply the same voltage as the second electrode of the light-emitting element.

6. The pixel circuit as claimed in claim 1, further comprising a second capacitor, in, A first electrode of the second capacitor is connected to the fourth node, and a first electrode of the light emitting element serves as a second electrode of the second capacitor.

7. A display substrate, comprising: substrate substrate; A plurality of sub-pixels are distributed in an array on the substrate along a first direction and a second direction; The plurality of sub-pixels include a first sub-pixel, and the first sub-pixel includes a pixel circuit and a light-emitting element; the pixel circuit includes: a driving subcircuit, comprising a control terminal connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third node, wherein the driving subcircuit is configured to control a driving signal from the first node to the third node and used to drive the light emitting element according to a voltage of the first node; a data writing subcircuit connected to the second node and configured to write a data signal into the second node in response to a first scanning signal; a compensation subcircuit connected to the first node and the third node, and configured to conduct the first node and the third node in response to a second scan signal, thereby controlling the driving subcircuit to write a compensation voltage to the first node based on a data signal written to the second node; a first switch subcircuit configured to control conduction of the drive signal between the third node and a fourth node in response to a first switch control signal and based on a voltage of the third node; and a first light-emitting control subcircuit connected to the fourth node and the fifth node, and connected to the first electrode of the light-emitting element through the fifth node, the first light-emitting control subcircuit being configured to control conduction of the drive signal between the fourth node and the fifth node in response to a first light-emitting control signal, so that the drive signal can be applied to the light-emitting element; The display substrate comprises a first display area and a second display area, wherein the first display area at least partially surrounds the second display area; The driving subcircuit and the first switch subcircuit of the pixel circuit are both located in the first display area, and the first light emitting control subcircuit and the light emitting element of the pixel circuit are located in the second display area.

8. The display substrate according to claim 7, further comprising a connecting line, in, One end of the connecting line is electrically connected to the first light-emitting control subcircuit, and the other end extends to the first display area to be electrically connected to the first switch subcircuit; The connecting wire is made of transparent conductive material.

9. The display substrate according to claim 8, wherein: In a direction perpendicular to the base substrate, the connecting line at least partially overlaps with the first electrode of the light emitting element.

10. The display substrate according to claim 8, wherein: The first light emission control subcircuit comprises a light emission control transistor, The first electrode of the light emitting control transistor is electrically connected to the connecting line through a first via hole; The second electrode of the light emitting control transistor is electrically connected to the first electrode of the light emitting element through a second via hole.

11. The display substrate according to claim 10, further comprising a first connection electrode, The first connection electrode is located on a side of the connection line close to the base substrate. The first electrode of the light emission control transistor is electrically connected to the connection line through the first connection electrode.

12. The display substrate according to claim 11, wherein: The orthographic projection of the first electrode of the light emitting element on the base substrate covers the orthographic projection of the first connecting electrode on the base substrate.

13. The display substrate according to claim 10, wherein: The first electrode of the light emitting element includes an electrode main body and an electrode protrusion protruding from the electrode main body. The electrode main body is used to contact the light-emitting layer of the light-emitting element, and the electrode protrusion is electrically connected to the second electrode of the light-emitting control transistor through the second via hole; The orthographic projection of the second via hole on the base substrate is farther away from the orthographic projection of the electrode main body on the base substrate than the orthographic projection of the first via hole on the base substrate.

14. The display substrate according to claim 10, further comprising a light emitting control line located in the second display area, in, The material of the light emitting control line is a transparent conductive material; The light emission control line is electrically connected to the gate of the light emission control transistor to provide the light emission control signal.

15. The display substrate according to claim 14, wherein: In a direction perpendicular to the base substrate, the light emitting control line is located on a side of the connecting line close to the first electrode of the light emitting element.

16. The display substrate according to claim 14, in, In a case where the pixel circuit further includes a second switch subcircuit, the second switch subcircuit is located in the first display area, and the display substrate further includes an auxiliary light emitting control line located in the first display area. The second switch sub-circuit is connected to the auxiliary light emitting control line to receive the second switch control signal; The auxiliary light emitting control line is electrically connected to the light emitting control line.

17. A display device, comprising the display substrate according to any one of claims 7 to 16.

18. The display device according to claim 17, further comprising a sensor, in, The display substrate has a first side for display and a second side opposite to the first side; The sensor is disposed on the second side of the display substrate and is configured to receive light from the first side of the display substrate and through the second display area for sensing.

19. A method for driving a pixel circuit, the pixel circuit comprising: a driving subcircuit, comprising a control terminal connected to the first node, a first terminal connected to the second node, and a second terminal connected to the third node, wherein the driving subcircuit is configured to control a driving signal from the first node to the third node and used to drive the light-emitting element according to a voltage of the first node; a data writing subcircuit connected to the second node and configured to write a data signal into the second node in response to a first scanning signal; a compensation subcircuit connected to the first node and the third node, and configured to conduct the first node and the third node in response to a second scan signal, thereby controlling the driving subcircuit to write a compensation voltage to the first node based on a data signal written to the second node; a first switch subcircuit configured to control conduction of the drive signal between the third node and the fourth node in response to a first switch control signal and based on a voltage of the third node; as well as a first light-emitting control subcircuit connected to the fourth node and the fifth node, and connected to the first electrode of the light-emitting element through the fifth node, the first light-emitting control subcircuit being configured to control conduction of the drive signal between the fourth node and the fifth node in response to a first light-emitting control signal, so that the drive signal can be applied to the light-emitting element; The driving method comprises: In the data writing and compensation stage, the data writing subcircuit is turned on and the first switch subcircuit and the first light emitting control subcircuit are turned off, so that the data signal is written into the second node and the driving subcircuit is compensated; In the pre-charging stage, the first switch sub-circuit is turned on and the first light-emitting control sub-circuit is turned off to charge the fourth node so that the potential of the fourth node reaches a predetermined value; In the light-emitting stage, the first switch subcircuit and the first light-emitting control subcircuit are turned on, the potential of the fourth node is applied to the fifth node, and the driving signal is applied to the light-emitting element to make the light-emitting element emit light.

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