A multiplexer detection circuit, device and performance detection method

Abstract

The present application relates to the technical field of detection, and particularly provides a performance detection circuit, device and method of multiplexer, the circuit comprises: a test interface circuit, an input end is connected with a main path socket and a branch path socket of a to-be-tested multiplexer, the test interface circuit is used for being connected with the to-be-tested multiplexer and judging the on-off of each connection branch; a logic gate circuit, an input end is connected with an output end of the test interface circuit. The performance detection circuit of multiplexer provided in the present application is based on a logic gate, cooperates with a buzzer circuit, connects the main path and branch path aviation socket of the multiplexer to the corresponding main path interface and branch path interface in the performance detection device respectively, realizes automatic detection of the multiplexer, and the detection device is simple to operate, and efficient detection of batch production products is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of detection, in particular to a multiplexer detection circuit, device and performance detection method. BACKGROUND

[0002] The multi-parameter intelligent water meter is an online comprehensive multi-parameter measuring instrument, including the measurement of water quantity, water quality and water pressure and other parameters. The multiplexer is an intermediate component connecting the data acquisition instrument and the sensor of the multi-parameter intelligent water meter, and is used for combining the signals of the multi-path sensor into a single signal and transmitting the single signal to the data acquisition instrument.

[0003] The multiplexer needs to be tested for performance before leaving the factory. In the existing test technology, when the multiplexer is detected, plugs need to be connected to the aviation socket interfaces of the four branches and one main path of the multiplexer. The other end of the plug has a wire leading out for use by a multimeter. Among the four branches, three are 4 channels, one is 3 channels, and the main path is 9 channels. The multimeter is used to test whether each channel between each branch and the main path is conductive. If all channels are conductive, the test is passed, otherwise there is a fault. This test method is relatively cumbersome and is not conducive to batch detection.

[0004] The existing test technology cannot solve these defects. Therefore, a performance detection device for the multiplexer of the multi-parameter intelligent water meter needs to be designed to replace the existing test method, which is simple to operate and can improve the test efficiency. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a performance detection circuit, device and performance detection method for a multiplexer to reduce detection complexity and improve detection efficiency.

[0006] In a first aspect, the embodiments of the present application provide a performance detection circuit for a multiplexer, which comprises: a test interface circuit, an input end of which is connected with a main path socket and a branch socket of a multiplexer to be tested, the test interface circuit being used to connect with the multiplexer to be tested and judge the continuity of each connection branch;

[0007] a logic gate circuit, an input end of which is connected with an output end of the test interface circuit, the logic gate circuit being used to receive the level state of the test interface circuit and output a corresponding level state according to a logic gate rule;

[0008] a buzzer circuit, an input end of which is connected with an output end of the logic gate circuit, the buzzer circuit being used to receive the level state output by the logic gate and emit a buzzing sound when the level state is a high level state to prompt that the performance of the multiplexer to be tested is good;

[0009] a power supply circuit, which is respectively connected with the test interface circuit, the logic gate circuit and the buzzer circuit.

[0010] As an implementable way, the test interface circuit comprises:

[0011] The main road interface module comprises first to ninth pins, which are respectively connected and grounded; the main road interface module is connected with the main road socket of the multiplexer;

[0012] The branch interface module has four, the input end of the four branch interface modules is respectively connected with the branch interface of the multiplexer, and the output end is connected with the input end of a logic gate circuit;

[0013] Among them, three branch interface modules include first to fourth pins, and one branch interface module includes first to third pins. Each branch interface module is connected with the input end of the logic gate circuit through a pin.

[0014] As an implementable way, the branch interface module comprises:

[0015] The branch interface comprises a plurality of pins;

[0016] The anode of the light-emitting diode is electrically connected with the power supply circuit, and the cathode is electrically connected with the pin;

[0017] Among them, the number of light-emitting diodes is matched with the number of pins.

[0018] As an implementable way, the logic gate comprises:

[0019] The first or gate chip comprises two first-stage or gates and one second-stage or gate. The input end of one of the first-stage or gates is electrically connected with the first pin and the second pin of the first branch interface module; the input end of the other first-stage or gate is electrically connected with the third pin and the fourth pin of the first branch interface module; the output ends of the two first-stage or gates are respectively electrically connected with the input ends of the second-stage or gate;

[0020] The second or gate chip comprises two first-stage or gates, one second-stage or gate and one third-stage or gate. The input end of one of the first-stage or gates is electrically connected with the first pin to the second pin of the second branch interface module, and the input end of the other first-stage or gate is electrically connected with the third pin to the fourth pin of the second branch interface module. The output ends of the two first-stage or gates are respectively connected with the input ends of the second-stage or gate. The output end of the second-stage or gate and the output end of the second-stage or gate of the first or gate chip are respectively electrically connected with the input end of the third-stage or gate;

[0021] a third OR gate chip comprising two first stage OR gates, one second stage OR gate, one input terminal of the first stage OR gate being electrically connected with the first to second pins of the third branch interface module, the other input terminal of the first stage OR gate being electrically connected with the third to fourth pins of the third branch interface module; the output terminals of the two first stage OR gates being respectively connected with the input terminals of the second stage OR gate;

[0022] a fourth OR gate chip comprising one first stage OR gate, one second stage OR gate, one third stage OR gate and one fourth stage OR gate; one input terminal of the first stage OR gate being electrically connected with the first to second pins of the fourth branch interface module, the other input terminal of the first stage OR gate being electrically connected with the third pin of the second branch interface module and the output terminal of the first stage OR gate; the output terminal of the second stage OR gate and the output terminal of the second stage OR gate of the third OR gate chip being respectively connected with the input terminal of the third stage OR gate, the output terminal of the third stage OR gate and the output terminal of the third stage OR gate of the second OR gate chip being respectively electrically connected with the input terminal of the fourth stage OR gate, the output terminal of the fourth stage OR gate being electrically connected with the buzzer circuit.

[0023] As an implementable manner, the buzzer circuit comprises:

[0024] a MOS transistor, the source being connected with the power supply circuit, the gate being electrically connected with the output terminal of the logic gate;

[0025] a buzzer, the positive terminal being connected with the drain of the MOS transistor, the negative terminal being grounded.

[0026] As an implementable manner, the power supply circuit comprises:

[0027] a power switch, being connected with the power supply, for turning on or blocking the power supply circuit;

[0028] a voltage stabilizing chip, the input terminal being electrically connected with the power switch.

[0029] As an implementable manner, the power supply circuit further comprises a voltage stabilizing inductor, one end being connected with the input terminal of the voltage stabilizing chip, the other end being electrically connected with the switch terminal of the voltage stabilizing chip.

[0030] As an implementable manner, the input terminal of the voltage stabilizing chip is connected with a first capacitor and then grounded.

[0031] The second aspect of the present application provides a performance detection device of a multiplexer, comprising a device body, a main path interface, a branch path interface and a circuit as described above, the device body being provided with the main path interface and the branch path interface, the main path interface being connected with the main path interface module in the circuit, the branch path interface being electrically connected with the branch path interface module.

[0032] The third aspect of the application provides a performance detection method of a multiplexer, applied to the device, and the method comprises:

[0033] receiving the multiplexer function detection result request sent by the controller;

[0034] turning on the power switch to turn on the power supply circuit;

[0035] determining whether all the light emitting diodes are in the lighting state and the buzzer emits the buzzing sound;

[0036] if yes, it is determined that the multiplexer function is normal;

[0037] returning the information that the multiplexer function is normal to the controller.

[0038] As an implementable mode, after the step of determining whether all the light emitting diodes are in the lighting state and the buzzer emits the buzzing sound, the method further comprises:

[0039] if no, determining the state of each light emitting diode, wherein the state comprises the lighting state and the non-lighting state;

[0040] obtaining the shunt interface number corresponding to the light emitting diode in the non-lighting state;

[0041] determining that the shunt interface function corresponding to the shunt interface number is abnormal;

[0042] returning the information that the shunt interface function corresponding to the shunt interface number is abnormal to the controller.

[0043] The embodiment of the application has the following beneficial effects: the application provides a performance detection circuit, device and method of a multiplexer, the circuit comprises: a test interface circuit, a logic gate circuit and a buzzer circuit connected in sequence, the input end of the test interface circuit is connected with the main road socket and the shunt interface of the multiplexer, the output end of the test interface circuit is connected with the input end of the logic gate circuit, and the output end of the logic gate circuit is connected with the buzzer circuit; the test interface circuit, the logic gate circuit and the buzzer circuit are also connected with a power supply circuit.

[0044] The performance detection circuit of the multiplexer provided by the application is based on a logic gate, cooperates with a buzzer circuit, connects the main road and the shunt aviation socket of the multiplexer to the corresponding main road interface and shunt interface of the performance detection device respectively, realizes automatic detection of the multiplexer, and the detection device is simple to operate and can realize efficient detection of batch products.

[0045] In order to solve the problems existing in the prior art test technology, and improve the test efficiency, the application provides a performance detection device for a multi-parameter intelligent water meter multiplexer.

[0046] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the application. The objects and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0047] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are specifically described below, and the accompanying drawings are described in detail as follows. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0049] Figure 1 The main road interface module circuit architecture diagram provided for the embodiment of the application is shown in the figure;

[0050] Figure 2 The shunt interface module circuit architecture diagram provided for the embodiment of the application is shown in the figure;

[0051] Figure 3 The logic gate circuit architecture diagram provided for the embodiment of the application is shown in the figure;

[0052] Figure 4 The buzzer circuit architecture diagram provided for the embodiment of the application is shown in the figure;

[0053] Figure 5 The power supply circuit architecture diagram provided for the embodiment of the application is shown in the figure;

[0054] Figure 6 The external structure schematic diagram of the performance detection device of the multiplexer provided for the embodiment of the application is shown in the figure;

[0055] Figure 7 The performance detection method flow chart of the multiplexer provided for the embodiment of the application is shown in the figure;

[0056] Figure 8Another multiplexer performance detection method flow chart provided by the embodiment of the application. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0058] In order to facilitate the understanding of the present embodiment, the technical terms designed by the present application will be briefly introduced first.

[0059] Logic gates are basic components on integrated circuits. Simple logic gates can be composed of transistors. The combination of these transistors can make the high and low levels representing two signals produce high or low level signals after passing through them. High and low levels can represent "true" and "false" in logic or 1 and 0 in binary, thereby realizing logical operations.

[0060] Logic gates are also called "basic units of digital logic circuits", and perform logical operations such as "or", "and", "not", "nor", "and not" and the like. Any complex logic circuit can be composed of these logic gates. They are widely used in computers, communications, controls and digital instruments.

[0061] After introducing the technical terms related to the present application, the application scenarios and design ideas of the embodiments of the present application will be briefly introduced next.

[0062] At present, when a multiplexer is detected, a plug needs to be connected to the aviation socket interface of its four branches and one main branch, and the other end of the plug has a wire leading out for use by a multimeter. Among the four branches, three are four channels, one is a three-channel, and the main branch is a nine-channel. The multimeter is used to test whether each channel between each branch and the main branch is conductive. If all channels are conductive, the test is passed, otherwise there is a fault. This test method is relatively cumbersome and is not conducive to batch detection.

[0063] Based on this, the embodiments of the present application provide a performance detection circuit, device and method for a multiplexer to reduce detection complexity and improve detection efficiency.

[0064] The embodiments of the present application provide a performance detection circuit for a multiplexer, which comprises a test interface circuit 1, a logic gate circuit 2 and a buzzer circuit 3 connected in sequence.

[0065] The input terminal of test interface circuit 1 is connected to the main port 11 and branch port 12 of the multiplexer, and the output terminal of test interface circuit 1 is connected to the input terminal of logic gate circuit 2. This test interface circuit is used to connect to the multiplexer under test and determine the continuity of each connection branch;

[0066] Logic gate circuit 2 has its input terminal connected to the output terminal of the test interface circuit 1; this logic gate circuit is used to receive the level state of the test interface circuit and output the corresponding level state according to the logic gate rules.

[0067] Buzzer circuit 3, with its input terminal connected to the output terminal of logic gate circuit 2, is used to receive the level state of the logic gate output and emit a buzzing sound when the level state is high to indicate that the multiplexer under test is performing well.

[0068] The test interface circuit 1, logic gate circuit 2, and buzzer circuit 3 are also connected to the power supply circuit 4.

[0069] The performance testing circuit for the multiplexer provided in this application embodiment connects the main and branch aviation sockets of the multiplexer to the corresponding main socket 11 and branch interface 12, respectively. By turning on the circuit, a logic gate-based testing circuit, combined with a buzzer circuit, reduces the complexity of the testing process and improves testing efficiency. At the same time, the test results can be intuitively understood through the buzzer or light flashing, further simplifying the operation and facilitating efficient testing of batch products.

[0070] As one feasible approach, the test interface circuit 1 includes: a main interface module 11 and branch interface modules 12. There is one main interface module 11 and four branch interface modules 12.

[0071] Combination Figure 1 The main interface module 11 shown includes first to ninth pins, which are respectively connected to and grounded; the main interface module 11 is connected to the main port of the multiplexer under test.

[0072] Combination Figure 2 The shown branch interface module 12 has four input terminals connected to the branch interface of the multiplexer under test, and the output terminal connected to the input terminal of a logic gate circuit 2. Among them, three branch interface modules 12 include first to fourth pins, one branch interface module 12 includes first to third pins, and each branch interface module 12 is connected to the input terminal of the logic gate circuit 2 through pins.

[0073] As one feasible approach, the splitter interface module 12 includes: a splitter interface 13 and a light-emitting diode 14.

[0074] The shunt interface 13 comprises a plurality of pins.

[0075] The positive electrode of the light emitting diode 14 is electrically connected with the power supply circuit, and the negative electrode is electrically connected with the pins of the shunt interface 13; wherein the number of the light emitting diodes 14 is adapted to the number of the pins of the shunt interface 13.

[0076] The test interface circuit 1 is divided into a main road interface module 11 and four shunt interface modules 12, which are composed of plug-in components and light emitting diodes, as shown in Figure 1 The nine pins of the main road interface module 11 are all connected to each other and connected to GND (i.e. ground), as shown in Figure 2 The three four-channel and one three-channel in the shunt interface module 12 correspond to the four shunts of the multiplexer, and each channel of the four shunt interface modules 12 is respectively connected to the negative electrode of a light emitting diode and the input end of a logic gate, and the positive electrode of the light emitting diode is connected to the circuit.

[0077] It is worth mentioning that before the test starts, the main road socket and the shunt socket of the multiplexer to be tested need to be connected with the main road interface module 11 and the shunt interface module 12 respectively and one by one.

[0078] When starting the test, if a certain light emitting diode is lit, it means that the channel of the shunt interface of the multiplexer to be tested and the corresponding channel of the main road interface module 11 are conductive, and the test is normal. At the same time, the level state of the input end of the logic gate circuit 2 is low.

[0079] On the contrary, if the light emitting diode is not lit, it means that the channel of the shunt interface of the multiplexer to be tested and the corresponding channel in the main road interface are not conductive, and the test is not passed, and at the same time, the level state of the input end of the logic gate is high.

[0080] As a kind of implementable way, the logic gate circuit 2 is composed of four or gate chips, and each channel of the shunt interface is connected with the input end of the or gate chip. The output end level state of the or gate is determined by the input end. Only when two input ends are low at the same time, the output end will be low, otherwise the output end will always be high.

[0081] Combined with Figure 3 As shown in the figure, the logic gate circuit 2 includes:

[0082] The first or gate chip includes two first or gates and one second or gate, the input end of one first or gate is electrically connected with the first pin and the second pin of the first shunt interface module; the input end of the other first or gate is electrically connected with the third pin and the fourth pin of the first shunt interface module; the output ends of the two first or gates are respectively electrically connected with the input ends of the second or gate.

[0083] The second or gate chip comprises two first-stage or gates, a second-stage or gate and a third-stage or gate; the input ends of the first-stage or gates are electrically connected with the first to second pins of the second shunt interface module, and the input ends of the other first-stage or gates are electrically connected with the third to fourth pins of the second shunt interface module; the output ends of the two first-stage or gates are respectively connected with the input ends of the second-stage or gate; the output end of the second-stage or gate and the output end of the second-stage or gate of the first or gate chip are respectively electrically connected with the input ends of the third-stage or gate;

[0084] The third or gate chip comprises two first-stage or gates, a second-stage or gate and a third-stage or gate; the input ends of the first-stage or gates are electrically connected with the first to second pins of the third shunt interface module, and the input ends of the other first-stage or gates are electrically connected with the third to fourth pins of the third shunt interface module; the output ends of the two first-stage or gates are respectively connected with the input ends of the second-stage or gate;

[0085] The fourth or gate chip comprises a first-stage or gate, a second-stage or gate, a third-stage or gate and a fourth-stage or gate; the input end of the first-stage or gate is electrically connected with the first to second pins of the fourth shunt interface module, and the input end of the other first-stage or gate is electrically connected with the third pin of the second shunt interface module and the output end of the first-stage or gate; the output end of the second-stage or gate and the output end of the second-stage or gate of the third or gate chip are respectively electrically connected with the input ends of the third-stage or gate; the output end of the third-stage or gate and the output end of the third-stage or gate of the second or gate chip are respectively electrically connected with the input ends of the fourth-stage or gate; and the output end of the fourth-stage or gate is electrically connected with the buzzer circuit.

[0086] Specifically, the four channels of the first shunt interface module are connected with the four input ends of the first or gate chip, and the four input ends correspond to the two first-stage or gates respectively; the output ends of the two first-stage or gates are connected with the input ends of the second-stage or gate.

[0087] The four channels of the second shunt interface module are connected with the four input ends of the second or gate chip, and the four input ends correspond to the two first-stage or gates respectively; the output ends of the two first-stage or gates are connected with the input ends of the second-stage or gate; the output end of the second-stage or gate and the output end of the second-stage or gate of the first or gate chip are connected with the input ends of the third-stage or gate of the second or gate chip.

[0088] The four channels of the third shunt interface module are connected with the four input ends of the third or gate chip, and the four input ends correspond to the two first-stage or gates respectively; the output ends of the two first-stage or gates are connected with the input ends of the second-stage or gate.

[0089] The three channels of the fourth shunt interface module are connected with the three input terminals of the fourth OR gate chip, the three input terminals of the fourth OR gate chip correspond to the input terminals of the first stage one OR gate and the other one OR gate respectively, the output terminal of the two-input OR gate is connected with the input terminal of the single-input OR gate, the output terminal of the single-input OR gate is connected with the input terminal of the second stage OR gate of the third OR gate chip, the output terminal of the second stage OR gate of the fourth OR gate chip is connected with the input terminal of the third stage OR gate of the second OR gate chip, and the output terminal of the third stage OR gate of the second OR gate chip is connected with the input terminal of the third stage OR gate of the fourth OR gate chip.

[0090] Finally, a high or low voltage signal is outputted from the output terminal of the third stage OR gate of the fourth OR gate chip, when all the channels of the shunt interface and the corresponding channels of the main interface are all turned on, the voltage signal is low, and when any one or more channels are not turned on, the voltage signal is high.

[0091] As an implementable mode, the buzzer circuit 3 comprises a MOS tube 31 and a buzzer 32.

[0092] As shown in Figure 4 , the source of the MOS tube 31 is connected with the power supply circuit, and the gate is electrically connected with the output terminal of the logic gate circuit 2.

[0093] The positive electrode of the buzzer 32 is connected with the drain of the MOS tube 31, and the negative electrode is grounded.

[0094] As an implementable mode, as shown in Figure 5 , the power supply circuit 4 comprises a power switch 41 and a voltage stabilizing chip 42.

[0095] As shown in Figure 5 , the power switch 41 is connected with the power supply, and is used for turning on or blocking the power supply circuit.

[0096] The power supply circuit 4 further comprises a voltage stabilizing inductive element, one end of which is connected with the input terminal of the voltage stabilizing chip 42, and the other end is electrically connected with the switch terminal of the voltage stabilizing chip 42.

[0097] The input terminal of the voltage stabilizing chip 42 is connected with the first capacitor 43 and then grounded.

[0098] As shown in Figure 6 , the second aspect of the embodiment of the application provides a performance detection device of a multiplexer, and as shown in Figure 6 , the detection device comprises a device body 5, a main interface 6, a shunt interface 7 and the above-mentioned circuit.

[0099] The device body 5 is provided with the main interface 6 and the shunt interface 7, the main interface 6 is connected with the main interface module 11 in the circuit, and the shunt interface 7 is electrically connected with the shunt interface module 12.

[0100] The device further comprises a plug-in (not shown in the figure) arranged at the main path interface 6 and the branch path interface 7, for conducting electrical connection between the main path interface 6 and the main path interface module 11, and for conducting electrical connection between the branch path interface 7 and the branch path interface module 12. This is common in electronic devices, and will not be described here.

[0101] Compared with the existing test technology, the performance detection device of the multiplexer is based on logic gates, and is equipped with a buzzer and an LED lamp (a light-emitting diode in the test circuit). The multiplexer of the multi-parameter intelligent water meter is automatically detected under the condition of being connected and powered on, which greatly reduces the complexity of the test. Through the state of the buzzer and the LED lamp, the detection result can be obtained more conveniently, and the test efficiency is improved.

[0102] Specifically, if all the light-emitting diodes on the test interface circuit of the detection device are in the lighting state, and the buzzer in the buzzer circuit has a buzzing sound, the measured multiplexer is normal in function and passes the test. If the buzzer in the buzzer circuit has no buzzing sound, there is one or more channels between the branch path interface and the main path socket of the measured multiplexer that are not conducted. By observing the light-emitting diodes on the test interface circuit of the performance detection device, the channel corresponding to the unlit light-emitting diode is the un-conducted channel.

[0103] The third aspect of the present application provides a performance detection method of a multiplexer, applied to the device described above. The device includes a memory for storing a computer program and a processor for executing the stored computer program. The device is connected to a controller to receive a detection result request and send a detection result to the controller. In combination Figure 7 The method includes:

[0104] S110, the processor receives the request for obtaining the function detection result of the multiplexer sent by the controller.

[0105] S120, the processor determines whether all the light-emitting diodes are in the lighting state and the buzzer emits a buzzing sound.

[0106] If yes, step S130 is performed.

[0107] S130, the processor determines that the multiplexer is normal in function.

[0108] S140, the processor returns information that the multiplexer is normal in function to the controller.

[0109] In the embodiment of the present application, in the case that all the light-emitting diodes are in the lighting state and the buzzer emits a buzzing sound, it is determined that the multiplexer is normal in function, and the detection result is returned to the controller. In this way, automatic detection can be realized, the manual labor is greatly reduced, and the detection efficiency and batch detection are improved.

[0110] As an implementable manner, the embodiment of the present application provides another multiplexer performance detection method, applied to the above device, which comprises a memory for storing computer programs and a processor for executing the stored computer programs. The device is connected with a controller to receive a detection result request and send a detection result to the controller. In combination with Figure 8 As shown in the figure, the method comprises, after the step of judging whether all the light-emitting diodes are in the lighting state and the buzzer emits the buzzing sound, further comprising:

[0111] The multiplexer performance detection method is applied to the above device, which comprises a memory for storing computer programs and a processor for executing the stored computer programs. The device is connected with a controller to receive a detection result request and send a detection result to the controller. In combination with Figure 8 As shown in the figure, the method comprises:

[0112] S210, the processor receives the acquisition multiplexer function detection result request sent by the controller.

[0113] S220, the processor judges whether all the light-emitting diodes are in the lighting state and the buzzer emits the buzzing sound.

[0114] If yes, step S230 is executed. If no, step S250 is executed.

[0115] S230, the processor determines that the multiplexer function is normal.

[0116] S240, the processor returns the information that the multiplexer function is normal to the controller.

[0117] S250, if no, the processor judges the state of each light-emitting diode, wherein the state comprises the lighting state and the non-lighting state.

[0118] S260, the processor acquires the shunt interface number corresponding to the light-emitting diode in the non-lighting state.

[0119] S270, the processor determines that the shunt interface function corresponding to the shunt interface number is abnormal.

[0120] S280, the processor returns the information that the shunt interface function corresponding to the shunt interface number is abnormal to the controller.

[0121] In the embodiment of the present application, only in the case that all the light emitting diodes are in the lighting state and the buzzer emits the buzzing sound, it is determined that the multiplexer function is normal, and the detection result is returned to the controller. In other cases, the shunt interface number corresponding to the light emitting diode in the unlighting state is acquired, and it is determined that the shunt interface function corresponding to the shunt interface number is abnormal, and the abnormal information is returned to the controller. In this way, automatic detection can be realized, and the labor amount is greatly reduced, and the detection efficiency and batch detection are improved.

[0122] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the foregoing method embodiment, and will not be described here.

[0123] In addition, in the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0124] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application or the part of the prior art that essentially contributes to the present application or the part of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and various program code storage media.

[0125] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance.

[0126] Finally, it should be noted that the above examples are merely specific embodiments of the present application, and are used to illustrate the technical solutions of the present application, but are not limiting thereof, and the protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that any person skilled in the art can still modify or easily think of changes to the technical solutions recorded in the foregoing examples, or make equivalent replacements to some of the technical features, within the technical range disclosed by the present application. These modifications, changes or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A performance detection circuit for a multiplexer, characterized by The utility model relates to a test interface circuit, input end and the main road socket and branch socket of the multiplexer under test connect, the test interface circuit is used for connecting with the multiplexer under test and judging each connection branch open and close, The logic gate circuit is connected with the output end of the test interface circuit, and the logic gate circuit is used for receiving the level state of the test interface circuit and outputting the corresponding level state according to the logic gate rule, The buzzer circuit is connected with the output end of the logic gate circuit, and the buzzer circuit is used for receiving the level state output by the logic gate and emitting the buzzing sound when the level state is the high level state to prompt that the multiplexer under test is good in performance, The power supply circuit is connected with the test interface circuit, the logic gate circuit and the buzzer circuit respectively, The test interface circuit includes a main road interface module, four branch interface modules and a power supply circuit. The main road interface module includes the first to ninth pins, and the first to ninth pins are connected with the ground respectively. The four branch interface modules are connected with the branch interface of the multiplexer respectively, and the output end of the branch interface module is connected with the input end of a logic gate circuit. The three branch interface modules include the first to fourth pins, and the one branch interface module includes the first to third pins. The branch interface module includes a branch interface and a light emitting diode.

2. The circuit of claim 1, wherein, The number of the light emitting diodes is matched with the number of the pins of the branch interface. The logic gate circuit includes a first or gate chip, a second or gate chip and a third or gate chip. The first or gate chip includes two first level or gates and one second level or gate. The second or gate chip includes two first level or gates, one second level or gate and one third level or gate.

3. The circuit of claim 1, wherein, The third or gate chip includes two first level or gates and one second level or gate. ​ ​ ​ A fourth OR gate chip includes a first stage OR gate, a second stage OR gate, a third stage OR gate and a fourth stage OR gate; one input terminal of the first stage OR gate is electrically connected with the first to second pins of the fourth branch interface module, and the other input terminal of the first stage OR gate is electrically connected with the third pin of the second branch interface module and the output terminal of the first stage OR gate; the output terminal of the second stage OR gate and the output terminal of the second stage OR gate of the third OR gate chip are respectively connected with the input terminals of the third stage OR gate, the output terminal of the third stage OR gate and the output terminal of the third stage OR gate of the second OR gate chip are respectively electrically connected with the input terminals of the fourth stage OR gate, and the output terminal of the fourth stage OR gate is electrically connected with the buzzer circuit.

4. The circuit of claim 1, wherein, The buzzer circuit includes: A MOS tube, the source thereof is connected with the power supply circuit, and the gate thereof is electrically connected with the output terminal of the logic gate circuit; A buzzer, the positive electrode thereof is connected with the drain of the MOS tube, and the negative electrode thereof is grounded.

5. The circuit of claim 1, wherein, The power supply circuit includes: A power switch, connected with the power supply, for turning on or blocking the power supply circuit; A voltage stabilizing chip, the input terminal thereof is electrically connected with the power switch.

6. A performance monitoring apparatus for a multiplexer, characterized by The device includes a device body, a main path interface, a branch path interface and the circuit as claimed in any one of claims 1-5, the main path interface and the branch path interface are arranged on the device body, and the main path interface is connected with the main path interface module in the circuit.

7. The apparatus of claim 6, wherein, The device further includes a plug-in part arranged between the main path interface and the branch path interface, for conducting electrical connection between the main path interface and the main path interface module, and for conducting electrical connection between the branch path interface and the branch path interface module.

8. A method of performance testing of a multiplexer, characterized by The method is applied to the device as claimed in claim 6, and the method includes: Receiving a request for acquiring a multiplexer function detection result sent by a controller; Judging whether all light emitting diodes are in a lighting state and a buzzer emits a buzzing sound; If yes, determining that the multiplexer function is normal; Returning information that the multiplexer function is normal to the controller.

9. The performance detection method of claim 8, wherein, After the step of judging whether all light emitting diodes are in a lighting state and a buzzer emits a buzzing sound, the method further includes: If no, judging a state of each light emitting diode, wherein the state includes a lighting state and a non-lighting state; Acquiring a branch path interface number corresponding to a light emitting diode in a non-lighting state; Determining that a branch path interface corresponding to the branch path interface number is abnormal; Returning information that the branch path interface corresponding to the branch path interface number is abnormal to the controller.

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