Fpga layout method and apparatus, electronic device, and storage medium

Abstract

The application provides an FPGA layout method, an FPGA layout device, an electronic device and a computer readable storage medium. The FPGA comprises a plurality of configurable logic modules, the configurable logic module comprises a plurality of logic regions, the logic region has M to-be-laid-out units needing external signal driving and N input lines for external signal input, the method comprises: when M is less than or equal to N, arranging the M to-be-laid-out units in the logic region, and making the external signal drive the M to-be-laid-out units through the M input lines respectively; when M is greater than N, arranging N to-be-laid-out units in the logic region, arranging M-N to-be-laid-out units outside the logic region, and making the external signal drive the N to-be-laid-out units through the N input lines respectively. According to the application, the external signal input line resource in the logic region can be fully utilized, the FPGA area utilization rate is improved, and the overall delay is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the FPGA (Field Programmable Gate Array) design technical field, and particularly relates to an FPGA layout method, an FPGA layout device, an electronic device and a computer readable storage medium. BACKGROUND

[0002] The technology of arranging units or elements in FPGA is known. In the existing layout method for FPGA logic area, there is often a situation of wiring resource waste. When the wiring resource is wasted, the distance between FPGA elements increases, which causes the increase of overall delay, and is not conducive to the performance of FPGA. Therefore, the FPGA layout method capable of improving the FPGA area utilization and reducing the overall delay is urgently needed in the field. SUMMARY

[0003] Therefore, the present application is committed to providing an FPGA layout method, an FPGA layout device, an electronic device and a computer readable storage medium, which can make full use of the wiring resources in FPGA, improve the FPGA area utilization and reduce the overall delay.

[0004] In one aspect, the present application provides an FPGA layout method, and the FPGA includes a plurality of configurable logic modules, the configurable logic module includes a plurality of logic areas, the logic area has M units to be arranged and N input lines for external signal input, the method comprises the following steps: when M is less than or equal to N, arranging M units to be arranged in the logic area, and making the external signal drive M units to be arranged through M input lines respectively; when M is greater than N, arranging N units to be arranged in the logic area, arranging M-N units to be arranged outside the logic area, and making the external signal drive N units to be arranged through N input lines respectively.

[0005] According to a special embodiment of the present application, the unit to be arranged includes a register and / or an adder.

[0006] According to a special embodiment of the present application, the input line includes a wire and / or a lookup table.

[0007] According to a special embodiment of the present application, the unit to be arranged includes a first register and an adder, the input line includes a wire and a lookup table, and the step of arranging M units to be arranged in the logic area comprises the following steps: arranging the first register and the adder in the logic area.

[0008] According to a particular embodiment of the present application, the external signal is respectively driven to the M to-be-laid-out units through the M input lines, comprising: driving the external signal to pass through the one of the wire and the look-up table to drive the one of the first register and the adder, and driving the external signal to pass through the other of the wire and the look-up table to drive the other of the first register and the adder.

[0009] According to a particular embodiment of the present application, the to-be-laid-out unit comprises the first register, the second register and the adder, the input line comprises the wire and the look-up table, and the N to-be-laid-out units are arranged in the logic area and the M-N to-be-laid-out units are arranged outside the logic area, comprising: arranging the first register and the adder in the logic area, and arranging the second register outside the logic area.

[0010] According to a particular embodiment of the present application, the external signal is respectively driven to the N to-be-laid-out units through the N input lines, comprising: driving the external signal to pass through the one of the wire and the look-up table to drive the one of the first register and the adder, and driving the external signal to pass through the other of the wire and the look-up table to drive the other of the first register and the adder.

[0011] In another aspect, the present application provides an FPGA layout device, the FPGA comprising a plurality of configurable logic modules, the configurable logic module comprising a plurality of logic areas, the logic area having M to-be-laid-out units needing external signal driving and N input lines for external signal input, the device comprising: a first arrangement module, configured to arrange the M to-be-laid-out units in the logic area and drive the external signal to the M to-be-laid-out units through the M input lines when M is less than or equal to N; and a second arrangement module, configured to arrange the N to-be-laid-out units in the logic area, arrange the M-N to-be-laid-out units outside the logic area, and drive the external signal to the N to-be-laid-out units through the N input lines when M is greater than N.

[0012] In another aspect, the present application provides an electronic device, comprising: a processor; a memory; and an application program stored in the memory and configured to be executed by the processor, the application program comprising instructions for executing the FPGA layout method.

[0013] In another aspect, the present application provides a computer readable storage medium storing a computer program for executing the FPGA layout method.

[0014] According to the FPGA layout method, the FPGA layout device, the electronic device and the computer readable storage medium of the present application, as many elements as possible needing external signal driving are placed in the logic area, so that the line resource for external signal input in the logic area is fully utilized, such layout operation or setting can make the FPGA element layout more compact, which is beneficial to improve the utilization rate of FPGA area and avoid the waste of line resource, thereby reducing the overall delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The specific embodiments of the present application are described in detail below with reference to the accompanying drawings, wherein:

[0016] Figure 1 A schematic diagram illustrating a flow chart of an FPGA layout method according to an embodiment of the present application is shown;

[0017] Figure 2 Show the basis Figure 1 A schematic structural diagram of an application object of the FPGA layout method of an embodiment;

[0018] Figure 3 A schematic structural diagram of an FPGA layout device according to an embodiment of the present application is shown;

[0019] Figure 4 A schematic structural diagram of an electronic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] In order to make those skilled in the art understand the concept and idea of ​​the present application more clearly, the present application is described in detail below in conjunction with specific embodiments. It should be understood that the embodiments provided herein are only a part of all possible embodiments of the present application. After reading the specification of the present application, those skilled in the art are capable of making improvements, modifications, or replacements to part or all of the following embodiments, and these improvements, modifications, or replacements are also included in the scope of protection claimed in the present application.

[0021] In this document, the terms "one", "an" and other similar words are not intended to indicate that there is only one of the things described, but rather that the relevant description is only for one of the things described, and the things described may have one or more. In this document, the terms "include", "comprise" and other similar words are intended to indicate logical relationships, and cannot be regarded as indicating relationships in spatial structure. For example, "A includes B" is intended to indicate that B logically belongs to A, but does not mean that B is spatially located inside A. In addition, the meanings of the terms "include", "include" and other similar words should be regarded as open, not closed. For example, "A includes B" is intended to indicate that B belongs to A, but B does not necessarily constitute the whole of A. A may also include other elements such as C, D, and E.

[0022] In this document, the terms "first", "second", and other similar terms are used to distinguish one element from another, and do not imply a particular order, number, or importance of the elements. In this document, the terms "example", "exemplary", "one example", and "an example" are used to indicate that something is an example, and not necessarily the only example, of something. A person skilled in the art will understand that any of the examples described herein can be replaced, combined, or otherwise combined with the descriptions of another one or more examples, and the resulting new examples are within the scope of protection of the present application.

[0023] In the embodiments of the present application, the FPGA layout can refer to a step in the FPGA design. The FPGA design usually includes front-end design and back-end design; the front-end design can include RTL (Register Transfer Level) design, verification, static timing analysis, coverage, and logic synthesis; the back-end design can include logic synthesis, formal verification, physical implementation (including floor plan, placement, and routing), clock tree synthesis, parasitic parameter extraction, and layout physical verification. For example, the FPGA design can include main steps such as function definition, device selection, design input, functional simulation, synthesis optimization, post-synthesis simulation, layout, routing, post-simulation, board-level simulation, and FPGA programming and debugging.

[0024] In the embodiments of the present application, the FPGA layout can refer to placing standard cells, I / O pads, and macro cells to implement the entire circuit logic. For example, the FPGA layout can refer to placing the macro cell modules of the FPGA, and generally determining the placement positions of various functional circuits such as IP modules, RAMs, I / O pins, and the like, and the layout can directly affect the final area of the FPGA. The input of the layout can be the netlist information after packaging, the constraint information of the FPGA, and the user-defined constraint information, including the physical constraints written in the user constraint file and the delay constraints written in the design constraint file, and the output of the layout can be the netlist after the layout, for the automatic router to route. The FPGA layout can usually include input / output layout, global clock layout, initial layout, overall layout, legalization layout, and detailed layout. For example, the process of the layout generally includes global layout, legalization layout, and detailed layout.

[0025] Figure 1 A flowchart of an FPGA layout method according to an embodiment of the present application is shown.

[0026] In the embodiment, the FPGA includes a plurality of configurable logic modules, and each configurable logic module includes a plurality of logic parcels, and each logic parcel has M to-be-laid-out units requiring external signal driving and N input lines for external signal input.

[0027] The configurable logic block (CLB) can refer to a module composed of a lookup table, a data selector, a carry chain, and a register, wherein the lookup table and the multiplexer complete the combinational logic function, and the register (which can be configured as a flip-flop or a latch) completes the timing logic function.

[0028] The logic parcel (LP) can refer to a constituent unit of the configurable logic module. One configurable logic module can include a plurality of logic parcels, for example, 4.

[0029] The external signal can refer to a signal from outside the configurable logic module. Some units or elements in the logic parcel require driving of the external signal to work normally, and therefore, the layout of the line resource in which the external signal can be input is required.

[0030] As an example, the to-be-laid-out unit includes a register and / or an adder.

[0031] The register (REG) can refer to a commonly used timing logic circuit, but such a timing logic circuit only includes a storage circuit. The storage circuit of the register is composed of a latch or a flip-flop. Since one latch or flip-flop can store 1-bit binary number, N-bit register can be composed of N latches or flip-flops.

[0032] The adder (ADD) can refer to a device for generating the sum of numbers. The device with the summand and the addend as input and the sum and the carry as output is a half adder. If the summand, the addend, and the low-bit carry are input, and the sum and the carry are output, it is a full adder. The adder is commonly used as the arithmetic logic unit of the computer to perform logical operations, shifting, and instruction calling.

[0033] As an example, the input line includes a bypass and / or a lookup table.

[0034] The bypass can refer to a line that forms a bypass in the logic parcel.

[0035] The lookup table (LUT) can refer to a data structure in which an array of runtime calculations is replaced by a simple query operation.

[0036] When the lookup table is used as the input line, the structure of the lookup table needs to be modified in a certain way. For details of the modification method, refer to the Chinese invention patent publication CN114861582A.

[0037] According to the embodiment, the FPGA layout method comprises steps S110 and S120, which are described in detail below.

[0038] S110, when M is less than or equal to N, arranging M units to be laid out in the logic region, and driving the M units to be laid out by the M input lines respectively.

[0039] When the number of units to be laid out is less than the number of input lines, it means that the resource of input lines is sufficient at this time, so all units to be laid out can be arranged in the current logic region.

[0040] As an example, when the units to be laid out include a first register and an adder, and the input lines include a wire and a lookup table, the first register and the adder can be arranged in the logic region, and one of the first register and the adder is driven by the wire and the other of the first register and the adder is driven by the lookup table. For example, the first register is driven by the wire and the adder is driven by the lookup table, or the adder is driven by the wire and the first register is driven by the lookup table.

[0041] S120, when M is greater than N, arranging N units to be laid out in the logic region, and arranging M-N units to be laid out outside the logic region, and driving the N units to be laid out by the N input lines respectively.

[0042] When the number of units to be laid out exceeds the number of input lines, it means that the external input line resource of the current logic region is insufficient, and the number of units to be laid out arranged in the logic region needs to be reduced so that the input line resource can be kept sufficient. The units to be laid out that fail to be arranged in the logic region can be arranged in other positions outside the logic region.

[0043] As an example, when the units to be laid out include a first register, a second register and an adder, and the input lines include a wire and a lookup table, the first register and the adder can be arranged in the logic region, and the second register is arranged outside the logic region, and one of the first register and the adder is driven by the wire and the other of the first register and the adder is driven by the lookup table. For example, the first register is driven by the wire and the adder is driven by the lookup table, or the adder is driven by the wire and the first register is driven by the lookup table.

[0044] Figure 2 A structure diagram of an application object of the FPGA layout method according to the embodiment is shown. Figure 1 The FPGA layout method according to the embodiment is shown. Figure 2The shown part is half of a logic region. In other words, one logic region includes two identical shown parts.

[0045] As Figure 2 shown, the embodiment mainly optimizes the layout constraints of LUT, ADD and REG in the same LP. In the current CLB structure, for each LP, only two bypass routing resources (only one is shown in the figure) are available,

[0046] When both REGs occupying the same bypass resource are externally driven, the REG can be legally laid out at the current position when the LUT has four or fewer inputs. For the specific implementation, refer to Chinese invention patent publication CN114861582A.

[0047] Figure 2 Two REGs and one ADD are shown in the middle. When both the two REGs and the ADD occupying the same bypass resource are externally driven, since there is only one bypass signal and the multi-output LUT can only provide one input signal, it cannot meet the three inputs from the outside, so this layout result is illegal, and individual cells need to be laid out separately.

[0048] The embodiment is to further utilize resources and add processing for ADD.

[0049] As shown in the figure, when the ADD and REG1 are both externally driven, if there is no cell laid out at the position of REG9, at this time, a line can be selected to be connected by configuring a multiplexer (MUX1, MUX2, MUX3 and / or MUX4), so that the two external input signals can be input through the bypass and another port of the LUT, and the current layout in the LP can be considered legal. If a cell is arranged at the position of REG9, since the output port in the current LP is limited and can only output two signals, while there are three output signals inside the LP at this time, so the layout at this time is illegal, and a new position needs to be found for the REG or the ADD.

[0050] When the ADD and REG9 are both externally driven, since the output port of the ADD and the output of the REG9 share the same multiplexer, when both have external outputs, an output conflict will occur, so when there is no cell laid out at the position of REG1, the output of the ADD can be connected to REG1 by configuring MUX1, MUX2, MUX3 and / or MUX4, and then output from another output selector through REG1. When a cell is arranged at the position of REG1, the layout of the LP at this time is illegal, and a new position needs to be found for the REG or the ADD.

[0051] Figure 3 Fig. 1 shows a schematic diagram of an FPGA layout device according to an embodiment of the application.

[0052] According to the embodiment, the FPGA comprises a plurality of configurable logic modules, each configurable logic module comprising a plurality of logic regions, each logic region having M to-be-laid-out units requiring external signal driving and N input lines for external signal input, and the FPGA layout device 300 comprises:

[0053] a first arrangement module 310 configured to, when M is less than or equal to N, arrange the M to-be-laid-out units in the logic region and drive the M to-be-laid-out units by the M input lines respectively with external signals;

[0054] a second arrangement module 320 configured to, when M is greater than N, arrange N to-be-laid-out units in the logic region, arrange M-N to-be-laid-out units outside the logic region, and drive the N to-be-laid-out units by the N input lines respectively with external signals.

[0055] In an embodiment, the to-be-laid-out units comprise registers and / or adders.

[0056] In an embodiment, the input lines comprise wires and / or lookup tables.

[0057] In an embodiment, the to-be-laid-out units comprise a first register and an adder, the input lines comprise wires and lookup tables, and the first arrangement module 310 is further configured to:

[0058] arrange the first register and the adder in the logic region.

[0059] In an embodiment, the first arrangement module 310 is further configured to:

[0060] drive one of the first register and the adder by the wires with external signals, and drive the other one of the first register and the adder by the lookup tables with external signals.

[0061] In an embodiment, the to-be-laid-out units comprise a first register, a second register and an adder, the input lines comprise wires and lookup tables, and the second arrangement module 320 is further configured to:

[0062] arrange the first register and the adder in the logic region, and arrange the second register outside the logic region.

[0063] In an embodiment, the second arrangement module 320 is further configured to:

[0064] drive one of the first register and the adder by the wires with external signals, and drive the other one of the first register and the adder by the lookup tables with external signals.

[0065] The following is described in conjunction withFigure 4 An electronic device according to an embodiment of the present application is described.

[0066] As shown in FIG. 4, the electronic device 400 includes one or more processors 410 and a memory 420. Figure 4

[0067] The processor 410 can be a central processing unit (CPU) or other form of processing unit having data processing and / or instruction executing capabilities, and can control other components in the electronic device 400 to perform desired functions.

[0068] The memory 420 can include one or more computer program products that can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory, for example, can include random access memory (RAM), cache memory, and / or the like. The non-volatile memory, for example, can include read-only memory (ROM), hard disk, flash memory, and / or the like. One or more computer program instructions can be stored on the computer-readable storage media, and the processor 410 can execute the program instructions to implement the FPGA layout method of various embodiments of the present application described above and / or other desired functions.

[0069] In one example, the electronic device 400 can further include an input device 430 and an output device 440, which are interconnected through a bus system and / or other form of connection mechanism (not shown).

[0070] For example, the input device 430 can be a microphone or microphone array for capturing voice input signals, a communication network connector for receiving captured input signals from the cloud or other devices, and can further include, for example, a keyboard, a mouse, and / or the like.

[0071] The output device 440 can output various information, including determined distance information, direction information, and / or the like, to the outside. The output device 440 can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and / or the like.

[0072] Of course, in order to simplify, Figure 4 In FIG. 4, only some of the components related to the present application among the electronic device 400 are shown, and components such as buses, input / output interfaces, and / or the like are omitted. In addition to this, the electronic device 400 can further include any other appropriate components according to a specific application.

[0073] ​Embodiments of the present application can also be computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, cause the processor to carry out steps of the FPGA layout method according to various embodiments of the present application described above.

[0074] The computer readable storage medium can be any combination of one or more computer readable medium. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0075] The concepts, principles and ideas of the present application are described in detail above in combination with the specific embodiments (including examples and instances). Those skilled in the art should understand that the embodiments of the present application are not only the above-mentioned forms, and those skilled in the art can make any possible improvements, replacements and equivalents to the steps, methods, devices and components in the above-mentioned embodiments after reading the present application. These improvements, replacements and equivalents should be considered to fall within the scope of the present application. The scope of protection of the present application is only subject to the claims.

Claims

1. An FPGA layout method, the FPGA comprising a plurality of configurable logic modules, the configurable logic module comprising a plurality of logic regions, the logic region having M to-be-laid-out units requiring external signal driving and N input lines for external signal input, the method comprising: arranging M to-be-laid-out units in the logic region and driving the M to-be-laid-out units by M input lines respectively when M is less than or equal to N; arranging N to-be-laid-out units in the logic region and arranging M-N to-be-laid-out units outside the logic region and driving the N to-be-laid-out units by N input lines respectively when M is greater than N.

2. The FPGA placement method of claim 1, wherein, The to-be-laid-out unit comprises a register and / or an adder.

3. The FPGA placement method of claim 1, wherein, The input line comprises a wire and / or a lookup table.

4. The FPGA placement method of claim 1, wherein, The to-be-laid-out unit comprises a first register and an adder, and the input line comprises a wire and a lookup table, and the arranging M to-be-laid-out units in the logic region comprises: arranging the first register and the adder in the logic region.

5. The FPGA placement method of claim 4, wherein, The driving the M to-be-laid-out units by M input lines respectively comprises: driving one of the first register and the adder by the wire and driving the other of the first register and the adder by the lookup table.

6. The FPGA placement method of claim 1, wherein, The to-be-laid-out unit comprises a first register, a second register and an adder, and the input line comprises a wire and a lookup table, and the arranging N to-be-laid-out units in the logic region and arranging M-N to-be-laid-out units outside the logic region comprises: arranging the first register and the adder in the logic region and arranging the second register outside the logic region.

7. The FPGA placement method of claim 6, wherein, The driving the N to-be-laid-out units by N input lines respectively comprises: driving one of the first register and the adder by the wire and driving the other of the first register and the adder by the lookup table.

8. An FPGA layout apparatus, the FPGA comprising a plurality of configurable logic modules, the configurable logic module comprising a plurality of logic regions, the logic region having M to-be-laid-out units requiring external signal driving and N input lines for external signal input, the apparatus comprising: a first arrangement module, configured to arrange M to-be-laid-out units in the logic region and drive the M to-be-laid-out units by M input lines respectively when M is less than or equal to N; a second arrangement module, configured to arrange N to-be-laid-out units in the logic region and arrange M-N to-be-laid-out units outside the logic region and drive the N to-be-laid-out units by N input lines respectively when M is greater than N.

9. An electronic device, comprising: a processor; a memory; An application program stored in the memory and configured to be executed by the processor, the application program including instructions for performing the FPGA placement method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program for performing the FPGA placement method according to any one of claims 1 to 7.

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