Semiconductor device and method of manufacturing the same, temperature detection circuit

Abstract

A semiconductor device and a manufacturing method thereof, and a temperature detection circuit, wherein the semiconductor device comprises: a semiconductor substrate, a front surface of the semiconductor substrate having a first region and a second region adjacent to each other, a first isolation belt being formed around the first region and being adapted to be connected to a first voltage; a MOS device being located in the first region; a temperature detection diode being located in the second region, one of a cathode region and an anode region of the temperature detection diode being adapted to be connected to a second voltage, and the other being adapted to be connected to a current source, a difference between the second voltage and the first voltage being less than a preset tolerance range. Through the disclosed scheme, the temperature detection diode can be arranged closer to the MOS device, and the temperature detection accuracy and response speed are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a manufacturing method thereof, and a temperature detection circuit. BACKGROUND

[0002] In some power management chips including power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and control circuit, since the power MOSFET generates large heat, it is usually necessary to monitor the temperature of the power MOSFET in real time.

[0003] At present, the temperature detection of semiconductor chips is usually realized by using the characteristic that the voltage drop of PN junction changes with temperature. The PN junction can be a diode, a PN junction between the base and the emitter of a transistor, or a PN junction structure in other devices, which are collectively referred to as diodes here. Specifically, the volt-ampere characteristic of the diode is sensitive to temperature, so the diode can be used as a temperature sensor. As can be seen from the diode characteristic curve, for every 1℃ rise in temperature, the forward voltage of the diode drops about 2.2mV (millivolt); and for every 1℃ drop in temperature, the forward voltage rises about 2.2mV. Therefore, the temperature change can be calculated by measuring the change in the forward voltage of the diode, so that the overheat protection circuit can be well controlled.

[0004] Generally, the closer the temperature detection diode is to the hot spot, the higher the accuracy and the faster the response of the temperature detection diode in detecting the temperature of the hot spot. For example, when the power MOSFET experiences a large instantaneous power, a temperature difference of more than 30℃ can be generated, and the distance between the temperature detection point and the power MOSFET is about 20um (microns).

[0005] As the power of the power MOSFET in the power management chip becomes larger and larger, the heat problem of the power MOSFET becomes more and more serious, and it is necessary to arrange the temperature detection diode at the closest position to the power MOSFET to timely and accurately detect the heat phenomenon of the power MOSFET. However, due to various factors such as structure, the distance between the power MOSFET and the temperature detection diode in the existing power management chip cannot meet the requirement of the closest arrangement, which seriously affects the temperature detection accuracy and response speed. SUMMARY

[0006] The technical problem solved by the present application is how to arrange the temperature detection diode closer to the MOS device to improve the temperature detection accuracy and response speed.

[0007] To solve the above technical problems, the embodiment of the present application provides a semiconductor device, which comprises: a semiconductor substrate, the front surface of the semiconductor substrate has a first region and a second region adjacent to each other, a first isolation belt is formed around the first region, the first isolation belt is adapted to be connected to a first voltage; a MOS device is located in the first region; a temperature detection diode is located in the second region, one of the cathode region and the anode region of the temperature detection diode is adapted to be connected to a second voltage, and the other is adapted to be connected to a current source, the difference between the second voltage and the first voltage is less than a preset tolerance range.

[0008] Optionally, the preset tolerance range is determined according to the breakdown voltage between the temperature detection diode and the first isolation belt.

[0009] Optionally, the region of the cathode region and the anode region of the temperature detection diode which is opposite to the doping type of the first isolation belt is adapted to be connected to the second voltage.

[0010] Optionally, the second region is formed with a first well region, the temperature detection diode is located in the first well region, and the first well region and the first isolation belt have a non-zero gap.

[0011] Optionally, the first isolation belt comprises: a first type well which is arranged around the first region and is located at least between the first region and the second region; and a first buried layer which is located below the first region and is connected to the first type well.

[0012] Optionally, the MOS device comprises a drain region and a source region, the drain region is closer to the first type well than the source region, and the first type well is connected to the drain region or has a non-zero gap.

[0013] Optionally, the semiconductor device further comprises: a second buried layer which is located below the second region, and the second buried layer is connected to the first buried layer.

[0014] Optionally, the first buried layer and the second buried layer are located in the same layer.

[0015] Optionally, a second isolation belt is formed around the second region, and the second isolation belt is jointly formed by the first type well located between the first region and the second region and the second buried layer.

[0016] Optionally, the semiconductor substrate located between the temperature detection diode and the first type well is adapted to be connected to a fourth voltage, and the fourth voltage is less than or equal to the second voltage.

[0017] Optionally, the semiconductor device further comprises: an isolation trench which is arranged around the first region and is located on the side of the first region away from the second region.

[0018] Optionally, the number of the temperature detection diodes is multiple, and the multiple temperature detection diodes are connected in series and dispersedly arranged in the second region.

[0019] To solve the above technical problems, the embodiment of the present application further provides a manufacturing method of a semiconductor device, comprising: providing a semiconductor substrate, the front surface of the semiconductor substrate having a first region and a second region adjacent to each other; forming a first isolation belt around the first region, the first isolation belt being adapted to be connected to a first voltage; forming a MOS device in the first region; forming a temperature detection diode in the second region, one of the cathode region and the anode region of the temperature detection diode being adapted to be connected to a second voltage, and the other being adapted to be connected to a current source, the difference between the second voltage and the first voltage being less than a preset tolerance range.

[0020] Optionally, the preset tolerance range is determined according to the breakdown voltage between the temperature detection diode and the first isolation belt.

[0021] Optionally, the region of the cathode region and the anode region of the temperature detection diode which is opposite to the doping type of the first isolation belt is adapted to be connected to the second voltage.

[0022] Optionally, the forming of the temperature detection diode in the second region comprises: doping to form a first well region in the second region, the first well region and the first isolation belt having a non-zero gap; forming the temperature detection diode in the second well region.

[0023] Optionally, the forming of the first isolation belt around the first region comprises: forming a first buried layer under the first region; forming a first type well around the first region and connecting the first buried layer, the first type well being located at least between the first region and the second region.

[0024] Optionally, the forming of the MOS device in the first region comprises: forming a source region and a drain region in the first region respectively, wherein the drain region is closer to the first type well than the source region, and the first type well is connected to the drain region or has a non-zero gap.

[0025] Optionally, the manufacturing method further comprises: forming a second buried layer under the second region and connecting the first buried layer at the same time / as before / as after the forming of the first buried layer.

[0026] Optionally, the first buried layer and the second buried layer are located in the same layer.

[0027] Optionally, before the forming of the temperature detection diode in the second region, the manufacturing method further comprises: based on the first type well located between the first region and the second region and the second buried layer, a second isolation belt is formed.

[0028] Optionally, the semiconductor substrate between the temperature detection diode and the first type well is adapted to connect a fourth voltage, the fourth voltage is less than or equal to the second voltage.

[0029] Optionally, the manufacturing method further comprises: forming an isolation groove around the first region on a side of the first region away from the second region.

[0030] Optionally, the forming the temperature detection diode in the second region comprises: dispersively forming a plurality of temperature detection diodes in the second region; and connecting the plurality of temperature detection diodes in series.

[0031] To solve the above technical problems, the embodiment of the present application further provides a temperature detection circuit, comprising: the semiconductor device; a first voltage output end electrically connected with the first isolation belt to provide a first voltage; a second voltage output end electrically connected with one of the cathode region and the anode region of the temperature detection diode to provide a second voltage, the difference between the second voltage and the first voltage is less than a preset tolerance range; a current source electrically connected with the other of the cathode region and the anode region of the temperature detection diode; and a detection module coupled with the cathode region and the anode region of the temperature detection diode respectively, the detection module is used for detecting the voltage difference between the cathode region and the anode region, and determining the temperature of the MOS device according to the voltage difference.

[0032] Optionally, the second voltage output end is electrically connected with the anode region, and the current source is electrically connected with the cathode region.

[0033] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0034] The embodiment of the present application provides a semiconductor device, comprising: a semiconductor substrate, the front surface of the semiconductor substrate has adjacent first and second regions, a first isolation belt is formed around the first region, and the first isolation belt is adapted to connect a first voltage; a MOS device located in the first region; and a temperature detection diode located in the second region, one of the cathode region and the anode region of the temperature detection diode is adapted to connect a second voltage, and the other is adapted to connect a current source, the difference between the second voltage and the first voltage is less than a preset tolerance range.

[0035] Compared with the prior art, the temperature detection diode and the region (e.g., the first isolation belt) where the MOS device is formed have a larger potential difference, which causes the temperature detection diode to be arranged far away from the MOS device to ensure a sufficient insulation distance. The present disclosure reduces or even eliminates the potential difference between the temperature detection diode and the first isolation belt, so that the MOS device and the temperature detection diode can work normally without maintaining a large insulation distance. Thus, the distance between the temperature detection diode and the MOS device is greatly reduced, so that the temperature detection diode can be arranged closer to the MOS device, which is beneficial to improve the temperature detection accuracy and response speed. Taking the first voltage as a high voltage as an example, compared with the prior art in which the temperature detection diode is usually grounded, the temperature detection diode in the present disclosure is connected to a high level, so that the potential difference is reduced or even eliminated.

[0036] Further, the embodiment of the present disclosure also provides a manufacturing method of a semiconductor device, which comprises: providing a semiconductor substrate, the front surface of the semiconductor substrate having a first region and a second region adjacent to each other; forming a first isolation belt around the first region, the first isolation belt being adapted to be connected to a first voltage; forming a MOS device in the first region; forming a temperature detection diode in the second region, one of the cathode region and the anode region of the temperature detection diode being adapted to be connected to a second voltage, and the other being adapted to be connected to a current source, wherein the difference between the second voltage and the first voltage is less than a preset tolerance range.

[0037] By improving the potential coupled to the first isolation belt and the temperature detection diode respectively, the potential difference between the two is reduced or even eliminated, so that the temperature detection diode can be arranged closest to the MOS device. Thus, the semiconductor device manufactured by using the present disclosure can detect the heating phenomenon of the MOS device with higher accuracy and faster response speed, which is beneficial to improve the reliability of the semiconductor device.

[0038] Further, the embodiment of the present disclosure also provides a temperature detection circuit, which comprises: the above semiconductor device; a first voltage output end, which is electrically connected to the first isolation belt to provide a first voltage; a second voltage output end, which is electrically connected to one of the cathode region and the anode region of the temperature detection diode to provide a second voltage, wherein the difference between the second voltage and the first voltage is less than a preset tolerance range; a current source, which is electrically connected to the other of the cathode region and the anode region of the temperature detection diode; and a detection module, which is coupled to the cathode region and the anode region of the temperature detection diode respectively, and is used to detect the voltage difference between the cathode region and the anode region, and determine the temperature of the MOS device according to the voltage difference.

[0039] Therefore, the temperature detection circuit described in this disclosure reduces or even eliminates the potential difference between the temperature detection diode and the first isolation band by applying appropriate potentials to the first isolation band and the temperature detection diode, allowing the temperature detection diode in the semiconductor device to be placed as close as possible to the MOS device. As a result, the temperature detection circuit can detect the heating phenomenon of the MOS device more accurately and quickly. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the first semiconductor device in the prior art;

[0041] Figure 2 yes Figure 1 A cross-sectional view along the AA direction;

[0042] Figure 3 This is a cross-sectional view of a second type of semiconductor device in the prior art;

[0043] Figure 4 This is a cross-sectional view of the third type of semiconductor device in the prior art;

[0044] Figure 5 This is a cross-sectional view of the fourth type of semiconductor device in the prior art;

[0045] Figure 6 This is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention;

[0046] Figure 7 yes Figure 6 Top view of the semiconductor device shown;

[0047] Figure 8 This is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention;

[0048] Figure 9 This is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention;

[0049] Figure 10 This is a cross-sectional view of a semiconductor device according to the fourth embodiment of the present invention;

[0050] Figure 11 This is a cross-sectional view of a semiconductor device according to the fifth embodiment of the present invention;

[0051] Figure 12 This is a flowchart of a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention;

[0052] Figure 13 This is an equivalent schematic diagram of a temperature detection circuit according to the seventh embodiment of the present invention. Detailed Implementation

[0053] As described in the background, the distance between the power MOSFET and the temperature detection diode in the existing power management chip cannot meet the needs of the aforementioned recent settings, which seriously affects the temperature detection accuracy and response speed.

[0054] The inventors of the present application have found that one of the reasons for the above technical problems is that the temperature detection diode of the existing power management chip is usually connected to the ground potential of the chip at the cathode. When detecting the temperature of the power MOSFET, due to the large potential difference between the temperature detection diode and the power MOSFET, a large insulation distance is needed to separate the two. This results in that the temperature detection diode in the existing power management chip is far away from the hot spot position, and cannot accurately and timely detect the temperature abnormality of the power MOSFET.

[0055] With Figure 1 and Figure 2 the existing semiconductor device 1 shown in the example, Figure 1 is a schematic diagram of the first semiconductor device 1 of the prior art, Figure 2 is Figure 1 a sectional view along the A-A direction. Among them, Figure 1 The top view of the semiconductor device 1 integrated with the power MOSFET in the existing power management chip is shown in the example. It can be seen that the semiconductor device 1 includes a plurality of MOS devices 11, and a PN junction is arranged in the middle as a temperature detection diode 12. It should be pointed out that, Figure 1 and Figure 2 only part of the MOS devices 11 of the semiconductor device 1 are shown in the example, and in actual application, more MOS devices 11 arrays can be arranged in Figure 1 the left and right columns of MOS devices 11 shown in the figure.

[0056] Figure 1 and Figure 2 are shown in the example taking the MOS device 11 of the High-Side as an example, that is, the source area (Source, marked as S in the figure) of the MOS device 11 is not connected to the ground potential, so the NBL (N buried layer, N-type buried layer) is needed to separate the source area S and the substrate 13. The NBL is usually connected to a potential higher than the voltage of the source area S through the HVNW (High-Voltage N-Well, high-voltage N well, also called high-voltage N well). For example, Figure 2 the HVNW and the drain area (Drain, marked as D in the figure) of the MOS device 11 are connected together and connected to Vin. Among them, Vin can be the system high potential of the power management chip. In this example, the bulk area (Bulk, marked as B in the figure) of the MOS device 11 can be connected to the source area S and connected to the same potential.

[0057] Further, with continued reference toFigure 2 The cathode region (i.e. N-type doped region) of the temperature detecting diode 12 is grounded GND, and the anode region (i.e. P-type doped region) is equivalent to a connection voltage GND+Vf through a current source. Wherein, Vf is the voltage difference of the temperature detecting diode 12 caused by temperature change. In this example, the anode region of the temperature detecting diode 12 is wrapped in an N-type generated N-well (Nwell) to insulate from the substrate 13.

[0058] Based on Figure 1 and Figure 2 The potential Vin of the HVNW connected with the NBL in the device structure and the potential connection mode shown can be in the order of 10-100V, and two diodes D1 and D2 will be formed between the HVNW and the N-well of the temperature detecting diode 12. Wherein, the cathode potential of D1 is close to Vin, and the cathode potential of D2 is close to GND, so D1 will mainly bear the voltage from Vin to GND. In order to ensure that D1 is not broken down, it is usually necessary to ensure that the insulating distance h1 of the P region between the HVNW and the N-well of the temperature detecting diode 12 is greater than the minimum distance required by the process. Usually, the insulating distance h1 is at least 20um (microns).

[0059] This will result in a large insulating distance h1, so that the distance from the temperature detecting diode 12 to the MOS device 11 is lengthened, which is not conducive to the accuracy of temperature detection. In this example, the HVNW is connected with the drain region D of the MOS device 11, so the distance from the temperature detecting diode 12 to the MOS device 11 can be equivalent to the insulating distance h1.

[0060] On the other hand, in Figure 2 The device structure shown, there is a lateral parasitic transistor 14 (lateral parasitic PNP in this example) between the base region B of the MOS device 11, the NBL and the substrate 13. When the potential of the base region B (and the connected source region S) is higher than that of the drain region D, there will be a current flowing from the base region B to the substrate 13. In order to avoid the influence of the lateral parasitic transistor 14 on the performance of the MOS device 11, a layer of P-type and HVNW2 will be added outside the HVNW of the first layer NBL to the surface of the substrate 13, and the HVNW2 will be connected to a high potential, as shown in Figure 2 In this way, the lateral parasitic transistor 14 is blocked by the HVNW2 and the NBL. Figure 3

[0061] Based on Figure 3 ​The distance between the P-type substrate 13 and the N-well of the temperature detection diode 12 is still required to be a safe distance of h1. Moreover, since the HVNW 2 is connected to the MOS device 11 further than the HVNW to the MOS device 11, the distance between the temperature detection diode 12 and the MOS device 11 becomes further, which is h3. In practical applications, the distance of the insulation distance h3 can reach 40um.

[0062] In some embodiments, Figure 2 In the shown structure, the HVNW connected to the NBL and the drain D of the MOS device 11 can be separated, such as Figure 4 In this case, the actual distance h4 between the temperature detection diode 12 and the MOS device 11 will be longer than h1, further limiting the temperature detection accuracy.

[0063] In some embodiments, the prior art provides a semiconductor device 1 to reduce the distance of the insulation distance h1 or reduce the influence of the aforementioned lateral parasitic triode 14 on the MOS device 11 by using a deep trench isolation (DTI) technology. Specifically, referring to Figure 5 A deeper (e.g. 15um) insulation trench 15 is added between the HVNW and the N-well of the temperature detection diode 12, so as to isolate the MOS device 11 and the surrounding. Compared with Figure 2 the shown process technology using PN isolation (i.e. the N-well of the temperature detection diode 12, the HVNW and the P-type substrate 13 part between them), Figure 5 The DTI process technology used in the shown semiconductor device 1 can reduce the distance of the insulation distance h1 to h6. In practical applications, the insulation distance h6 can usually be 10um.

[0064] However, the filler of the DTI is an insulation material, such as silicon dioxide. The thermal conductivity of the insulation material is generally poor, for example, the thermal conductivity of silicon dioxide is 0.27 (W / m·K, watt / meter·degree), while the thermal conductivity of silicon is greater than 100 (W / m·K), which is quite different. This leads to a large temperature difference between the temperature detection diode 12 and the MOS device 11, and under the blockage of the insulation trench 15 with poor thermal conductivity, the temperature change of the MOS device 11 cannot be effectively transmitted to the temperature detection diode 12. Therefore, even based on Figure 5 The shown device structure and potential connection mode still cannot accurately and timely realize the temperature detection of the MOS device 11.

[0065] To solve the above technical problems, the embodiment of the present application provides a semiconductor device, comprising: a semiconductor substrate, the front surface of the semiconductor substrate has adjacent first and second regions, a first isolation belt is formed around the first region, the first isolation belt is adapted to connect a first voltage; a MOS device is located in the first region; a temperature detection diode is located in the second region, one of the cathode region and the anode region of the temperature detection diode is adapted to connect a second voltage, and the other is adapted to connect a current source, the difference between the second voltage and the first voltage is less than a preset tolerance range.

[0066] The present application discloses a scheme for reducing or even eliminating the potential difference between the temperature detection diode and the first isolation belt, so that the MOS device and the temperature detection diode can work normally without maintaining a large insulation distance. Thus, the distance between the temperature detection diode and the MOS device is greatly reduced, so that the temperature detection diode can be deployed closer to the MOS device, which is beneficial to improve the temperature detection accuracy and response speed. Taking the first voltage as a high voltage as an example, compared with the prior art which usually connects the temperature detection diode to ground, the temperature detection diode is connected to a high level in the present application, so as to realize the reduction or even elimination of the potential difference.

[0067] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0068] Next, the embodiments of the present application will be described in detail with reference to the accompanying drawings. The same parts are marked with the same reference numerals in the drawings. Each embodiment is only an example, and of course the structures shown in different embodiments can be partially replaced or combined. In the modified example, the description of matters common to the first embodiment is omitted, and only the different points are described. In particular, the same effects produced by the same structures are no longer mentioned one by one for each embodiment.

[0069] Figure 6 is a sectional view of a semiconductor device 200 according to a first embodiment of the present application, Figure 7 is Figure 6 is a top view of the semiconductor device 200 shown in FIG. 1. Among them, Figure 6 emphasizes the Figure 7 is a sectional view of the temperature detection diode and the device structure around the temperature detection diode in the semiconductor device 200.

[0070] The present embodiment can be applied to a temperature detection scene, such as detecting the heating phenomenon of a functional device in the semiconductor device 200. The functional device may, for example, be a MOS device, such as a power MOSFET. The semiconductor device 200 can belong to a part of a power management chip, and is used to realize part or all of the functions of the power management chip. Alternatively, the semiconductor device 200 can be a power management chip.

[0071] In particular, referring to Figure 6 The semiconductor device 200 described in the embodiments can include a semiconductor substrate 201, a MOS device 21, and a temperature detection diode 22.

[0072] In particular, the semiconductor substrate 201 can have opposite front side 201a and back side 201b. The front side 201a of the semiconductor substrate 201 can also be referred to as a surface of the semiconductor substrate 201. Figure 7 is a schematic view of the semiconductor device 200 as viewed from the front side 201a of the semiconductor substrate 201.

[0073] Further, in combination with Figure 6 and Figure 7 , the front side 201a of the semiconductor substrate 201 has adjacent first region 202 and second region 203. The MOS device 21 can be located in the first region 202, and the temperature detection diode 22 can be located in the second region 203.

[0074] In some embodiments, the second region 203 can be substantially located at the center of the front side 201a of the semiconductor substrate 201, and the regions of the front side 201a other than the second region 203 can be the first region 202. Thus, the temperature detection diode 22 located in the second region 203 can reliably perform temperature detection on the MOS device 21 formed at any position of the front side 201a. In actual applications, the second region 203 can also be located at any position of the front side 201a of the semiconductor substrate 201, and is not limited to the central region.

[0075] In some embodiments, the number of second regions 203 can be multiple and distributed in different regions of the front side 201a of the semiconductor substrate 201. Thus, the temperature detection diodes 22 located in different second regions 203 can perform temperature detection on the nearby MOS devices 21. This is advantageous to improve the accuracy and response speed of temperature detection.

[0076] In one specific implementation, continuing to refer to Figure 6 and Figure 7 , a first isolation band 23 can be formed around the first region 202 for isolating the first region 202 from other parts of the semiconductor substrate 201.

[0077] In particular, the first isolation band 23 can include a first type well 231 disposed around the first region 202 and located at least between the first region 202 and the second region 203 to isolate the first region 202 from the second region 203. For example, referring to Figure 7 , the first type well 231 can be disposed around the second region 203 to form a boundary between the first region 202 and the second region 203. In some embodiments, the first type well 231 can be, for example, an HVNW.

[0078] Further, the first-type well 231 can also be located at a side of the first region 202 away from the second region 203, and enclose the whole first region 202. Figure 6 The first-type well 231 located at a side of the first region 202 away from the second region 203 is not shown. In some embodiments, the first-type well 231 is formed by a lateral process. Figure 6 As shown in the view angle, two MOS devices 21 can be arranged between the first-type wells 231 located at two sides of the first region 202, and the two MOS devices 21 are arranged symmetrically with respect to the middle line between them.

[0079] Further, continuing to refer to Figure 6 , the first isolation belt 23 can include a first buried layer 232 located below the first region 202 and connected with the first-type well 231, so as to isolate the first region 202 from the semiconductor substrate 201. In some embodiments, the first buried layer 232 can be, for example, an NBL.

[0080] Thus, the first buried layer 232 located below the first region 202 is connected with the first-type well 231 located at the inner and outer sides of the first region 202, so as to jointly form the first isolation belt 23 that isolates the first region 202 from the semiconductor substrate 201.

[0081] In a specific implementation, the first isolation belt 23 is adapted to be connected with a first voltage V1. For example, the first-type well 231 can be provided with an electrode to directly or indirectly connect a power supply end (not shown in the figure) of a power management chip.

[0082] In a specific implementation, the MOS device 21 can be processed on the front surface 201a of the semiconductor substrate 201 by a lateral process. The source S, gate G, drain D and bulk B of the MOS device 21 are all located on the front surface 201a of the semiconductor substrate 201.

[0083] In some embodiments, the drain D of the MOS device 21 is closer to the first-type well 231 than the source S / bulk B. Further, the first-type well 231 and the drain D can be connected, as shown in Figure 6 Alternatively, the first-type well 231 and the drain D can have a gap that is not zero, similar to Figure 4 In actual applications, it can also be that the source S / bulk B of the MOS device 21 is closer to the HVNW than the drain D.

[0084] In a specific implementation, continuing to refer to Figure 6 , the second region 203 can be formed with a first well region 24, and the temperature detection diode 22 is located in the first well region 24. Thus, the temperature detection diode 22 is isolated from the semiconductor substrate 201 by the first well region 24.

[0085] Further, the first well region 24 and the first isolation belt 23 have a gap which is not zero, so as to avoid D1 breakdown.

[0086] In one embodiment, one of the cathode region and the anode region of the temperature detection diode 22 is adapted to be connected to the second voltage V2, and the other is adapted to be connected to a current source. Figure 6 For example, the anode region of the temperature detection diode 22 is adapted to be connected to the second voltage V2, and the cathode region of the temperature detection diode 22 is equivalent to be connected to V2-Vf.

[0087] Further, the difference between the second voltage V2 and the first voltage V1 is less than a preset tolerance range. The preset tolerance range can be determined according to the breakdown voltage between the temperature detection diode 22 and the first isolation belt 23. For example, by making the difference between the second voltage V2 and the first voltage V1 less than the breakdown voltage between the temperature detection diode 22 and the first isolation belt 23, the insulation distance h2 between the first well region 24 where the temperature detection diode 22 is located and the first type well 231 can be effectively shortened, thereby greatly shortening the distance between the temperature detection diode 22 and the MOS device 21.

[0088] In some embodiments, V2=V1=Vin, that is, the P region of the temperature detection diode 22 is connected to Vin, and the N region is connected to Vin-Vf through the current source. At this time, the cathode potential of D1 is Vin, and the cathode potential of D2 is Vin-Vf. Since the first well region 24 and the first type well 23 are basically at the same potential, the insulation distance h2 can be shortened to a very close distance. Tests show that the distance h2 can be 10 um. As can be seen, by using the present embodiment, a DTI process structure such as the insulating groove 15 shown in the prior art is not needed to obtain a shorter insulation distance h2, and the temperature detection accuracy and response speed of the semiconductor device 200 will not be affected by the insulation material, so the accuracy and response speed are both better. Figure 5

[0089] In some embodiments, the anode region of the temperature detection diode 22 can be connected to a voltage less than Vin, that is, the second voltage V2 can be slightly less than the first voltage V1, such as V2=Vin-1V. The effect on the insulation distance h2 can be ignored.

[0090] In some embodiments, the first voltage V1 can be less than the second voltage V2.

[0091] In some embodiments, the first voltage V1 can be greater than the second voltage V2.

[0092] ​In one embodiment, the region of the cathode region and the anode region of the temperature detecting diode 22 which is opposite to the doping type of the first isolation belt 23 is adapted to be connected to the second voltage V2. For example, referring to Figure 6 In order to isolate the P-type substrate 201 and the MOS device 21, the first isolation belt 23 is NBL and HVNW with N-type doping, and similarly, the first well region 24 is N-well. Accordingly, in this example, the P region (i.e. the anode region) of the temperature detecting diode 22 is adapted to be connected to the second voltage V2.

[0093] In one variation, the region of the cathode region and the anode region of the temperature detecting diode 22 which is the same as the doping type of the first isolation belt 23 is adapted to be connected to the second voltage V2. For example, referring to Figure 6 The N region (i.e. the cathode region) of the temperature detecting diode 22 is adapted to be connected to the second voltage V2. Further, V2≥Vp-Vf, in order to avoid the diode conduction from the P-type substrate 201 around the cathode region to the cathode region. Wherein Vp is the potential of the surface of the P-type substrate 201 around the cathode region, which is the fourth voltage V4 as described below.

[0094] In one embodiment, by making the difference between the first voltage V1 and the second voltage V2 less than a preset tolerance range, the temperature detecting diode 22 can be placed more flexibly on the premise that the insulation distance h2 is greatly reduced. Specifically, the distance of the temperature detecting diode 22 to different MOS devices 21 can be different. For example, referring to Figure 6 For example, the semiconductor device 200 shown in the figure, the distance of the temperature detecting diode 22 to the MOS device 21 on the left side can be equal to the insulation distance h2, and the distance to the MOS device 21 on the right side can be slightly greater than the insulation distance h2. Since the insulation distance h2 itself is greatly shortened, the detection accuracy and response speed of the semiconductor device 200 described in this example to temperature are still significantly improved due to Figure 2 The semiconductor device 1 shown in the figure.

[0095] In one embodiment, the source region S of the MOS device 21 is adapted to be connected to the third voltage V3.

[0096] For example, taking a high-side switch as an example, the source region S of the MOS device 21 as a high-side switch is usually connected to the third voltage V3 which is higher than the ground potential. Further, the third voltage V3 can be a voltage greater than or equal to 0 and less than or equal to the first voltage V1.

[0097] Figure 8 is a cross-sectional view of a semiconductor device 300 according to a second embodiment of the present application. Here, only the differences between the semiconductor device 300 and the above-described Figure 6 semiconductor device 200 shown in the figure are described.

[0098] Specifically, referring to Figure 8Semiconductor device 300 and the above Figure 6 The main differences of the semiconductor device 200 shown include: the semiconductor device 300 may also include a second buried layer 31 located below the second region 203, and the second buried layer 31 is connected to the first buried layer 232.

[0099] Furthermore, the first type well 231 and the second buried layer 232 located between the first region 202 and the second region 203 can together form a second isolation band 32 surrounding the second region 203. The second isolation band 32 is adapted to isolate the entire second region 203 from the semiconductor substrate 201. Thus, while reducing the insulation distance from h1 to h2, it blocks... Figure 2 The lateral parasitic transistor 14 is shown.

[0100] Furthermore, compared to Figure 3 The structure shown requires an additional HVNW2 layer between the HVNW and the temperature sensing diode 12 to block the lateral parasitic transistor 14. This embodiment achieves the blocking effect by adding a second buried layer 31 below the second region 203, resulting in a simpler internal structure for the semiconductor device 300 and reduced process complexity. Furthermore, the portion of the second isolation band 32 located between the first region 202 and the second region 203 reuses the first-type well 231, thereby reducing the insulation distance from... Figure 3 The h3 shown is shortened to h2.

[0101] In a specific implementation, combined with Figure 7 and Figure 8 The semiconductor device 300 may include an isolation trench 25 disposed around the first region 202 and located on the side of the first region 202 away from the second region 203.

[0102] Compared to Figure 5 The structure shown eliminates the lateral parasitic transistor 14 by adding an insulating groove 15 between the HVNW and the temperature sensing diode 12. This implementation scheme has two advantages: firstly, it eliminates the need for a large insulation distance h1; secondly, it avoids the generation of the lateral parasitic transistor 14 based on the second buried layer 31. Figure 5 The insulating groove 15 in the middle can be removed.

[0103] In other words, the semiconductor device 300 can only provide an insulating trench 25 around the MOS device 21, while removing the DTI structure between the MOS device 21 and the temperature sensing diode 22 to reduce the temperature difference.

[0104] In some embodiments, the isolation trench 25 may be a DTI structure.

[0105] In some embodiments, the isolation trench 25 may be HVNW2.

[0106] In some embodiments, the second buried layer 31 can be directly connected to the first buried layer 232, as shown. For example, the first buried layer 232 and the second buried layer 31 can be located in the same layer and can be fabricated in the same process. Figure 8

[0107] In some embodiments, the second buried layer 31 can be indirectly connected to the first buried layer 232 through the first type well 231 located between the first region 202 and the second region 203. The first buried layer 232 and the second buried layer 31 can be fabricated in different processes.

[0108] In some embodiments, the second buried layer 31 and the first buried layer 232 can have the same doping type, such as NBL. Further, the second buried layer 31 and the first buried layer 232 can have the same doping concentration. Alternatively, the second buried layer 31 and the first buried layer 232 can have different doping concentrations.

[0109] Figure 9 is a cross-sectional view of a semiconductor device 400 according to a third embodiment of the present application. Here, only the differences between the semiconductor device 400 and the semiconductor device 300 shown in Figure 8 will be described.

[0110] Specifically, referring to Figure 9 , the main differences between the semiconductor device 400 and the semiconductor device 300 shown in Figure 8 include that the semiconductor substrate 201 located between the temperature detection diode 22 and the first type well 231 is adapted to be connected to a fourth voltage V4, which is less than or equal to the second voltage V2.

[0111] For example, the P-type semiconductor substrate 201 located around the first well region 24 can have an electrode on the front surface 201a to connect to a high voltage, such as Vin.

[0112] In some embodiments, the P-type semiconductor substrate 201 located around the first well region 24 can be doped with a high concentration of P-type impurities to form a high concentration P+ P-region and have an electrode in the region.

[0113] Figure 10 is a cross-sectional view of a semiconductor device 500 according to a fourth embodiment of the present application. Here, only the differences between the semiconductor device 500 and the semiconductor device 300 shown in Figure 8 will be described.

[0114] Specifically, referring to Figure 10 , the main differences between the semiconductor device 500 and the semiconductor device 300 shown in Figure 8 ​The main differences in the semiconductor device 300 shown include: the first well region 24 can be removed. That is, the temperature sensing diode 22 is formed directly on the front side 201a of the semiconductor substrate 201 within the second region 203.

[0115] Furthermore, the entire P-type semiconductor substrate 201 surrounded by the second isolation band 32 can serve as the anode region of the temperature sensing diode 22.

[0116] Since the second region 203 and the semiconductor substrate 201 are insulated by the second isolation band 32, and the anode region of the temperature sensing diode 22 is suitable for connection to the second voltage V2 with a higher potential, the first well region 24 is unnecessary. This further simplifies the manufacturing process of the semiconductor device 500.

[0117] Figure 11 This is a cross-sectional view of a semiconductor device 600 according to the fifth embodiment of the present invention. This view primarily focuses on the semiconductor device 600 and the aforementioned... Figure 8 The differences of the semiconductor device 300 shown will be explained.

[0118] Specifically, refer to Figure 11 Semiconductor device 600 and the above Figure 8 The main differences between the semiconductor device 300 shown include: the drain region D of the first-type well 231 and the MOS device 21 has a non-zero gap. That is, the drain region D of the first-type well 231 and the MOS device 21 are phase-separated.

[0119] Compared to Figure 4 In the structure shown, because the insulation distance h2 between the first well region 24 and the first type well 231 is greatly shortened, the distance between the temperature sensing diode 22 and the MOS device 21 can be shortened from h4 to h5. Experiments show that h5 can be 15µm.

[0120] In the above Figure 6 to Figure 11 In a common variation of the illustrated embodiment, the number of temperature sensing diodes 22 can be multiple, connected in series and distributed in the second region 203. Therefore, the final detection voltage can be increased from Vf with a single temperature sensing diode 22 to N × Vf, where N is the total number of temperature sensing diodes 22 and is an integer greater than or equal to 2. This improves detection sensitivity.

[0121] Therefore, by adopting this embodiment, the potential difference between the temperature sensing diode 22 and the first isolation band 23 is reduced or even eliminated, ensuring the normal operation of both the MOS device 21 and the temperature sensing diode 22 without maintaining a large insulation distance. This significantly reduces the distance between the temperature sensing diode 22 and the MOS device 21, allowing the temperature sensing diode 22 to be deployed closer to the MOS device 21, which improves temperature detection accuracy and response speed. Taking a high voltage V1 as an example, in this embodiment, the temperature sensing diode 22 is connected to a high level, thus reducing or even eliminating the potential difference.

[0122] Figure 12 This is a flowchart illustrating a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. This embodiment is suitable for manufacturing the aforementioned... Figure 6 to Figure 11 Semiconductor devices 200, 300, 400, 500, and 600 are shown. Therefore, explanations of the terms used in this embodiment can be found by referring to... Figure 6 to Figure 11 The relevant descriptions of the embodiments shown will not be repeated here.

[0123] Specifically, refer to Figure 12 The semiconductor device manufacturing method described in this embodiment may include the following steps:

[0124] Step S101: Provide a semiconductor substrate, the front side of which has adjacent first and second regions;

[0125] Step S102: A first isolation strip is formed around the first region, the first isolation strip being adapted to connect a first voltage;

[0126] Step S103: Form a MOS device in the first region;

[0127] Step S104: A temperature sensing diode is formed in the second region. One of the cathode region and the anode region of the temperature sensing diode is adapted to be connected to a second voltage, and the other is adapted to be connected to a current source. The difference between the second voltage and the first voltage is less than a preset tolerance range.

[0128] In one specific implementation, in step S101, a P-type semiconductor substrate may be provided. Further, in step S103, a MOS device may be formed on the front side of the P-type semiconductor substrate in the first region using a lateral process.

[0129] In one specific implementation, step S102 may include the steps of: forming a first buried layer beneath the first region; and forming a first type well around the first region and connecting it to the first buried layer, wherein the first type well is located at least between the first region and the second region. For example, N-type ion implantation or chemical vapor deposition can be performed on the P-type semiconductor substrate of the first region to form the first buried layer beneath the first region. Further, N-type ion implantation can be performed between the first region and the second region, and on the P-type semiconductor substrate on the side of the first region away from the second region, to form the first type well connecting the first buried layer.

[0130] Furthermore, electrodes are provided in the first type of well for subsequent connection of a first voltage.

[0131] In one specific implementation, step S104 may include the steps of: forming a first well region by doping in the second region, wherein the first well region and the first isolation band have a non-zero gap; and forming a temperature sensing diode in the second well region. For example, N-type doping can be performed on the front side of the P-type semiconductor substrate in the second region to obtain an N-type first well region, and then P-type doping and N-type doping can be performed in the first well region respectively to obtain a temperature sensing diode.

[0132] Furthermore, electrodes are respectively set in the cathode and anode regions of the temperature sensing diode to facilitate the subsequent connection of a second voltage and current source.

[0133] In one specific implementation, step S103 may include the steps of forming a source region and a drain region in the first region, wherein the drain region is closer to the first-type well than the source region, and the first-type well and the drain region are connected or have a non-zero gap. For example, for a MOS device fabricated using a lateral process, a source region, a drain region, a base region, and a gate region may be formed in the first region.

[0134] In one specific implementation, the manufacturing method described in this embodiment may further include the step of forming an isolation trench around the first region on the side of the first region away from the second region. For example, a DTI (Dielectric Tunneling Insulation) trench may be dug around the first region on the side of the first region away from the second region and filled with insulating material.

[0135] Thus, it is possible to prepare... Figure 6 and Figure 7 The semiconductor device 200 shown.

[0136] In one specific implementation, the manufacturing method described in this embodiment may further include the step of: forming a second buried layer below the second region and connecting it to the first buried layer while / before / after forming the first buried layer.

[0137] For example, while forming the first buried layer, N-type ion implantation or chemical vapor deposition can also be performed below the second region located in the same layer to obtain the second buried layer.

[0138] Furthermore, by forming a second buried layer below the second region, before step S104, the manufacturing method described in this embodiment may further include: forming a second isolation zone based on the first trap and the second buried layer located between the first region and the second region.

[0139] Thus, it is possible to prepare... Figure 8 The semiconductor device 300 shown has a first-type well and a drain region of a MOS device connected together. Alternatively, it can be fabricated as follows: Figure 11 The semiconductor device 600 shown has a first-type well and a drain region of a MOS device that are phase-separated.

[0140] In one embodiment, the semiconductor substrate located between the temperature sensing diode and the first-type well is adapted to connect a fourth voltage, which is less than or equal to the second voltage. For example, electrodes can be disposed on the semiconductor substrate between the first well region and the first-type well for subsequent connection of the fourth voltage.

[0141] Thus, it is possible to prepare... Figure 9 The semiconductor device 400 shown.

[0142] In one specific implementation, given that a second buried layer is provided below the second region, the step of forming the first well region can be omitted when performing step S104. Instead, P-type doping and N-type doping can be performed directly in the second region surrounded by the second isolation band to obtain a temperature sensing diode.

[0143] Thus, it is possible to prepare... Figure 10 The semiconductor device shown is 500.

[0144] In a common variation of the above embodiments, step S104 may include the steps of: dispersing and forming a plurality of temperature sensing diodes in the second region; and connecting the plurality of temperature sensing diodes in series. This allows for the fabrication of a semiconductor device with higher sensitivity.

[0145] By improving the potentials at which the first isolation band and the temperature sensing diode are coupled, the potential difference between them is reduced or even eliminated, allowing the temperature sensing diode to be positioned closest to the MOS device. Consequently, the semiconductor device manufactured using this method can detect the heating phenomenon of the MOS device with higher accuracy and faster response speed, thus improving the reliability of the semiconductor device.

[0146] It should be noted that although the P-type semiconductor substrate is exemplarily shown in the figures, the N-type semiconductor substrate can also be used in actual applications, which does not affect the implementation of the present disclosure. When the N-type semiconductor substrate is used, the first isolation band can include a P-type buried layer and a high-voltage P-well, and similarly, the second buried layer is a P-type doped buried layer, and the first well region is a P-well. At this time, the cathode region of the temperature detection diode can be coupled to the second voltage, and the anode region is coupled to the current source.

[0147] Figure 13 is an equivalent schematic diagram of a temperature detection circuit according to a seventh embodiment of the present application. The temperature detection circuit according to the present embodiment is used to detect the heat generation phenomenon of the MOS device in the semiconductor device 200, 300, 400, 500 and 600. Figure 6 to Figure 11

[0148] Specifically, referring to Figure 13 , the temperature detection circuit according to the present embodiment can include the semiconductor device 200, 300, 400, 500 and 600 described above; a first voltage output end (not shown in the figure) electrically connected to the first isolation band 23 to provide a first voltage V1; a second voltage output end 1301 electrically connected to one of the cathode region and the anode region of the temperature detection diode 22 to provide a second voltage V2, and the difference between the second voltage V2 and the first voltage V1 is less than a preset tolerance range; a current source 1302 electrically connected to the other of the cathode region and the anode region of the temperature detection diode 22; and a detection module 1303 coupled to the cathode region and the anode region of the temperature detection diode 22, respectively, for detecting a voltage difference Vf between the cathode region and the anode region, and determining the temperature of the MOS device 21 according to the voltage difference Vf. Figure 6 to Figure 11 For example, referring to

[0149] , the second voltage output end 1301 can be electrically connected to the anode region of the temperature detection diode 22, and the current source 1302 can be electrically connected to the cathode region of the temperature detection diode. Figure 6 to Figure 13 Further, according to the characteristic curve of the voltage and temperature of the diode, the detection module 1303 can identify the temperature of the MOS device 21 according to the current detected voltage drop (i.e. voltage difference Vf) of the temperature detection diode 22. Thus, temperature detection can be achieved.

[0150] In some embodiments, the first voltage output end and the second voltage output end 1301 can share the same voltage end.

[0151]

[0152] ​​Therefore, the temperature detection circuit in the present application can detect the heat phenomenon of the MOS device more accurately and quickly.

[0153] In the present application, "greater than" can include greater than and greater than or equal to. Similarly, "less than" in the present application can include less than and less than or equal to.

[0154] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, therefore the protection scope of the present application should be limited by the scope defined by the claims.

Claims

1. A semiconductor device, characterized by, Comprising: a semiconductor substrate, a front surface of the semiconductor substrate having a first region and a second region adjacent to each other, a first isolation band being formed around the first region, the first isolation band being connected to a first voltage; a MOS device being located in the first region; a temperature detecting diode being located in the second region, one of a cathode region and an anode region of the temperature detecting diode being connected to a second voltage, the other being connected to a current source, a difference between the second voltage and the first voltage being less than a preset tolerance range, the preset tolerance range being determined according to a breakdown voltage between the temperature detecting diode and the first isolation band.

2. The semiconductor device according to claim 1, wherein The region of the cathode region and the anode region of the temperature detecting diode which is opposite to a doping type of the first isolation band is connected to the second voltage.

3. The semiconductor device of claim 1, wherein The second region is formed with a first well region, the temperature detecting diode being located in the first well region, the first well region and the first isolation band having a non-zero gap.

4. The semiconductor device of claim 1, wherein The first isolation band comprises: a first type well being disposed around the first region and being located at least between the first region and the second region; a first buried layer being located below the first region and being connected to the first type well.

5. The semiconductor device according to claim 4, wherein The MOS device comprises a drain region and a source region, the drain region being closer to the first type well than the source region, the first type well being connected to the drain region or having a non-zero gap.

6. The semiconductor device of claim 4, wherein Further comprising: a second buried layer being located below the second region, the second buried layer being connected to the first buried layer.

7. The semiconductor device of claim 6, wherein The first buried layer and the second buried layer are located in the same layer.

8. The semiconductor device of claim 6, wherein, A second isolation band is formed around the second region, the second isolation band being formed by the first type well and the second buried layer which are located between the first region and the second region.

9. The semiconductor device of claim 8, wherein, The semiconductor substrate located between the temperature detecting diode and the first type well is connected to a fourth voltage, the fourth voltage being less than or equal to the second voltage.

10. The semiconductor device of claim 1, wherein Further comprising: an isolation trench being disposed around the first region and being located at a side of the first region away from the second region.

11. The semiconductor device according to any one of Claims 1 to 10, wherein The temperature detecting diode is in a plurality, the plurality of temperature detecting diodes being connected in series and being dispersedly disposed in the second region.

12. A method of manufacturing a semiconductor device, characterized by Comprising: providing a semiconductor substrate, a front surface of the semiconductor substrate having a first region and a second region adjacent to each other; forming a first isolation band around the first region, the first isolation band being connected to a first voltage; forming a MOS device in the first region; forming a temperature detecting diode in the second region, one of a cathode region and an anode region of the temperature detecting diode being connected to a second voltage, the other being connected to a current source, a difference between the second voltage and the first voltage being less than a preset tolerance range, the preset tolerance range being determined according to a breakdown voltage between the temperature detecting diode and the first isolation band.

13. The manufacturing method according to claim 12, wherein The region of the cathode region and the anode region of the temperature detecting diode which is opposite to a doping type of the first isolation band is connected to the second voltage.

14. The manufacturing method according to claim 12, wherein The forming a temperature detecting diode in the second region comprises: doping to form a first well region in the second region, the first well region and the first isolation band having a non-zero gap; forming the temperature detecting diode in the first well region.

15. The manufacturing method according to claim 12, wherein The first isolation zone surrounding the first region comprises: forming a first buried layer under the first region; forming a first type well surrounding the first region and connecting with the first buried layer, the first type well being located between the first region and the second region.

16. The manufacturing method according to claim 15, wherein The MOS device formed in the first region comprises: forming a source region and a drain region in the first region respectively, wherein the drain region is closer to the first type well than the source region, and the first type well and the drain region are connected or have a non-zero gap.

17. The manufacturing method according to claim 15, wherein Further comprising: forming a second buried layer under the second region and connecting with the first buried layer at the same time / before / after forming the first buried layer.

18. The manufacturing method according to claim 17, wherein The first buried layer and the second buried layer are located in the same layer.

19. The manufacturing method according to claim 17, wherein Before forming the temperature detection diode in the second region, further comprising: surrounding the first type well and the second buried layer together to form a second isolation zone between the first region and the second region.

20. The manufacturing method of claim 17, wherein, The semiconductor substrate between the temperature detection diode and the first type well is connected to a fourth voltage, which is less than or equal to the second voltage.

21. The manufacturing method according to claim 12, wherein Further comprising: forming an isolation trench surrounding the first region on the side of the first region away from the second region.

22. The manufacturing method of claim 12, wherein, The temperature detection diode formed in the second region comprises: forming a plurality of temperature detection diodes dispersed in the second region; connecting a plurality of the temperature detection diodes in series.

23. A temperature detection circuit, characterized in that, Comprise: the semiconductor device of any one of claims 1 to 11; a first voltage output terminal electrically connected to the first isolation zone to provide a first voltage; a second voltage output terminal electrically connected to one of the cathode region and the anode region of the temperature detection diode to provide a second voltage, the difference between the second voltage and the first voltage being less than a predetermined tolerance range; a current source electrically connected to the other of the cathode region and the anode region of the temperature detection diode; a detection module coupled to the cathode region and the anode region of the temperature detection diode respectively, the detection module being configured to detect a voltage difference between the cathode region and the anode region, and determine a temperature of the MOS device according to the voltage difference.

24. The temperature sensing circuit of claim 23, wherein, The second voltage output terminal is electrically connected to the anode region, and the current source is electrically connected to the cathode region.

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