Duty cycle correction apparatus and method

Abstract

The present disclosure relates to a duty cycle correction apparatus, method, and clock circuit. The duty cycle correction apparatus includes a duty cycle correction circuit and a duty cycle control circuit. The duty cycle correction circuit corrects a duty cycle of an input clock signal based on a duty cycle control signal and a duty cycle resolution control signal to generate an output clock signal. The duty cycle control circuit generates the duty cycle control signal by detecting the duty cycle of the output clock signal, generates a duty cycle correction completion signal when the duty cycle correction is completed, and re-corrects the duty cycle of the input clock signal by activating the duty cycle resolution control signal when the duty cycle correction completion signal is activated at a timing earlier than a reference time.

Description

Technical Field

[0001] Various embodiments of this disclosure may generally relate to integrated circuit technology, and more specifically, to duty cycle correction apparatus and methods, and semiconductor devices using the duty cycle correction apparatus and methods. Background Technology

[0002] Electronic devices may include many electronic components, and computer systems within electronic devices may include many semiconductor devices composed of semiconductor elements. The semiconductor devices constituting a computer system can communicate with each other by sending and receiving clock signals and data. Semiconductor devices can send data to other semiconductor devices synchronously with clock signals, or receive data sent from other semiconductor devices.

[0003] Semiconductor devices can synchronize clock signals and data using internal circuitry; however, the phase between the clock signal and data can change due to transistor skew and process variations. When the phase between the clock signal and data changes, the effective data window or duration may decrease, potentially making accurate data communication within the semiconductor device difficult. Therefore, semiconductor devices can include duty cycle correction circuitry to compensate for the phase shift between the data and clock signals. Summary of the Invention

[0004] In one embodiment of this disclosure, a duty cycle correction device may include: a duty cycle correction circuit configured to receive an input clock signal and correct the duty cycle of the input clock signal based on a duty cycle control signal and a duty cycle resolution control signal to generate an output clock signal, wherein the duty cycle of the input clock signal is corrected by changing the resolution based on the duty cycle resolution control signal; and a duty cycle control circuit configured to detect the duty cycle of the output clock signal to generate a duty cycle control signal, generate a duty cycle correction completion signal when the duty cycle correction of the input clock signal is completed, and activate the duty cycle resolution control signal when the duty cycle correction completion signal is activated at a timing earlier than a reference time.

[0005] In one embodiment of this disclosure, a duty cycle correction device may include: a duty cycle correction circuit configured to receive an input clock signal and correct the duty cycle of the input clock signal based on a duty cycle control signal and a duty cycle resolution control signal to generate an output clock signal, wherein the duty cycle of the input clock signal is corrected by changing the resolution of the duty cycle correction of the input clock signal based on the duty cycle resolution control signal; and a duty cycle control circuit configured to count the input clock signal and activate the duty cycle resolution control signal when the count value of the input clock signal is less than a threshold in a state where the duty cycle correction completion signal is activated.

[0006] In one embodiment of this disclosure, a duty cycle correction device may include: a first variable driver configured to drive an input clock signal based on a duty cycle control signal and correct the duty cycle of the input clock signal to output an output clock signal to an output node; and a second variable driver including: a first PMOS transistor, to which the input clock signal is input and a power supply voltage is applied to the source terminal of the first PMOS transistor; and a second PMOS transistor, to which a complementary duty cycle resolution control signal is input and the source terminal of the second PMOS transistor is connected to the drain terminal of the first PMOS transistor. The drain terminal of the first NMOS transistor is connected to the output node; the drain terminal of the first NMOS transistor is connected to the output node; the drain terminal of the first NMOS transistor is connected to the output node; the input clock signal is input to the gate terminal of the second NMOS transistor, the drain terminal of the second NMOS transistor is connected to the source terminal of the first NMOS transistor, and a ground voltage is applied to the source terminal of the second NMOS transistor; and the duty cycle control circuit is configured to count the input clock signal and activate the duty cycle resolution control signal when the count value of the input clock signal is less than a threshold while the duty cycle correction completion signal is activated.

[0007] In one embodiment of this disclosure, a duty cycle correction method may include: generating a duty cycle detection signal by detecting the duty cycle of an output clock signal; correcting the duty cycle of an input clock signal at a first resolution by changing a duty cycle control signal based on the duty cycle detection signal; activating a duty cycle resolution control signal when the duty cycle correction operation of the input clock signal at the first resolution is completed at a timing earlier than a reference time and a duty cycle correction completion signal is activated; and re-correcting the duty cycle of the input clock signal at a second resolution when the duty cycle resolution control signal is activated.

[0008] These and other features, aspects, and implementation methods will be described in more detail below. Attached Figure Description

[0009] The above and other aspects, features and advantages of the subject matter of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a diagram showing the configuration of a duty cycle correction device according to one embodiment of the present disclosure; Figure 2 This illustrates one embodiment according to the present disclosure. Figure 1 A diagram showing the configuration of the duty cycle correction circuit; Figure 3 This illustrates one embodiment according to the present disclosure. Figure 1 A diagram showing the configuration of the duty cycle resolution control circuit; Figure 4 This is a flowchart describing a duty cycle correction method according to one embodiment of the present disclosure; and Figure 5 This is a timing diagram showing the operation of a duty cycle correction device according to one embodiment of the present disclosure. Detailed Implementation

[0010] Various embodiments of this disclosure are described in detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments and intermediate structures. In this regard, variations in the configuration and shape illustrated are expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the described embodiments should not be construed as limited to the specific configurations and shapes shown herein, but may include deviations in configuration and shape without departing from the spirit and scope of this disclosure as defined in the appended claims.

[0011] Embodiments of this disclosure are described herein with reference to cross-sectional and / or planar diagrams of the embodiments. However, the embodiments of this disclosure should not be construed as limiting the disclosure. Although some embodiments of this disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of this disclosure.

[0012] Figure 1 This is a diagram showing the configuration of a duty cycle correction device 100 according to one embodiment of the present disclosure. (Refer to...) Figure 1The duty cycle correction device 100 can receive an input clock signal CLK_IN, correct the duty cycle of the input clock signal CLK_IN, and generate an output clock signal CLK_OUT. The input clock signal CLK_IN can be an external clock signal transmitted from an external device including the semiconductor device 100. The duty cycle correction device 100 can perform a duty cycle correction operation to compensate for changes in the duty cycle of the input clock signal CLK_IN.

[0013] The duty cycle correction device 100 can receive the input clock signal CLK_IN, count the input clock count of the input clock signal CLK_IN, detect the duty cycle of the output clock signal CLK_OUT to generate a duty cycle detection signal DDS and a duty cycle control signal DCS<0:3>, generate a duty cycle correction completion signal DCC_DONE when the duty cycle correction is completed based on the duty cycle detection signal DDS, and generate a duty cycle resolution control signal RCS based on the duty cycle correction completion signal DCC_DONE and the input clock count of the input clock signal CLK_IN.

[0014] The duty cycle correction device 100 can generate an output clock signal CLK_OUT by correcting the duty cycle of the input clock signal CLK_IN with a first resolution when the duty cycle resolution control signal RCS is inactive, and generate an output clock signal CLK_OUT by correcting the duty cycle of the input clock signal CLK_IN with a second resolution that is finer than the first resolution when the duty cycle resolution control signal RCS is activated and the input clock count of the input clock signal is less than a threshold.

[0015] The duty cycle correction device 100 may include a duty cycle correction circuit 110 and a duty cycle control circuit 120.

[0016] The duty cycle correction circuit 110 can receive the input clock signal CLK_IN and correct the duty cycle of the input clock signal CLK_IN based on the duty cycle control signal DCS<0:3> and the duty cycle resolution control signal RCS to generate the output clock signal CLK_OUT.

[0017] The duty cycle correction circuit 110 can correct the duty cycle of the input clock signal CLK_IN at a first resolution when the duty cycle resolution control signal RCS is inactive, and re-correct the duty cycle of the input clock signal CLK_IN at a second resolution when the duty cycle resolution control signal RCS is activated. In the duty cycle correction at the first resolution, the duty cycle correction circuit 110 can correct the duty cycle of the input clock signal CLK_IN based on the code value of the duty cycle control signal DCS<0:3>.

[0018] For example, the duty cycle of the error-free input clock signal CLK_IN is 50%. When the duty cycle control circuit 120 generates a duty cycle detection signal DDS that includes information indicating that the low-level period of the output clock signal CLK_OUT is greater than the high-level period of the output clock signal CLK_OUT, the duty cycle correction circuit 110 can correct the duty cycle of the input clock signal CLK_IN based on the code value of the duty cycle control signal DCS<0:3>, which is increased according to the duty cycle detection signal DDS.

[0019] Furthermore, when the duty cycle control circuit 120 generates a duty cycle detection signal DDS that includes information indicating that the high-level period of the output clock signal CLK_OUT is greater than the low-level period of the output clock signal CLK_OUT, the duty cycle correction circuit 110 can correct the duty cycle of the input clock signal CLK_IN based on the code value of the duty cycle control signal DCS<0:3>, which is reduced according to the duty cycle detection signal DDS. The duty cycle correction range based on the code value of the duty cycle control signal DCS<0:3> can be set in the design of the duty cycle correction device 100.

[0020] The duty cycle control circuit 120 can receive the output clock signal CLK_OUT, detect the duty cycle of the output clock signal CLK_OUT to generate a duty cycle detection signal DDS, and generate a duty cycle control signal DCS<0:3> and a duty cycle correction completion signal DCC_DONE based on the duty cycle detection signal DDS.

[0021] The duty cycle control circuit 120 can count the input clock count of the input clock signal CLK_IN, and activate the duty cycle resolution control signal RCS when the input clock count of the input clock signal CLK_IN is less than a threshold while generating the duty cycle correction completion signal DCC_DONE.

[0022] The duty cycle control circuit 120 may include a duty cycle detection circuit 121, a duty cycle control signal generation circuit 122, and a duty cycle resolution control circuit 123.

[0023] The duty cycle detection circuit 121 can receive the output clock signal CLK_OUT and detect the duty cycle of the output clock signal CLK_OUT to generate a duty cycle detection signal DDS. For example, the duty cycle detection circuit 121 can compare the magnitudes of the low-level and high-level periods of the output clock signal CLK_OUT and output the comparison result as the duty cycle detection signal DDS. The duty cycle detection signal DDS may include information indicating how much longer the low-level period of the output clock signal CLK_OUT is compared to the high-level period of the output clock signal CLK_OUT, or information indicating how much longer the high-level period of the output clock signal CLK_OUT is compared to the low-level period of the output clock signal CLK_OUT. The duty cycle detection circuit 121 may include a conventional analog integrator circuit.

[0024] The duty cycle control signal generation circuit 122 can generate the duty cycle control signal DCS<0:3> and the duty cycle correction completion signal DCC_DONE based on the duty cycle detection signal DDS and the correction completion reset signal DCC_DONE_RST. The duty cycle correction completion signal DCC_DONE can be generated when the duty cycle detection circuit 121 continuously generates duty cycle detection signals DDS with different levels.

[0025] For example, when the duty cycle detection circuit 121 generates a duty cycle detection signal DDS with a logic low level and then generates a duty cycle detection signal DDS with a logic high level, or when the duty cycle detection circuit 121 generates a duty cycle detection signal DDS with a logic high level and then generates a duty cycle detection signal DDS with a logic low level, the duty cycle control signal generation circuit 122 can generate a duty cycle correction completion signal DCC_DONE. As will be described later, when the resolution enable signal RCS_EN_EDGE is activated, the correction completion reset signal DCC_DONE_RST can initialize the duty cycle control signal DCS<0:3>.

[0026] The duty cycle resolution control circuit 123 can receive the input clock signal CLK_IN and the duty cycle correction completion signal DCC_DONE, count the input clock count of the input clock signal CLK_IN, and generate the duty cycle resolution control signal RCS and the correction completion reset signal DCC_DONE_RST based on the input clock count of the input clock signal CLK_IN and the duty cycle correction completion signal DCC_DONE.

[0027] For example, when the duty cycle correction completion signal DCC_DONE is generated at a timing earlier than the set reference time (e.g., when the input clock count of the input clock signal CLK_IN is less than a threshold), the duty cycle resolution control circuit 123 can activate the duty cycle resolution control signal RCS. Furthermore, when the duty cycle correction completion signal DCC_DONE is not generated at a timing earlier than the set reference time (e.g., when the input clock count of the input clock signal CLK_IN is greater than a threshold), the duty cycle resolution control circuit 123 can keep the duty cycle resolution control signal RCS in an inactive state.

[0028] Therefore, if the duty cycle correction operation is not completed before the set reference time, the duty cycle resolution control circuit 123 can control the duty cycle correction circuit 110 to terminate the duty cycle correction without requiring additional duty cycle correction operation. If the duty cycle correction operation is completed before the set reference time, the duty cycle resolution control circuit 123 can control the duty cycle correction circuit 110 to additionally perform the duty cycle correction operation with fine duty cycle correction resolution.

[0029] Figure 2 This illustrates one embodiment according to the present disclosure. Figure 1 A diagram showing the configuration of the duty cycle correction circuit 110. (See diagram for reference.) Figure 2 As shown, the duty cycle correction circuit 110 can receive the input clock signal CLK_IN and can perform pull-up or pull-down operations in response to the input clock signal CLK_IN to generate the output clock signal CLK_OUT through the second output node ON. Specifically, the duty cycle correction circuit 110 can correct the duty cycle of the input clock signal CLK_IN based on the duty cycle control signal DCS<0:3> and the duty cycle resolution control signal RCS to generate the output clock signal CLK_OUT through the second output node ON.

[0030] The duty cycle correction method performed by the duty cycle correction circuit 110 will be described below. When the output clock signal CLK_OUT is generated by performing pull-up and pull-down operations in response to the input clock signal CLK_IN, the slew rate of the rising and falling edges of the output clock signal CLK_OUT can be controlled according to the pull-up drive capability and the pull-down drive capability.

[0031] For example, when the slew rate of the rising edge of the clock signal increases and the slew rate of the falling edge of the clock signal decreases, the high-level period of the clock signal can be increased and the low-level period of the clock signal can be decreased. Conversely, when the slew rate of the rising edge of the clock signal decreases and the slew rate of the falling edge increases, the high-level period of the clock signal can be decreased and the low-level period of the clock signal can be increased. When the pull-up drive capability increases, the slew rate of the rising edge can increase, and when the pull-up drive capability decreases, the slew rate of the rising edge can decrease. When the pull-down drive capability increases, the slew rate of the falling edge can increase, and when the pull-down drive capability decreases, the slew rate of the falling edge can decrease.

[0032] Therefore, when the pull-up drive capability increases and the pull-down drive capability decreases, the high-level period of the output clock signal CLK_OUT can be increased, and when the pull-down drive capability increases and the pull-up drive capability decreases, the low-level period of the output clock signal CLK_OUT can be increased. Using the above method, the duty cycle correction circuit 110 can correct the duty cycle of the input clock signal CLK_IN to generate the output clock signal CLK_OUT.

[0033] The duty cycle correction circuit 110 may include a first variable driver 111 and a second variable driver 112.

[0034] The first variable driver 111 can receive the input clock signal CLK_IN and perform pull-up and pull-down operations in response to the input clock signal CLK_IN to output the output clock signal CLK_OUT. The first variable driver 111 can correct the duty cycle of the input clock signal CLK_IN based on the duty cycle control signal DCS<0:3> to generate the output clock signal CLK_OUT.

[0035] The first variable driver 111 may include: a first pull-up / pull-down driver circuit configured to pull up or pull down a first output node OUT in response to an input clock signal CLK_IN; a second pull-up / pull-down driver circuit configured to pull up or pull down a second output node ON in response to a node level of the first output node OUT to output an output clock signal CLK_OUT; and a slew rate control circuit configured to correct the duty cycle of the input clock signal CLK_IN by controlling the slew rate of the output clock signal CLK_OUT based on a duty cycle control signal DCS<0:3>.

[0036] The first pull-up / pull-down driver circuit of the first variable driver 111 can receive the input clock signal CLK_IN and pull up / pull down the first output node OUT in response to the input clock signal CLK_IN. For example, the first pull-up / pull-down driver circuit can pull up the first output node OUT when the input clock signal CLK_IN is at a logic low level, and pull down the first output node OUT when the input clock signal CLK_IN is at a logic high level.

[0037] The second pull-up / pull-down driver circuit of the first variable driver 111 can pull up / pull down the second output node ON in response to the node level of the first output node OUT to generate the output clock signal CLK_OUT. For example, the second pull-up / pull-down driver circuit can pull up the second output node ON when the node level of the first output node OUT is at a logic low level, and pull down the second output node ON when the node level of the first output node OUT is at a logic high level.

[0038] The slew rate control circuit of the first variable driver 111 may include: a first slew rate control circuit configured to control the slew rate of the falling edge of the output clock signal CLK_OUT based on the duty cycle control signal DCS<0:3>; and a second slew rate control circuit configured to control the slew rate of the rising edge of the output clock signal CLK_OUT based on the duty cycle control signal DCS<0:3>.

[0039] The first variable driver 111 may include a plurality of PMOS transistors (e.g., first PMOS transistor P1 to tenth PMOS transistor P10) and a plurality of NMOS transistors (e.g., first NMOS transistor N1 to tenth NMOS transistor N10). The PMOS transistors P1 to P10 and the NMOS transistors N1 to N10 in the first variable driver 111 may have different dimensions from each other (e.g., the channel width of the transistors).

[0040] The first pull-up / pull-down driver circuit of the first variable driver 111 may include a first PMOS transistor P1 and a first NMOS transistor N1. An input clock signal CLK_IN is applied to the gates of the first PMOS transistor P1 and the first NMOS transistor N1. The first PMOS transistor P1 and the first NMOS transistor N1 are respectively connected between the power supply voltage VDD terminal and the first output node OUT, and between the first output node OUT and the ground voltage VSS terminal. The second pull-up / pull-down driver circuit of the first variable driver 111 may include a sixth PMOS transistor P6 and a sixth NMOS transistor N6. The node level of the first output node OUT is applied to the gates of the sixth PMOS transistor P6 and the sixth NMOS transistor N6. The sixth PMOS transistor P6 and the sixth NMOS transistor N6 are respectively connected between the power supply voltage VDD terminal and the second output node ON, and between the second output node ON and the ground voltage VSS terminal.

[0041] In the slew rate control circuit of the first variable driver 111, the first slew rate control circuit may include multiple PMOS transistor pairs P2 and P7, P3 and P8, P4 and P9, and P5 and P10, and the code value DCS of the input clock signal CLK_IN and duty cycle control signal DCS<0:3>. <3> DCS <2> DCS <1> DCS <0> A code value is applied to the gates of the aforementioned plurality of PMOS transistor pairs, and the aforementioned plurality of PMOS transistor pairs are connected in parallel between the power supply voltage VDD terminal and the first output node OUT. The second conversion rate control circuit may include a plurality of NMOS transistor pairs N2 and N7, N3 and N8, N4 and N9, and N5 and N10, and the code value of the duty cycle control signal DCS<0:3> is DCS. <3> DCS <2> DCS <1> DCS <0> A code value and the input clock signal CLK_IN are respectively applied to the gates of the aforementioned plurality of NMOS transistor pairs, and the aforementioned plurality of NMOS transistor pairs are connected in parallel between the first output node OUT and the ground voltage VSS terminal. The number of PMOS transistor pairs and NMOS transistor pairs can correspond to the code value of the duty cycle control signal DCS<0:3>.

[0042] In the first conversion rate control circuit, the seventh PMOS transistor P7 to the tenth PMOS transistor P10 can respond to the code value DCS of the duty cycle control signal DCS<0:3>. <3> DCS <2> DCS <1> DCS <0> The switching speed of the falling edge of the output clock signal CLK_OUT can be increased as the number of PMOS transistors (P7 through P10) that are turned on or off increases. In the second switching speed control circuit, the seventh NMOS transistor (N7) through the tenth NMOS transistor (N10) can respond to the code value DCS of the duty cycle control signal DCS<0:3>. <3> DCS <2> DCS <1> DCS <0> The switching rate of the rising edge of the output clock signal CLK_OUT can be increased as the number of NMOS transistors turned on or off increases from the seventh NMOS transistor N7 to the tenth NMOS transistor N10. The first variable driver 111 can correct the duty cycle (e.g., duty cycle error) of the input clock signal CLK_IN to generate the output clock signal CLK_OUT by controlling the switching rate of the rising and falling edges of the output clock signal CLK_OUT as described above.

[0043] Based on the duty cycle resolution control signal RCS and its complementary signal RCSB (hereinafter referred to as "complementary duty cycle resolution control signal RCSB"), the second variable driver 112 can perform the operation of recalibrating the duty cycle of the input clock signal CLK_IN at a second resolution that is finer than the first resolution.

[0044] The second variable driver 112 may include an eleventh PMOS transistor P11 and a twelfth PMOS transistor P12, as well as an eleventh NMOS transistor N11 and a twelfth NMOS transistor N12. The PMOS transistor pair P11 and P12 can receive the input clock signal CLK_IN and the complementary duty cycle resolution control signal RCSB through their gates, respectively, and can be connected in series between the power supply voltage VDD terminal and the first output node OUT. The NMOS transistor pair N11 and N12 can receive the duty cycle resolution control signal RCS and the input clock signal CLK_IN through their gates, respectively, and can be connected in series between the first output node OUT and the ground voltage VSS terminal.

[0045] The second variable driver 112 can turn on or off the twelfth PMOS transistor P12 in response to the complementary duty cycle resolution control signal RCSB to control the slewing rate of the falling edge of the output clock signal CLK_OUT, and can turn on or off the eleventh NMOS transistor N11 in response to the duty cycle resolution control signal RCS to control the slewing rate of the rising edge of the output clock signal CLK_OUT. Therefore, the second variable driver 112 can additionally correct the duty cycle of the input clock signal CLK_IN with a second resolution to generate the output clock signal CLK_OUT.

[0046] Figure 3 This illustrates one embodiment according to the present disclosure. Figure 1 A diagram showing the configuration of the duty cycle resolution control circuit 123. (See diagram for reference.) Figure 3 As shown, the duty cycle resolution control circuit 123 can receive the input clock signal CLK_IN and the duty cycle correction completion signal DCC_DONE, count the input clock signal CLK_IN, and generate the duty cycle resolution control signal RCS and the complementary duty cycle resolution control signal RCSB based on the input clock count of the input clock signal CLK_IN and the duty cycle correction completion signal DCC_DONE.

[0047] When the duty cycle correction completion signal DCC_DONE is generated at a timing earlier than the set reference time (e.g., when the input clock count of the input clock signal CLK_IN is less than a threshold while the duty cycle correction completion signal DCC_DONE is being generated), the duty cycle resolution control circuit 123 can activate the duty cycle resolution control signal RCS. Furthermore, when the duty cycle correction completion signal DCC_DONE is not generated at a timing earlier than the set reference time (e.g., when the input clock count of the input clock signal CLK_IN is equal to or greater than a threshold while the duty cycle correction completion signal DCC_DONE is being generated), the duty cycle resolution control circuit 123 can keep the duty cycle resolution control signal RCS in an inactive state.

[0048] The duty cycle resolution control circuit 123 may include a resolution control signal generation circuit 300 and a reset signal generation circuit 310.

[0049] The resolution control signal generation circuit 300 can receive the input clock signal CLK_IN and the duty cycle correction completion signal DCC_DONE, count the input clock count of the input clock signal CLK_IN, and generate the resolution enable signal RCS_EN_EDGE, the duty cycle resolution control signal RCS, and the complementary duty cycle resolution control signal RCSB based on the input clock count of the input clock signal CLK_IN and the duty cycle correction completion signal DCC_DONE.

[0050] The resolution control signal generation circuit 300 may include a correction counting circuit 301, a resolution enable signal generation circuit 302, and a resolution control signal output circuit 303.

[0051] The correction counting circuit 301 can receive the input clock signal CLK_IN, count the input clock count of the input clock signal CLK_IN, and compare the input clock count with a preset count to generate a duty cycle correction counting signal DCC_DONE_ct. For example, when the input clock count of the input clock signal CLK_IN is less than the preset count, the correction counting circuit 301 can output the duty cycle correction counting signal DCC_DONE_ct as a logic low level. When the input clock count of the input clock signal CLK_IN is equal to or greater than the preset count, the correction counting circuit 301 can output the duty cycle correction counting signal DCC_DONE_ct as a logic high level.

[0052] The resolution enable signal generation circuit 302 can receive the complementary signal DCC_DONE_ctB (hereinafter referred to as "complementary duty cycle correction count signal DCC_DONE_ctB") of the duty cycle correction count signal DCC_DONE_ct (wherein, the duty cycle correction count signal DCC_DONE_ct is inverted by the first inverter 300-1) and the duty cycle correction completion signal DCC_DONE, and generate the resolution enable signal RCS_EN_EDGE.

[0053] The resolution enable signal generation circuit 302 may include a first NAND gate 302-1 and a second inverter 302-2. The first NAND gate 302-1 can receive a complementary duty cycle correction count signal DCC_DONE_ctB and a duty cycle correction completion signal DCC_DONE, and perform a NAND operation on these signals. The second inverter 302-2 can receive the output signal of the first NAND gate 302-1, invert the output signal, and generate the inverted result as the resolution enable signal RCS_EN_EDGE.

[0054] The resolution control signal output circuit 303 can receive the resolution enable signal RCS_EN_EDGE, and generate the duty cycle resolution control signal RCS and the complementary duty cycle resolution control signal RCSB synchronously with the rising edge of the resolution enable signal RCS_EN_EDGE.

[0055] The resolution control signal output circuit 303 may include a first flip-flop 303-1 and a third inverter 303-2. A power supply voltage VDD may be applied to the input terminal D of the first flip-flop 303-1, and a resolution enable signal RCS_EN_EDGE may be applied to the clock terminal of the first flip-flop 303-1. The first flip-flop 303-1 may output the signal input to the input terminal as an output signal, synchronously with the resolution enable signal RCS_EN_EDGE. The third inverter 303-2 may receive the duty cycle resolution control signal RCS output from the output terminal of the first flip-flop 303-1, invert the duty cycle resolution control signal RCS, and output the inverted result as a complementary duty cycle resolution control signal RCSB.

[0056] The reset signal generation circuit 310 can receive the resolution enable signal RCS_EN_EDGE and output the correction completion reset signal DCC_DONE_RST.

[0057] The reset signal generation circuit 310 may include a second NAND gate 311, a fourth inverter 312, a second flip-flop 313, and a fifth inverter 314. The second NAND gate 311 can receive the complementary signal DCC_RST_CTRLB (hereinafter referred to as the "complementary duty cycle reset control signal DCC_RST_CTRLB") of the resolution enable signal RCS_EN_EDGE and the duty cycle reset control signal DCC_RST_CTRLB, and perform a NAND operation on the resolution enable signal RCS_EN_EDGE and the complementary duty cycle reset control signal DCC_RST_CTRLB. The fourth inverter 312 can invert the output signal of the second NAND gate 311 and output the inverted result as the correction complete reset signal DCC_DONE_RST. The power supply voltage VDD can be applied to the input terminal D of the second flip-flop 313, and the correction complete reset signal DCC_DONE_RST can be applied to the clock terminal of the second flip-flop 313. The second flip-flop 313 can receive the correction completion reset signal DCC_DONE_RST and can be triggered on the falling edge of the correction completion reset signal DCC_DONE_RST to output the duty cycle reset control signal DCC_RST_CTRL. The fifth inverter 314 can receive the output signal of the second flip-flop 313, invert the output signal of the second flip-flop 313, and output the inverted result as the complementary duty cycle reset control signal DCC_RST_CTRLB.

[0058] The calibration completion reset signal DCC_DONE_RST can be transmitted to the duty cycle control signal generation circuit 122 to initialize the duty cycle control signal DCS<0: 3>.

[0059] Figure 4This is for describing one embodiment according to the present disclosure. Figure 1 A flowchart of the duty cycle correction method for the duty cycle correction device 100 shown is provided. Figure 5 This is a timing diagram used to describe the duty cycle correction method of a duty cycle correction device 100 according to one embodiment of the present disclosure. In the following text, reference will be made to... Figures 1 to 5 The duty cycle correction operation of the duty cycle correction device 100 is described in sequence.

[0060] Duty cycle correction of the duty cycle correction device 100 can be started (S21), and the count number of the duty cycle correction completion counter (e.g., the correction counting circuit 301 of the resolution control signal generation circuit 123) DCC_DONE_CT range <1:0> can be set (S22). The count number of the duty cycle correction completion counter can be the same standard as the reference time for correcting the duty cycle.

[0061] The duty cycle correction completion counter may include an option register (not shown) set in the duty cycle resolution control circuit 123, and the counting time and count count can be set. The option register can be configured by a chain of flip-flops.

[0062] For example, the duty cycle correction operation will be described based on the number of counts. For example, when the count range DCC_DONE_CT <1:0> is set to have a binary value "01", the input clock count of the duty cycle correction completion counter is set to 16. However, the number of input clock counts is not limited to this, and when the count range DCC_DONE_CT <1:0> is set to have a binary value "00", "10", or "11", the number of input clock counts can be set to 8, 32, or 64, as shown in operation S22.

[0063] First, the duty cycle correction device 100 can be used to correct the duty cycle. Figure 1 The duty cycle detection circuit 121 detects the duty cycle of the output clock signal CLK_OUT to generate a duty cycle detection signal DDS. The duty cycle correction device 100 can generate a duty cycle control signal DCS<0:3> based on the duty cycle detection signal DDS through the duty cycle control signal generation circuit 122. Then, based on the duty cycle control signal DCS<0:3>, the duty cycle correction device 100 can correct the duty cycle of the input clock signal CLK_IN with a first resolution through the first variable driver 111 to generate the output clock signal CLK_OUT (S23).

[0064] Subsequently, the duty cycle correction device 100 can determine whether the input clock count of the input clock signal CLK_IN is less than a threshold (e.g., 16), and determine whether the duty cycle correction completion signal DCC_DONE is generated from the duty cycle control signal generation circuit 122 (S24).

[0065] Specifically, refer to Figure 5 The duty cycle correction device 100 can receive the input clock signal CLK_IN and count the input clock count of the input clock signal CLK_IN. When the input clock count of the input clock signal CLK_IN is less than a threshold (e.g., between 1 and 15), the duty cycle correction device 100 can generate a duty cycle correction count signal DCC_DONE_ct as a logic low level, and a complementary duty cycle correction count signal DCC_DONE_ctB as a logic high level, which is inverted by the first inverter 300-1.

[0066] Furthermore, the duty cycle correction device 100 can generate a duty cycle correction completion signal DCC_DONE based on the duty cycle detection signal DDS through the duty cycle control signal generation circuit 122. When the duty cycle correction is complete, the duty cycle correction device 100 can generate the duty cycle correction completion signal DCC_DONE as a logic high level. Therefore, in operation S24, when the duty cycle correction completion signal DCC_DONE as a logic high level is generated, the duty cycle correction device 100 can determine whether to generate a complementary duty cycle correction count signal DCC_DONE_ctB as a logic high level.

[0067] When it is determined that a complementary duty cycle correction count signal DCC_DONE_ctB as a logic low level is generated while the duty cycle correction completion signal DCC_DONE as a logic high level is generated (S24: No) (for example, when it is determined that the duty cycle correction was not completed at a timing earlier than the reference time (S24: No)), the duty cycle correction device 100 can generate a resolution enable signal RCS_EN_EDGE as a logic low level and a duty cycle resolution control signal RCS by the duty cycle resolution control circuit 123, and can proceed to operation S27 and complete the duty cycle correction operation without additional duty cycle correction.

[0068] When it is determined that a complementary duty cycle correction count signal DCC_DONE_ctB as a logic high level and a duty cycle correction completion signal DCC_DONE as a logic high level are generated (S24: Yes) (for example, when it is determined that the duty cycle correction is completed at a timing earlier than the reference time (S24: Yes)), the duty cycle correction device 100 can generate a resolution enable signal RCS_EN_EDGE, a duty cycle resolution control signal RCS, and a correction completion reset signal DCC_DONE_RST as logic high levels through the duty cycle resolution control circuit 123, and can proceed to operation S25.

[0069] Figure 2 The second variable driver 112 of the duty cycle correction circuit 110 in the duty cycle correction device 100 can be activated based on the duty cycle resolution control signal RCS (S25), and can recalibrate the duty cycle of the input clock signal CLK_IN with a finer second resolution than the first resolution (S26). At this time, the duty cycle control signal DCS<0:3> can be initialized by the correction completion reset signal DCC_DONE_RST.

[0070] The embodiments described above are intended to illustrate, not limit, the invention. Various alternatives and equivalents may be employed. The invention is not limited to the embodiments described herein. The invention is also not limited to any particular type of semiconductor device. In view of this disclosure, other additions, deletions, or modifications are apparent and are intended to fall within the scope of the appended claims. Furthermore, embodiments may be combined to form additional embodiments.

[0071] Intersection of related applications

[0072] This application claims priority to Korean Patent Application No. 10-2021-0132969, filed on October 7, 2021, and Korean Patent Application No. 10-2022-0063484, filed on May 24, 2022, which are incorporated herein by reference in their entirety.

Claims

1. A duty cycle correction device, the duty cycle correction device comprising: A duty cycle correction circuit, which corrects the duty cycle of an input clock signal based on a duty cycle control signal to generate an output clock signal, and additionally corrects the duty cycle of the input clock signal to generate the output clock signal when a duty cycle resolution control signal is activated. as well as A duty cycle control circuit detects the duty cycle of the output clock signal to generate a duty cycle control signal and a duty cycle correction completion signal for the input clock signal, and activates the duty cycle resolution control signal when the duty cycle correction completion signal is generated at a timing earlier than a reference time.

2. The duty cycle correction device according to claim 1, wherein, The duty cycle correction circuit includes: A first variable driver, which performs a pull-up / pull-down operation on the input clock signal based on the duty cycle control signal; and A second variable driver performs a pull-up / pull-down operation on the input clock signal when the duty cycle resolution control signal is activated.

3. The duty cycle correction device according to claim 1, wherein, The duty cycle control circuit also keeps the duty cycle resolution control signal in an inactive state if the duty cycle correction completion signal is not generated at a time earlier than the reference time.

4. The duty cycle correction device according to claim 3, wherein, The duty cycle control circuit includes: A duty cycle detection circuit detects the duty cycle of the output clock signal to generate a duty cycle detection signal; A duty cycle control signal generation circuit, wherein the duty cycle control signal generation circuit generates the duty cycle correction completion signal and the duty cycle control signal based on the duty cycle detection signal; and A duty cycle resolution control circuit receives the input clock signal and the duty cycle correction completion signal to generate the duty cycle resolution control signal.

5. The duty cycle correction device according to claim 4, wherein, When the correction of the duty cycle of the input clock signal based on the duty cycle control signal is completed, the duty cycle control signal generation circuit generates the duty cycle correction completion signal.

6. The duty cycle correction device according to claim 4, wherein, The duty cycle resolution control circuit also includes: When the duty cycle correction completion signal is generated at a timing earlier than the reference time, the duty cycle resolution control signal is activated, and If the duty cycle correction completion signal is not generated at a timing earlier than the reference time, the duty cycle resolution control signal is kept in an inactive state.

7. A duty cycle correction device, the duty cycle correction device comprising: A duty cycle correction circuit, wherein the duty cycle correction circuit corrects the duty cycle of an input clock signal to generate an output clock signal based on a duty cycle control signal and a duty cycle resolution control signal, wherein the duty cycle correction circuit corrects the duty cycle of the input clock signal based on the duty cycle control signal, and recorrects the duty cycle of the input clock signal based on the duty cycle resolution control signal, wherein the resolutions for correction and recorrection are different from each other; and Duty cycle control circuit, wherein the duty cycle control circuit: The input clock signal is counted. When the correction based on the duty cycle control signal is completed, a duty cycle correction completion signal is generated, and When the count value of the input clock signal is less than the threshold during the timing of generating the duty cycle correction completion signal, the duty cycle resolution control signal is generated.

8. The duty cycle correction device according to claim 7, in, The duty cycle correction circuit corrects the duty cycle of the input clock signal by performing pull-up / pull-down operations on the input clock signal. The duty cycle correction circuit corrects the duty cycle of the input clock signal by changing the pull-up / pull-down drive capability based on the code value of the duty cycle control signal. The duty cycle correction circuit, based on the duty cycle resolution control signal, recalibrates the duty cycle of the input clock signal by performing pull-up / pull-down operations on the input clock signal. The resolution used for recalibration is finer than the resolution used for calibration.

9. The duty cycle correction device according to claim 8, wherein, The duty cycle control circuit includes: A duty cycle detection circuit detects the duty cycle of the output clock signal to generate a duty cycle detection signal; A duty cycle control signal generation circuit receives the duty cycle detection signal, generates a duty cycle control signal whose code value changes based on the duty cycle detection signal, and generates a duty cycle correction completion signal when duty cycle correction is complete; and A duty cycle resolution control circuit receives the input clock signal and the duty cycle correction completion signal to generate the duty cycle resolution control signal. The duty cycle resolution control circuit also activates the duty cycle resolution control signal when the duty cycle correction completion signal is generated at a time earlier than the reference time.

10. A duty cycle correction device, the duty cycle correction device comprising: A first variable driver, which corrects the duty cycle of an input clock signal with a first resolution based on a duty cycle control signal to generate an output clock signal; The second variable driver, based on the duty cycle resolution control signal, recalibrates the duty cycle of the input clock signal with a second resolution that is finer than the first resolution to generate the output clock signal; as well as Duty cycle control circuit, wherein the duty cycle control circuit: The input clock signal is counted. When the calibration is complete, a duty cycle calibration completion signal is generated, and When the count value of the input clock signal is less than the threshold during the timing of generating the duty cycle correction completion signal, the duty cycle resolution control signal is generated.

11. The duty cycle correction device according to claim 10, in, The first variable driver corrects the duty cycle of the input clock signal by performing a pull-up / pull-down operation on the input clock signal to generate the output clock signal, and The first variable driver corrects the duty cycle of the input clock signal by changing the pull-up / pull-down drive capability based on the code value of the duty cycle control signal.

12. The duty cycle correction device according to claim 11, wherein, The first variable driver includes: A first pull-up / pull-down driver circuit, which responds to the input clock signal to pull up or pull down the first output node; A second pull-up / pull-down driver circuit, which responds to the node level of the first output node by pulling up or pulling down the second output node to output the output clock signal through the second output node; and A slew rate control circuit corrects the duty cycle of the input clock signal by controlling the slew rate of the output clock signal based on the code value of the duty cycle control signal.

13. The duty cycle correction device according to claim 12, wherein, The conversion rate control circuit includes: A first slew rate control circuit corrects the duty cycle of the input clock signal by controlling the slew rate of the falling edge of the output clock signal based on the code value of the duty cycle control signal; and The second slew rate control circuit corrects the duty cycle of the input clock signal by controlling the slew rate of the rising edge of the output clock signal based on the code value of the duty cycle control signal.

14. The duty cycle correction device according to claim 13, in, The first conversion rate control circuit includes multiple PMOS transistor pairs. A code value from the duty cycle control signal and the input clock signal are respectively applied to the gate of each PMOS transistor pair. The multiple PMOS transistor pairs are connected in parallel between the power supply voltage terminal and the first output node. The second conversion rate control circuit includes multiple NMOS transistor pairs. One of the code values ​​of the duty cycle control signal and the input clock signal are respectively applied to the gate of the NMOS transistor pairs. The multiple NMOS transistor pairs are connected in parallel between the first output node and the ground voltage terminal.

15. The duty cycle correction device according to claim 11, wherein, The second variable driver recalibrates the duty cycle of the input clock signal by performing a pull-up / pull-down operation on the input clock signal based on the duty cycle resolution control signal to generate the output clock signal.

16. The duty cycle correction device according to claim 15, wherein, The second variable driver includes: A pair of PMOS transistors, wherein complementary signals of the input clock signal and the duty cycle resolution control signal are respectively applied to the gates of the PMOS transistor pair, and the PMOS transistor pair is connected in series between the power supply voltage terminal and the first output node; and The NMOS transistor pair, wherein the duty cycle resolution control signal and the input clock signal are respectively applied to the gate of the NMOS transistor pair, and the NMOS transistor pair is connected in series between the first output node and the ground voltage terminal.

17. A duty cycle correction method, the duty cycle correction method comprising the following steps: A duty cycle detection signal is generated by detecting the duty cycle of the output clock signal. The duty cycle of the input clock signal is corrected at a first resolution by changing the duty cycle control signal based on the duty cycle detection signal to generate the output clock signal. When the correction of the duty cycle of the input clock signal at the first resolution is completed at a timing earlier than the reference time, a duty cycle resolution control signal is generated. as well as Based on the duty cycle resolution control signal, the duty cycle of the input clock signal is recalibrated with a second resolution to generate the output clock signal.

18. The method according to claim 17, wherein, The step of correcting the input clock signal with the first resolution includes the following steps: generating the output clock signal by performing a pull-up / pull-down operation on the input clock signal based on the duty cycle control signal.

19. The method of claim 17, wherein, The steps for generating the duty cycle resolution control signal include the following: Count the input clock signal; and When the count value of the input clock signal is less than the threshold during the timing of generating the duty cycle correction completion signal, the duty cycle resolution control signal is generated.

20. The method of claim 17, wherein, The step of recalibrating the duty cycle includes the following steps: based on the duty cycle resolution control signal, the duty cycle of the input clock signal is recalibrated by performing a pull-up / pull-down operation on the input clock signal at a second resolution that is finer than the first resolution, in order to generate the output clock signal.

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