Method of manufacturing a semiconductor structure and semiconductor structure

Abstract

This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate, the substrate including an array region and a peripheral region surrounding the array region, the array region including an active region; forming a mask layer on the substrate; forming a contact hole pattern in a portion of the mask layer located in the array region; etching the substrate based on the contact hole pattern to form contact holes in the array region of the substrate, the contact holes exposing at least a portion of the active region; forming a first conductive layer in the contact holes, such that the first conductive layer is connected to the active region; forming a second conductive layer in both the peripheral region and the array region where the first conductive layer is formed in the contact holes; and removing the second conductive layer located in the array region to expose the first conductive layer. The method of this disclosure simplifies the fabrication process, reduces defects caused by the fabrication process to the semiconductor structure, improves the yield of the semiconductor structure, and reduces costs.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor fabrication technology, and in particular to a method for fabricating a semiconductor structure and a semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. It consists of many repeating memory cells and has storage functions. With the increasing demands on DRAM performance, the manufacturing process is complex and prone to defects, reducing yield and increasing cost.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure, which can simplify the fabrication process, reduce defects caused by the fabrication process to the semiconductor structure, improve the yield of the semiconductor structure, and reduce costs.

[0005] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including an array region and a peripheral region surrounding the array region, the array region including an active region; forming a mask layer on the substrate; forming a contact hole pattern on a portion of the mask layer located in the array region; etching the substrate based on the contact hole pattern to form contact holes in the array region of the substrate, the contact holes exposing at least a portion of the active region; forming a first conductive layer in the contact holes, such that the first conductive layer is connected to the active region; forming a second conductive layer on both the peripheral region and the array region on which the first conductive layer is formed in the contact holes; and removing the second conductive layer located in the array region to expose the first conductive layer.

[0006] According to some exemplary embodiments of the present disclosure, forming a contact hole pattern in the portion of the mask layer located in the array region includes: forming a photomask layer on the mask layer; forming the contact hole pattern in the portion of the photomask layer located in the array region; and transferring the contact hole pattern into the mask layer.

[0007] According to some exemplary embodiments of the present disclosure, forming a first conductive layer in the contact hole to connect the first conductive layer to the active region includes: forming a first conductive layer in the array region and the peripheral region, wherein the first conductive layer fills the contact hole; removing the first conductive layer located on the surfaces of the peripheral region and the array region, wherein the first conductive layer is retained in the contact hole.

[0008] According to some exemplary embodiments of this disclosure, after the first conductive layer is formed in the array region and the peripheral region, the method further includes: ion doping the first conductive layer using an ion implantation process.

[0009] According to some exemplary embodiments of this disclosure, the element doped in the first conductive layer is at least one of boron, phosphorus, arsenic and antimony.

[0010] According to some exemplary embodiments of this disclosure, the first conductive layer is made of doped polycrystalline silicon.

[0011] According to some exemplary embodiments of the present disclosure, removing the second conductive layer located in the array region to expose the first conductive layer includes: forming an etch barrier layer on the second conductive layer located in the peripheral region; removing the second conductive layer located in the array region; and removing the etch barrier layer to expose the second conductive layer located in the peripheral region.

[0012] According to some exemplary embodiments of the present disclosure, before forming a mask layer on the substrate, the method further includes forming an etch stop layer in the array region.

[0013] According to some exemplary embodiments of the present disclosure, before forming the mask layer on the substrate, the method further includes: forming a gate oxide layer on the etch stop layer and the peripheral region; forming the mask layer on the substrate includes forming the mask layer on the gate oxide layer.

[0014] According to some exemplary embodiments of the present disclosure, a second conductive layer is formed on both the peripheral region and the array region on which the first conductive layer is formed in the contact hole, including: forming a second conductive layer on the gate oxide layer; removing the second conductive layer located in the array region to expose the first conductive layer, including: using an etching process to remove the second conductive layer and the gate oxide layer located in the array region to expose the etch stop layer and the first conductive layer located in the contact hole.

[0015] According to some exemplary embodiments of this disclosure, the gate oxide layer is at least one of silicon oxide and silicon oxynitride.

[0016] According to some exemplary embodiments of this disclosure, the material of the second conductive layer is at least one of doped polycrystalline silicon, polycrystalline silicon, metal, and conductive metal oxide.

[0017] According to some exemplary embodiments of this disclosure, the material of the mask layer is at least one of polycrystalline silicon and carbon.

[0018] According to some exemplary embodiments of this disclosure, the first conductive layer located in the contact hole is a bit line contact or a capacitive contact; the second conductive layer located in the peripheral region is a gate.

[0019] This disclosure also provides a semiconductor structure prepared by the method described in any of the above embodiments.

[0020] As can be seen from the above technical solutions, the semiconductor structure preparation method and semiconductor structure of this disclosure have at least one of the following advantages and positive effects:

[0021] In this embodiment, a contact hole is formed first and a first conductive layer is formed in the contact hole, and then a second conductive layer is formed in the peripheral area. Compared with the conventional process of forming the second conductive layer first, multiple process steps are saved, the defects caused by multiple process steps to the semiconductor structure are reduced, the yield of the semiconductor is improved, and the cost of the semiconductor structure is reduced. Attached Figure Description

[0022] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0023] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure;

[0024] Figure 2 This is a schematic diagram illustrating the formation of a gate oxide layer on a substrate in a semiconductor structure according to some embodiments of this disclosure;

[0025] Figure 3 This is a schematic diagram illustrating the formation of a mask layer on a substrate, as shown in some embodiments of this disclosure;

[0026] Figure 4 This is a schematic diagram illustrating the formation of a photomask layer on a mask layer, as shown in some embodiments of this disclosure;

[0027] Figure 5 This is a schematic diagram illustrating the formation of contact holes in an array region according to some embodiments of this disclosure;

[0028] Figure 6 This is a schematic diagram illustrating the formation of a first conductive layer according to some embodiments of this disclosure;

[0029] Figure 7This is a schematic diagram illustrating the removal of a first conductive layer located on the surface of a substrate, as shown in some embodiments of this disclosure;

[0030] Figure 8 This is a schematic diagram illustrating the formation of a second conductive layer according to some embodiments of this disclosure;

[0031] Figure 9 This is a schematic diagram illustrating the formation of an etch barrier layer on a second conductive layer in the peripheral region, as shown in some embodiments of this disclosure;

[0032] Figure 10 This is a schematic diagram illustrating the removal of the second conductive layer, the gate oxide layer, and the etch barrier layer located in the peripheral region, as shown in some embodiments of this disclosure.

[0033] Explanation of reference numerals in the attached figures:

[0034] 1. Substrate; 2. Etch stop layer; 3. Gate oxide layer; 4. Mask layer; 5. Photomask layer; 6. First conductive layer; 7. Second conductive layer; 8. Etch stop layer; 9. Word line structure; 10. Shallow trench isolation; A. Array region; a. Active region; B. Peripheral region; S. Contact hole pattern; H. Contact hole. Detailed Implementation

[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0036] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0037] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0038] In addition, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0039] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor's gate is connected to the word line, its drain to the bit line, and its source to the capacitor. The voltage signal on the word line controls the transistor to turn on or off, thereby allowing data to be read from the capacitor via the bit line or written to the capacitor via the bit line for storage.

[0040] With technological advancements, the performance requirements for dynamic random access memory (DRAM) are increasing, while simultaneously, cost reduction is crucial to enhance market competitiveness. In traditional fabrication processes, especially in the front-end fabrication of DRAM, bit line contacts are typically formed in the array region before a conductive layer is formed in the peripheral region. Since the semiconductor structures of the array and peripheral regions differ, fabricating a layer in one region must minimize disruption to the already formed layers in the other. This makes the traditional process quite cumbersome. For example, conductive layers are formed on both the array and peripheral regions of the semiconductor substrate, followed by an oxide protective layer. Then, the conductive layer and oxide protective layer in the array region are removed. Contact holes are formed on the substrate in the array region, and bit line contacts are formed within these holes. Finally, the oxide protective layer on the conductive layer in the peripheral region is removed, exposing the conductive layer for connection to the peripheral circuitry. This process requires forming an oxide protective layer and then separately removing it from the peripheral region, making it complex and prone to defects due to the numerous steps involved, potentially affecting the already formed layer structures.

[0041] Based on this, embodiments of this disclosure provide a method for fabricating a semiconductor structure. For example... Figure 1 The diagram shows a flowchart of a preparation method according to an embodiment of this disclosure. Figures 2 to 10 Schematic diagrams of the semiconductor structure during the fabrication process are shown below. For example... Figure 1 As shown, the preparation method of this embodiment includes steps S110 to S170.

[0042] S110: Provides a substrate 1, which includes an array region A and a peripheral region B surrounding the array region A. The array region A includes an active region a.

[0043] like Figure 2 As shown, the substrate 1 includes a semiconductor substrate on which shallow trench isolation 10s are formed, with active regions a disposed between the shallow trench isolations 10s. The shallow trench isolations 10s are used for insulating isolation, and their material can be silicon nitride or silicon dioxide. The substrate 1 includes an array region A and a peripheral region B surrounding the array region A. The array region A is used to form the main devices of the semiconductor structure, such as transistors, capacitors, bit lines, word lines, etc., while the peripheral region B is used to form peripheral circuits.

[0044] In this embodiment of the disclosure, a buried word line structure 9 is provided in the semiconductor substrate, and the word line structure 9 is connected to the active region a. The word line structure 9 may include a high dielectric constant dielectric layer, a polysilicon layer, a work function layer, and a word line metal layer, etc.

[0045] In some embodiments, the semiconductor substrate can be made of silicon, silicon carbide, silicon-on-insulator, silicon-on-insulator, silicon-germanide-on-insulator, or germanium-on-insulator, etc. The semiconductor substrate can also be implanted with certain dopant particles to modify its electrical parameters according to design requirements.

[0046] S120: A mask layer 4 is formed on the substrate 1.

[0047] In some embodiments, such as Figure 3 As shown, a mask layer 4 can be formed on the substrate 1 using a deposition process. The mask layer 4 can be a hard mask layer, and the material of the mask layer 4 can be at least one of polycrystalline silicon and carbon.

[0048] In some embodiments, before forming the mask layer 4, such as Figure 1 As shown, the method further includes forming an etch stop layer 2 in the array region A. In this embodiment, after forming the embedded word line structure 9, an etch stop layer 2 is formed in the word line trench above the embedded word line structure 9 and on the surface of the substrate 1 using a deposition process. This allows the embedded word line structure 9 to be insulated and isolated, and serves as an etch stop in subsequent etching processes, preventing excessive etching from damaging the surface of the substrate 1. The etch stop layer 2 located in the peripheral region B is removed using an etching process, so that the etch stop layer 2 is formed only in the array region A.

[0049] In some embodiments, the material of the etch stop layer 2 may be silicon nitride or silicon oxynitride, without any special limitation.

[0050] In some embodiments, such as Figure 1As shown, before forming the mask layer 4 on the substrate 1, the method further includes forming a gate oxide layer 3 on the etch stop layer 2 and the peripheral region B; then forming the mask layer 4 on the substrate 1 includes forming the mask layer 4 on the gate oxide layer 3. Specifically, after forming the etch stop layer 2 in the array region A, the gate oxide layer 3 can be formed in the array region A and the peripheral region B of the substrate 1 using a deposition process, and then the mask layer 4 can be formed on the gate oxide layer 3. The gate oxide layer 3 mainly serves as the oxide layer for the gate subsequently formed in the peripheral region B.

[0051] In some embodiments, the gate oxide layer 3 is made of at least one of silicon oxide and silicon oxynitride. In some embodiments, the material of the gate oxide layer 3 is different from that of the etch stop layer 2. In subsequent processes, the gate oxide layer 3 located in array region A can be removed using an etching process. The two have different etch selectivity ratios, and the greater the difference in etch selectivity ratio between them, the better, provided that their respective performance requirements are met. Therefore, their materials can be different. For example, the gate oxide layer 3 is made of silicon dioxide, and the etch stop layer 2 is made of silicon nitride.

[0052] S130: A contact hole pattern S is formed in the portion of the mask layer 4 located in the array region A.

[0053] like Figure 4 As shown, a contact hole pattern S is formed in the portion of the mask layer 4 located in the array region A, which may include the following: A1 to A3.

[0054] A1: A photomask layer 5 is formed on the mask layer 4.

[0055] Specifically, the photomask layer 5 can be formed on the mask layer 4 of the array region A and the peripheral region B using a deposition process. In some embodiments, the photomask layer 5 can be a photoresist.

[0056] A2: A contact hole pattern S is formed in the portion of the photomask layer 5 located in the array region A.

[0057] In some embodiments, a contact hole pattern can be formed on the photomask layer 5 above the array region A, and then the contact hole pattern S can be transferred to the photomask layer 5 after exposure and development.

[0058] In some embodiments, the contact hole pattern S may be a bit line contact hole pattern or a capacitor contact hole pattern. Those skilled in the art can set the position, number, and shape of the contact hole pattern S according to the formation position of the bit line contact or capacitor contact.

[0059] A3: Transfer the contact hole pattern S to the mask layer 4.

[0060] Specifically, based on the contact hole pattern S of the photomask layer 5, the mask layer 4 can be etched using an etching process to transfer the contact hole pattern S into the mask layer 4, so as to form the contact hole H.

[0061] After the contact hole pattern S is formed in the mask layer 4, the photomask layer 5 can be removed by etching or chemical mechanical polishing (CMP).

[0062] The etching process can be either dry etching or wet etching. Dry etching can be plasma etching, where the etching gas can be chlorine. The degree of etching can be controlled by adjusting the amount of etching gas used. Wet etching can use concentrated sulfuric acid and hydrogen peroxide as etchants, and the degree of etching can be controlled by adjusting the concentration of the etchant or the etching time.

[0063] S140: Based on the contact hole pattern S, the substrate 1 is etched to form a contact hole H in the array region A of the substrate 1, and the contact hole H exposes at least part of the active region a.

[0064] like Figure 4 As shown, based on the contact hole pattern S of the mask layer 4, the array region A of the substrate 1 can be etched using an etching process to form contact holes H in the array region A of the substrate 1. The contact holes H expose at least a portion of the active region a.

[0065] After forming contact holes H in the substrate 1, the mask layer 4 can be removed by etching or chemical mechanical polishing to expose the gate oxide layer 3.

[0066] The etching process can be a wet etching process. When the mask layer 4 is a hard mask layer, especially when its material is polycrystalline silicon, the etchant used in the wet etching process can be a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). By controlling the concentration, amount, and etching time of the etchant, the mask layer 4 can be completely removed without damaging the gate oxide layer 3 located below the mask layer 4. Of course, those skilled in the art can make adjustments according to the actual situation, and no special limitations are made here.

[0067] S150: A first conductive layer 6 is formed in the contact hole H, so that the first conductive layer 6 is connected to the active region a.

[0068] In some embodiments, S150 may include the following: B1 to B2.

[0069] B1: A first conductive layer 6 is formed in the array region A and the peripheral region B, and the first conductive layer 6 fills the contact hole H.

[0070] A first conductive layer 6 can be deposited in the contact hole H and on the surface of the exposed gate oxide layer 3 using a deposition process. The first conductive layer 6 located in the contact hole H can be formed as a bit line contact or a capacitive contact. The first conductive layer 6 has good conductivity to enable electrical connection between the active region a and the bit line or capacitor.

[0071] In some embodiments, the first conductive layer 6 may be made of doped polycrystalline silicon to improve the conductivity of the first conductive layer 6.

[0072] In some embodiments, after the first conductive layer 6 is formed in the array region A and the peripheral region B, the method may further include: ion doping the first conductive layer 6 using an ion implantation process.

[0073] Ion implantation can be understood as a material modification process that introduces doped ions into a solid. During ion implantation, accelerated doped ions are implanted into a solid material in a vacuum system, thereby transforming the implanted region into a doped material. In this embodiment, when the first conductive layer 6 is not doped, the material of the first conductive layer 6 can be undoped polycrystalline silicon. By using the ion implantation process to implant ions into the first conductive layer 6, the undoped polycrystalline silicon is transformed into doped polycrystalline silicon, thereby improving the conductivity of the first conductive layer 6.

[0074] In some embodiments, the element doped in the first conductive layer 6 is at least one of boron, phosphorus, arsenic and antimony.

[0075] The first conductive layer 6 is doped with the aforementioned elements, which improves the conductivity of the first conductive layer 6, making the bit line contacts or capacitive contacts formed by the first conductive layer 6 have better conductivity and improving the electrical performance of the semiconductor structure.

[0076] B2: Remove the first conductive layer 6 located on the surface of the peripheral region B and the array region A, and retain the first conductive layer 6 in the contact hole H.

[0077] like Figure 7 As shown, the first conductive layer 6 located on the surface of the gate oxide layer 3 can be removed by etching or chemical mechanical polishing, exposing the gate oxide layer 3 and the first conductive layer 6 located in the contact hole H, so as to form bit line contact or capacitive contact in the contact hole H.

[0078] S160: A second conductive layer 7 is formed on the outer peripheral region B and the array region A on which the first conductive layer 6 is formed in the contact hole H.

[0079] like Figure 8As shown, S160 may include forming a second conductive layer 7 on the gate oxide layer 3. That is, after forming the first conductive layer 6 in the contact hole H, the second conductive layer 7 can be formed on the surface of the gate oxide layer 3 using a deposition process. The second conductive layer 7 is used to form the gate of the peripheral region B, so the second conductive layer 7 of the peripheral region B needs to be retained in the end, while the second conductive layer 7 located in the array region A is removed.

[0080] In some embodiments, the second conductive layer 7 is made of at least one of doped polysilicon, polysilicon, metal, and conductive metal oxide. Using the aforementioned materials, the second conductive layer 7 serves as the gate of the peripheral region B, exhibiting excellent conductivity.

[0081] S170: Remove the second conductive layer 7 located in array region A to expose the first conductive layer 6.

[0082] In some embodiments, S170 may include the following: C1 to C3.

[0083] C1: An etch barrier layer 8 is formed on the second conductive layer 7 located in the peripheral region B.

[0084] Specifically, such as Figure 9 As shown, an etch barrier layer 8 can be formed on the second conductive layer 7 located in the array region A and the peripheral region B using a deposition process. Then, the etch barrier layer 8 located in the array region A is removed, and the etch barrier layer 8 located in the peripheral region B is retained to cover the second conductive layer 7 located in the peripheral region B.

[0085] C2: Remove the second conductive layer 7 located in array region A.

[0086] In some embodiments, such as Figure 10As shown, specifically, an etching process is used to remove the second conductive layer 7 and the gate oxide layer 3 located in the array region A, exposing the etch stop layer 2 and the first conductive layer 6 located in the contact hole H. In some embodiments, the second conductive layer 7 can be removed first using a first etching process, in which the etchant can only etch the second conductive layer 7. Then, a second etching process is used to etch the gate oxide layer 3 located in the array region A down to the etch stop layer 2, in which the etchant can only etch the gate oxide layer 3. Through two etching processes, the second conductive layer 7 and the gate oxide layer 3 located in the array region A can be removed more thoroughly, ensuring the uniformity of the surface of the etch stop layer 2, so as to facilitate the formation of other layer structures in subsequent processes and reduce the formation of defects. In addition, the etching of the first conductive layer 6 located in the contact hole H can also be avoided, ensuring the integrity of the first conductive layer 6. In other embodiments, the second conductive layer 7 and the gate oxide layer 3 can be removed directly to the etch stop layer 2 using a single etching process, exposing the first conductive layer 6 located in the contact hole H. The etchant used in this single etching process can etch both the second conductive layer 7 and the gate oxide layer 3, thus simplifying the process and reducing costs.

[0087] Regardless of the etching method used, the materials of the etch stop layer 2 and the gate oxide layer 3 are different. For example, the etch stop layer 2 is made of silicon nitride, while the gate oxide layer 3 is made of silicon dioxide. The etchant selected for each layer has a different selectivity. Furthermore, the etching amount can be controlled by adjusting the amount of etchant and the etching time to avoid over-etching of the first conductive layer 6 in the contact hole H.

[0088] Since the second conductive layer 7 and the gate oxide layer 3 in array region A are removed by etching, the etch barrier layer 8 is not etched in the above etching process. Therefore, the material of the etch barrier layer 8 is different from that of the second conductive layer 7 and the gate oxide layer 3. That is, the etch selectivity of the etch barrier layer is different from that of the second conductive layer 7 and the gate oxide layer 3. In each etching process, the etchant has a greater etch selectivity for the second conductive layer 7 and the gate oxide layer 3. In one embodiment, the material of the second conductive layer 7 is polysilicon (undoped), the material of the gate oxide layer 3 is silicon dioxide, and the material of the etch barrier layer 8 is photoresist.

[0089] C3: Remove the etch barrier layer 8 to expose the second conductive layer 7 located in the peripheral region B.

[0090] In some embodiments, such as Figure 10 As shown, an etching process can be used to remove the etch barrier layer 8 to expose the second conductive layer 7 located in the peripheral region B. The exposed second conductive layer 7 can serve as the gate of the peripheral region B for connection with peripheral circuitry.

[0091] The etching process can be a dry etching process, such as plasma etching, which can directionally remove the etch barrier layer 8 located on the second conductive layer 7 without damaging other layer structures.

[0092] In some other embodiments, the specific implementation methods of S150 and S160 are different from those of S150 and S160 in the above embodiments.

[0093] S150: A first conductive layer 6 is formed in the contact hole H, connecting the first conductive layer 6 to the active region a. Specifically, S150 may include the following: D1 to D4.

[0094] D1: A first conductive layer 6 is formed in the array region A and the peripheral region B, and the first conductive layer 6 fills the contact hole H.

[0095] The first conductive layer 6 can be made of polycrystalline silicon, specifically undoped polycrystalline silicon. For example... Figure 6 As shown, a first conductive layer 6 can be deposited in the contact hole H and on the surface of the exposed gate oxide layer 3 using a deposition process.

[0096] D2: A hard mask layer is formed on the first conductive layer 6 located in the peripheral region B. The first conductive layer 6 and the gate oxide layer 3 located in the array region A are etched, leaving the first conductive layer 6 located in the contact hole H exposed. Specifically, a hard mask layer can be formed on the first conductive layer 6 located in the peripheral region B using a deposition process. When etching the first conductive layer 6 and the gate oxide layer 3 in the array region A, this hard mask layer is used to cover the first conductive layer 6 located in the peripheral region B, preventing the first conductive layer 6 from being etched.

[0097] D3: Ion doping of the first conductive layer 6 located in the contact hole H.

[0098] Specifically, the first conductive layer 6 located in the contact hole H can be doped using an ion implantation process, wherein the doping element can be at least one of boron, phosphorus, arsenic, and antimony. By doping the first conductive layer 6 located in the contact hole H, the conductivity of the first conductive layer 6 can be improved, giving the bit line contact or capacitive contact formed by the first conductive layer 6 better conductivity and improving the electrical performance of the semiconductor structure.

[0099] S160: A second conductive layer 7 is formed in the outer region B.

[0100] When the first conductive layer 6 located in the contact hole H is ion-doped, since the first conductive layer 6 located in the peripheral region B is covered by a hard mask layer, the first conductive layer 6 located in the peripheral region B is not doped, and its material is still undoped polycrystalline silicon.

[0101] The hard mask layer on the first conductive layer 6 located in the peripheral region B is removed to expose the first conductive layer 6, which is then formed as the second conductive layer 7 in this embodiment of the present disclosure.

[0102] Specifically, the hard mask layer on the first conductive layer 6 located in the peripheral region B can be removed using an etching process. Since this first conductive layer 6 is undoped polysilicon, it is used for connection to peripheral circuits, such as... Figure 10 As shown, for ease of distinction, the first conductive layer 6 can be referred to as the second conductive layer 7.

[0103] In the above embodiments, the second conductive layer 7 was not formed by a separate deposition process, thus saving process steps.

[0104] In some embodiments, the first conductive layer 6 located in the contact hole H is a bit line contact. The method of this disclosure embodiment further includes: forming a bit line structure (not shown in the figure), the bit line structure including a bit line metal layer and a bit line insulating layer, wherein the bit line metal layer can be made of at least one of tungsten, titanium, nickel, aluminum, and platinum, and the bit line metal layer is connected to the bit line contact to realize the conduction of the circuit. The bit line insulating layer can be made of silicon nitride and is disposed on the surface of the bit line metal layer.

[0105] In some embodiments, the first conductive layer 6 located in the contact hole H is a capacitive contact. The method of this disclosure embodiment further includes: forming a capacitor (not shown in the figure). Specifically, a stacked structure is formed on the substrate 1, which may be a silicon oxide layer and a silicon nitride layer alternately formed on the substrate 1. A capacitor hole is formed in the stacked structure. In the process of forming the capacitor hole, the silicon oxide layer may serve as a sacrificial layer and the silicon nitride layer may serve as a support layer. A lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially deposited in the capacitor hole. The capacitor includes the lower electrode layer, the dielectric layer, and the upper electrode layer. The lower electrode layer is connected to the capacitor contact to realize the conduction of the circuit. The lower electrode layer may be a columnar electrode or a cylindrical electrode. The materials of the lower electrode layer and the upper electrode layer may include at least one of metal nitride and metal silicide species, such as titanium nitride, titanium silicide, nickel silicide, etc. The dielectric layer can be a high-k dielectric layer to increase the capacitance value per unit area. The material of the dielectric layer can include at least one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, and AlOx. The dielectric layer can also include multiple layers of different materials stacked together, without any special limitation here.

[0106] The deposition processes used in the embodiments of this disclosure can be chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and no special limitation is made here.

[0107] In traditional semiconductor fabrication processes, a second conductive layer 7 is first formed, followed by an oxide protective layer. Throughout the entire process, the oxide protective layer remains on the second conductive layer 7 until it needs to be removed separately at the end of the process. However, the fabrication method of this disclosure first forms a contact hole H in the substrate 1, and then forms a first conductive layer 6 within the contact hole H. Subsequently, the second conductive layer 7 is formed in the peripheral region B. Throughout the entire process, no oxide protective layer is formed as in traditional processes to protect the second conductive layer 7. Therefore, there is no need for a separate process to remove the oxide protective layer. Compared to traditional techniques, the fabrication method of this disclosure saves multiple process steps, reduces defects caused by these steps to the semiconductor structure, improves semiconductor yield, and lowers costs.

[0108] The embodiments of this disclosure also provide a semiconductor structure, which is prepared by the preparation method in any of the above embodiments, and the specific preparation process will not be described in detail here.

[0109] In some embodiments, the semiconductor structure includes a substrate 1, which includes an array region A and a peripheral region B surrounding the array region A. The semiconductor structure also includes an embedded word line structure 9, bit line contacts, and bit lines. The bit line contact is a first conductive layer 6 in the fabrication method embodiment, located in the substrate 1, and the bit line is located on the substrate 1 and connected to the bit line contact.

[0110] In some embodiments, the semiconductor structure further includes a capacitor and a capacitor contact. The capacitor contact is located in the substrate 1 and is the first conductive layer 6 in the fabrication method embodiment. The capacitor is located on the substrate 1 and includes a lower electrode layer, a dielectric layer, and an upper electrode layer, wherein the lower electrode layer is connected to the capacitor contact.

[0111] The semiconductor structure of this disclosure, prepared by the above-described method, reduces manufacturing costs and improves the yield of the semiconductor structure.

[0112] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to adopt this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region and a peripheral region surrounding the array region, the array region including an active region; An etch stop layer is formed in the array region, and a gate oxide layer is formed on the etch stop layer and in the peripheral region. The etch stop layer is made of silicon nitride or silicon oxynitride, and the gate oxide layer is made of silicon oxide. A mask layer is formed on the substrate; A contact hole pattern is formed in the portion of the mask layer located in the array region; The substrate is etched based on the contact hole pattern to form contact holes in the array region of the substrate. The contact holes penetrate the gate oxide layer and the etch stop layer and expose at least a portion of the active region. The mask layer is removed using a wet etching process; A first conductive layer is formed in the array region and the peripheral region, and the first conductive layer fills the contact hole; The first conductive layer located on the surface of the peripheral area and the array area is removed by an etching process, leaving the first conductive layer only in the contact hole; A second conductive layer is formed on both the peripheral region and the array region on which the first conductive layer is formed in the contact hole; The second conductive layer, the gate oxide layer, and the etch stop layer located in the array region are removed in sequence to expose the first conductive layer located in the contact hole.

2. The method according to claim 1, characterized in that, A contact hole pattern is formed in the portion of the mask layer located in the array region, including: A photomask layer is formed on the mask layer; The contact hole pattern is formed in the portion of the photomask layer located in the array region; The contact hole pattern is transferred into the mask layer.

3. The method according to claim 1, characterized in that, After the first conductive layer is formed in the array region and the peripheral region, the method further includes: The first conductive layer is ion-doped using an ion implantation process.

4. The method according to claim 3, characterized in that, The element doped into the first conductive layer is at least one of boron, phosphorus, arsenic and antimony.

5. The method according to claim 1, characterized in that, The first conductive layer is made of doped polycrystalline silicon.

6. The method according to claim 1, characterized in that, Removing the second conductive layer, gate oxide layer, and etch stop layer located in the array region to expose the first conductive layer located in the contact hole includes: An etch barrier layer is formed on the second conductive layer located in the peripheral region; Remove the second conductive layer, the gate oxide layer, and the etch stop layer located in the array region; Remove the etch barrier layer to expose the second conductive layer located in the peripheral area.

7. The method according to claim 1, characterized in that, The material of the second conductive layer is at least one of doped polycrystalline silicon, polycrystalline silicon, metal, and conductive metal oxide.

8. The method according to claim 1, characterized in that, The mask layer is made of at least one of polycrystalline silicon and carbon.

9. The method according to any one of claims 1 to 8, characterized in that, The first conductive layer located in the contact hole is a bit line contact or a capacitive contact; The second conductive layer located in the peripheral region is a gate.

10. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method of any one of claims 1 to 9.

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