Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

Embodiments of the present disclosure disclose a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of the semiconductor structure includes: providing a substrate, the substrate including a stacked structure and a lower electrode hole penetrating the stacked structure; forming a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer in the lower electrode hole, the first lower electrode layer covering the inner surface of the lower electrode hole, the second lower electrode layer covering the surface of the first lower electrode layer, the third lower electrode layer covering the surface of the second lower electrode layer, and the first lower electrode layer, the second lower electrode layer, and the third lower electrode layer being defined as a lower electrode layer; wherein, the strength of the second lower electrode layer is greater than the strength of the first lower electrode layer and the third lower electrode layer. In the manufacturing method provided by the present disclosure, a lower electrode layer composed of the first lower electrode layer, the second lower electrode layer with high strength, and the third lower electrode layer is formed, and the overall strength of the lower electrode layer is relatively high, which can improve the problem that the capacitor column is prone to bending or tilting due to insufficient strength of a single-layer electrode plate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a manufacturing method of a semiconductor structure and a semiconductor structure. Background Art

[0002] Dynamic random access memory (DRAM) is a commonly used semiconductor structure in electronic devices, which includes a plurality of memory cells, and each memory cell includes a transistor and a capacitor. As the feature size of DRAM continues to shrink, the capacitance of the capacitor is usually increased by increasing the height of the capacitor column, thereby improving the storage density. However, the capacitor column with a high aspect ratio is prone to problems such as instability of the capacitor column, which may cause poor capacitance performance or even capacitor failure. Therefore, how to form a stable and reliable columnar capacitor structure has become a technical problem to be solved urgently at present. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a manufacturing method of a semiconductor structure and a semiconductor structure to solve or improve the technical problems existing in the background art.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a manufacturing method of a semiconductor structure, including:

[0005] Providing a substrate, where the substrate includes a stacked structure and a lower electrode hole penetrating the stacked structure;

[0006] Forming a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer in the lower electrode hole, where the first lower electrode layer covers the inner surface of the lower electrode hole, the second lower electrode layer covers the surface of the first lower electrode layer, the third lower electrode layer covers the surface of the second lower electrode layer, and the first lower electrode layer, the second lower electrode layer, and the third lower electrode layer are defined as the lower electrode layer; wherein,

[0007] The strength of the second lower electrode layer is greater than the strength of the first lower electrode layer and the third lower electrode layer.

[0008] In some embodiments, forming the first lower electrode layer and the second lower electrode layer includes:

[0009] Performing a first process cycle a first predetermined number of times to prepare the first lower electrode layer; performing a second process cycle a second predetermined number of times to prepare the second lower electrode layer; wherein, the ratio range of the first predetermined number to the second predetermined number is 40 to 50.

[0010] In some embodiments, the first process cycle includes:

[0011] Introduce a first gas and continue for a first duration; continue to introduce the first gas for purging, lasting for a second duration; introduce a second gas for deposition reaction, lasting for a third duration; continue to introduce the second gas for purging, lasting for a fourth duration.

[0012] In some embodiments, the second process cycle includes:

[0013] Introduce a third gas and continue for a fifth duration; continue to introduce the third gas for purging, lasting for a sixth duration; introduce a fourth gas for deposition reaction, lasting for a seventh duration; continue to introduce the fourth gas for purging, lasting for an eighth duration.

[0014] In some embodiments, the first lower electrode layer, the second lower electrode layer, and / or the third lower electrode layer are formed at a temperature of 580°C to 620°C.

[0015] In some embodiments, providing a substrate includes:

[0016] Form the stacked structure on the substrate, the stacked structure at least includes a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer;

[0017] Etch the stacked structure in a direction perpendicular to the substrate plane to expose the substrate to form the lower electrode hole.

[0018] In some embodiments, after forming the lower electrode layer, the method further includes:

[0019] Form a first mask layer and pattern the first mask layer to expose part of the third support layer and the lower electrode layer;

[0020] Etch the third support layer to form a first window;

[0021] Remove the second sacrificial layer through the first window;

[0022] Etch the second support layer to form a second window;

[0023] Remove the first sacrificial layer through the second window.

[0024] In some embodiments, after removing the first sacrificial layer, the method further includes:

[0025] Form a dielectric layer that at least covers the surface of the lower electrode layer;

[0026] Form an upper electrode layer that covers the surface of the dielectric layer.

[0027] According to a second aspect of the embodiments of the present disclosure, there is provided a semiconductor structure, including:

[0028] Substrate;

[0029] A support structure located above the substrate, the support structure including a lower electrode hole penetrating the support structure;

[0030] A lower electrode layer located within the lower electrode hole, wherein the lower electrode layer includes a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer. The first lower electrode layer covers the inner surface of the lower electrode hole, the second lower electrode layer covers the surface of the first lower electrode layer, and the third lower electrode layer covers the surface of the second lower electrode layer; wherein, the strength of the second lower electrode layer is greater than the strength of the first lower electrode layer and the third lower electrode layer.

[0031] In some embodiments, the ratio of the thickness of the first lower electrode layer to the thickness of the second lower electrode layer ranges from 80 to 250.

[0032] In some embodiments, the materials of the first lower electrode layer and the third lower electrode layer include titanium nitride, and the material of the second lower electrode layer includes silicon nitride.

[0033] In some embodiments, the third lower electrode layer includes a first sub - part and a second sub - part. Along the direction parallel to the substrate plane, the size of the second sub - part is larger than the size of the first sub - part, and the second sub - part covers the upper surfaces of the first sub - part and the second lower electrode layer.

[0034] In some embodiments, the first lower electrode layer covering the inner surface of the lower electrode hole forms a first cavity, the second lower electrode layer only covers the side wall of the first cavity and forms a second cavity, and the third lower electrode layer fills the second cavity.

[0035] In some embodiments, the semiconductor structure further includes:

[0036] A dielectric layer covering the lower electrode layer and the surface of the support structure and an upper electrode layer covering the surface of the dielectric layer.

[0037] In some embodiments, there is a gap between the upper electrode layers, and the semiconductor structure further includes:

[0038] A conductive connection layer, the conductive connection layer filling the gap and covering the top of the upper electrode layer.

[0039] Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate, where the substrate includes a stacked structure and a lower electrode hole penetrating the stacked structure; forming a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer in the lower electrode hole, where the first lower electrode layer covers the inner surface of the lower electrode hole, the second lower electrode layer covers the surface of the first lower electrode layer, the third lower electrode layer covers the surface of the second lower electrode layer, and the first lower electrode layer, the second lower electrode layer, and the third lower electrode layer are defined as the lower electrode layer; wherein, the strength of the second lower electrode layer is greater than the strength of the first lower electrode layer and the third lower electrode layer. In the present disclosure, first, a substrate is provided, where the substrate includes a stacked structure and a lower electrode hole penetrating the stacked structure, and then a first lower electrode layer covering the inner surface of the lower electrode hole, a second lower electrode layer covering the surface of the first lower electrode layer, and a third lower electrode layer covering the surface of the second lower electrode layer are formed in the lower electrode hole. Since the first lower electrode layer, the second lower electrode layer, and the third lower electrode layer together constitute the lower electrode layer, and the strength of the second lower electrode layer is greater than the strength of the first lower electrode layer and the third lower electrode layer, it is possible to effectively improve the problem that the capacitor column is prone to bending or tilting due to insufficient strength of a single-layer lower electrode plate. In the embodiments of the present disclosure, the second lower electrode layer with high strength is compounded in the first lower electrode layer and the third lower electrode layer, which can enhance the strength of the entire lower electrode layer, and further effectively resist the deformation caused by stress, so that the stability of the capacitor column in the process is enhanced, and it is possible to improve the problem that the etching opening is skewed due to the bending or tilting of the capacitor column, resulting in the inability to normally open the support layer, so that the bottom oxide layer cannot be fully removed, and sufficient space cannot be reserved for the upper electrode layer, thereby causing the failure of the entire capacitor.

[0040] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

[0042] Figures 2a to 2k is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure during manufacturing;

[0043] Figure 3 is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0044] Figure 4 is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present disclosure;

[0045] Figure 5 is a cross-sectional schematic diagram of a semiconductor structure according to another embodiment of the present disclosure;

[0046] Figure 6 A cross-sectional schematic view of a semiconductor structure according to another embodiment of the present disclosure.

[0047] Reference numerals:

[0048] 10 - Substrate; 100 - Base; 101 - Capacitor contact pad; 102 - Dielectric layer; 11 - Stacked structure; 111 - First support layer; 112 - First sacrificial layer; 113 - Second support layer; 114 - Second sacrificial layer; 115 - Third support layer; 12 - Lower electrode hole; 13 - First lower electrode layer; 131 - First lower electrode material layer; 14 - Second lower electrode layer; 141 - Second lower electrode material layer; 15 - Third lower electrode layer; 151 - Third lower electrode material layer; 16 - Lower electrode layer; 17 - First mask layer; 18 - First window; 19 - Second window; 20 - Patterned photoresist layer; 21 - Dielectric layer; 22 - Upper electrode layer; 23 - Conductive connection layer; 24 - Support structure; 25 - First sub - part; 26 - Second sub - part; 27 - First cavity; 28 - Second cavity; 29 - Gap. Detailed implementation manners

[0049] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific implementation manners set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0050] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, to avoid confusion with the present disclosure, some well - known technical features are not described; that is, not all features of the actual embodiments are described here, and the well - known functions and structures are not described in detail.

[0051] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0052] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present disclosure. And when discussing a second element, component, region, layer or portion, it does not imply that a first element, component, region, layer or portion necessarily exists in the present disclosure.

[0053] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0054] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0055] As the feature size of dynamic random access memory (DRAM) continues to shrink, the capacitance of the capacitor is usually increased by increasing the height of the capacitor column, thereby improving the storage density. However, forming a capacitor column with a high aspect ratio will face problems such as structural instability. For example, the strength of the lower electrode layer is not high enough to effectively resist the deformation caused by stress, resulting in problems such as bending or tilting of the capacitor column, which causes the critical dimensions to change, resulting in the inability to normally open the support layer in the subsequent capacitor manufacturing process. Therefore, the lower oxide layer cannot be fully removed, resulting in insufficient space reserved for the upper electrode layer of the capacitor, and finally leading to the problem of capacitor failure.

[0056] Based on this, the present disclosure provides a method for manufacturing a semiconductor structure. For details, please refer to the attached Figure 1 , as shown in the figure, the method includes:

[0057] Step 101: Provide a substrate, the substrate includes a stacked structure and a lower electrode hole penetrating the stacked structure;

[0058] Step 102: Form a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer in the lower electrode hole. The first lower electrode layer covers the inner surface of the lower electrode hole, the second lower electrode layer covers the surface of the first lower electrode layer, and the third lower electrode layer covers the surface of the second lower electrode layer. The first lower electrode layer, the second lower electrode layer, and the third lower electrode layer are defined as the lower electrode layer; wherein, the strength of the second lower electrode layer is greater than the strength of the first lower electrode layer and the third lower electrode layer.

[0059] The following further elaborates on the method for manufacturing a semiconductor structure provided by the present disclosure in conjunction with specific embodiments.

[0060] First, execute step 101. Refer to the attached Figure 2b , provide a substrate 10, the substrate 10 includes a stacked structure 11 and a lower electrode hole 12 penetrating the stacked structure 11.

[0061] Here, provide a substrate 10. Refer to the attached Figure 2a and the attached Figure 2b , including: forming a stacked structure 11 on a substrate 100, the stacked structure 11 at least includes a first support layer 111, a first sacrificial layer 112, a second support layer 113, a second sacrificial layer 114, and a third support layer 115 (refer to the attached Figure 2a ); etch the stacked structure 11 in a direction perpendicular to the plane of the substrate 100 to expose the substrate 100 to form a lower electrode hole 12 (refer to the attached Figure 2b ).

[0062] The above-mentioned stacked structure 11 can better support the formed capacitor structure while ensuring the height of the formed capacitor.

[0063] In some embodiments, the substrate 100 includes, for example, but is not limited to, a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon-germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In some specific embodiments, referring to the attached Figure 2a , the substrate 100 includes a doped or undoped silicon substrate. The substrate 100 includes a plurality of capacitive contact pads 101, and a dielectric layer 102 is filled between the capacitive contact pads 101. The plurality of capacitive contact pads 101 may be arranged in a hexagonal array in the substrate 100. In some other embodiments, the plurality of capacitive contact pads 101 may also adopt other array arrangement manners, which are not specifically limited herein. The material of the capacitive contact pad 101 may include a conductive material, for example, any combination of one or more of the metal materials tungsten, copper, aluminum, titanium, tantalum, silver, tantalum nitride, and titanium nitride. The material of the dielectric layer may include an insulating material, such as an oxide, a nitride, or a nitrogen oxide, etc. The stacked structure 11 may be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes. The anisotropic etching process, such as a plasma etching process, may be used to etch the stacked structure 11 to form the lower electrode hole 12. The materials of the first support layer 111, the second support layer 113, and the third support layer 115 include, but are not limited to, nitrides. The materials of the first sacrificial layer and the second sacrificial layer include, but are not limited to, oxides. In some specific embodiments, the materials of the second support layer 113 and the third support layer 115 may include a C-containing insulating material, such as SiCN. Since the SiCN material has good hardness, it can provide good support for the capacitor formed subsequently. The materials of the first support layer 111 and the first sacrificial layer 112 may include a B-containing insulating material. For example, the material of the first support layer 111 may be SiBN, and the material of the first sacrificial layer 112 may be borophosphosilicate glass (BPSG). Since both the first sacrificial layer 112 and the first support layer 111 use materials doped with boron element, the hardness of the materials is reduced, so that the etching process is easier to complete, and the morphology of the lower electrode hole 12 can be ensured.

[0064] It can be understood that the types and numbers of the film layers included in the above stacked structure 11 may change with the change of the capacitor height. The stacked structure 11 in the above embodiments is only taken as an example and is not a specific limitation.

[0065] Next, step 102 is executed. Referring to the attached Figure 2j, a first lower electrode layer 13, a second lower electrode layer 14, and a third lower electrode layer 15 are formed within the lower electrode hole 12. The first lower electrode layer 13 covers the inner surface of the lower electrode hole 12, the second lower electrode layer 14 covers the surface of the first lower electrode layer 13, and the third lower electrode layer 15 covers the surface of the second lower electrode layer 14. The first lower electrode layer 13, the second lower electrode layer 14, and the third lower electrode layer 15 are defined as the lower electrode layer 16. Among them, the strength of the second lower electrode layer 14 is greater than the strength of the first lower electrode layer 13 and the third lower electrode layer 15.

[0066] Since the first lower electrode layer 13, the second lower electrode layer 14, and the third lower electrode layer 15 together constitute the lower electrode layer 16, and the strength of the second lower electrode layer 14 is greater than the strength of the first lower electrode layer 13 and the third lower electrode layer 15, it is possible to effectively improve the problem that the capacitor column is prone to bending or tilting due to the insufficient strength of the single-layer lower electrode plate.

[0067] In some embodiments, referring to the attached Figure 2c and the attached Figure 2d , forming the first lower electrode layer 13 and the second lower electrode layer 14 includes: performing a first process cycle a first predetermined number of times to prepare the first lower electrode layer 13; performing a second process cycle a second predetermined number of times to prepare the second lower electrode layer 14.

[0068] The first lower electrode layer 13 and the second lower electrode layer 14 are formed by using the first process cycle and the second process cycle to form a physical composite film layer. Among them, the first lower electrode layer 13 has good electrical properties and mainly functions as the electrode plate of the capacitor. The second lower electrode layer 14 has higher strength and mainly plays a supporting role to improve the overall strength of the composite film layer. When the ratio of the first predetermined number to the second predetermined number is relatively large, the proportion of the thickness of the first lower electrode layer 13 is relatively large, while the proportion of the thickness of the second lower electrode layer 14 is relatively small, which will cause the strength of the composite film layer to fail to reach the expected level and have limited effect on improving the bending or tilting of the capacitor column. When the ratio of the first predetermined number to the second predetermined number is relatively small, the proportion of the thickness of the second lower electrode layer 14 is relatively large, while the proportion of the thickness of the first lower electrode layer 13 is relatively small, which will cause the resistance of the composite film layer to increase and the electrical properties to decrease, thereby affecting the performance of the capacitor to a certain extent. Therefore, in some specific embodiments, the ratio range of the first predetermined number to the second predetermined number can be 40 to 50, including the end point values. For example, it can be 42, 45, 47, or 49. This will enable the strength and electrical properties of the composite film layer formed by the first lower electrode layer 13 and the second lower electrode layer 14 to reach the expected level, and can achieve the beneficial effect of better improving the bending or tilting of the capacitor column while taking into account the performance of the capacitor.

[0069] Specifically, the first process cycle includes: introducing a first gas and maintaining it for a first duration; continuing to introduce the first gas for purging, maintaining it for a second duration; introducing a second gas for deposition reaction, maintaining it for a third duration; continuing to introduce the second gas for purging, maintaining it for a fourth duration.

[0070] The second process cycle includes: introducing a third gas and maintaining it for a fifth duration; continuing to introduce the third gas for purging, maintaining it for a sixth duration; introducing a fourth gas for deposition reaction, maintaining it for a seventh duration; continuing to introduce the fourth gas for purging, maintaining it for an eighth duration.

[0071] In some embodiments, the first process and the second process can be one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes, preferably the atomic layer deposition (ALD) process. During the deposition process, different reaction conditions, such as the type of reaction gas, the flow rate of the introduced reaction gas, the time of introducing the reaction gas and the purging time, as well as the reaction temperature, etc., will all affect the quality, thickness, or shape of the formed film layer. In some specific embodiments, refer to the appendix Figure 2c to the appendix Figure 2e , first, perform the first process cycle for a first predetermined number of times. The first predetermined number can be, for example, 200. Among them, the first gas can be titanium tetrachloride, the flow rate of the introduced first gas can be 140 sccm, the second gas can be ammonia, the flow rate of the introduced second gas can be 1800 sccm, the first duration can be 0.05 s, the second duration can be 0.2 s, the third duration can be 0.3 s, and the fourth duration can be 0.3 s to form a first lower electrode material layer 131 covering the inner surface of the lower electrode hole 12 and the top of the third support layer 115 (refer to the appendix Figure 2c ), and the material of the first lower electrode material layer is titanium nitride; then, for example, adopt a chemical mechanical polishing process (CMP) to remove the first lower electrode material layer 131 located on the top of the third support layer 115 to form a first lower electrode layer 13 located on the inner surface of the lower electrode hole 12 (refer to the appendix Figure 2d ). Next, perform the second process cycle for a second predetermined number of times. The second predetermined number can be, for example, 5. Among them, the third gas can be dichlorosilane, the flow rate of the introduced third gas can be 100 sccm, the fourth gas can be ammonia, the flow rate of the introduced fourth gas can be 1800 sccm, the fifth duration can be 6.95 s, the sixth duration can be 0.2 s, the seventh duration can be 0.3 s, and the eighth duration can be 0.3 s to form a second lower electrode material layer 141 covering the first lower electrode layer 13 and the top of the third support layer 115 (refer to the appendix Figure 2d), the material of the second lower electrode material layer 141 is silicon nitride; then, for example, a chemical mechanical polishing process (CMP) is used to remove the second lower electrode material layer 141 located on the top of the third support layer 115 and the first lower electrode layer 13, forming the second electrode layer 14 (see the appendix Figure 2e ).

[0072] In some embodiments, the first lower electrode layer and the second lower electrode layer are formed at a temperature of 580 °C to 620 °C. The temperature range of the deposition process is 580 °C to 620 °C, including the end values. For example, it can be 590 °C, 600 °C, 605 °C or 610 °C. By using the atomic layer deposition (ALD) process and controlling the conditions of the deposition reaction according to the above parameters, a film layer with high density, good thickness controllability and uniformity can be formed, and the bonding degree between the first lower electrode layer 13 and the second lower electrode layer 14 is good. For example, under the above reaction conditions, the thickness of the first lower electrode layer 13 formed by a single first process cycle deposition is about 0.08 nm to 0.1 nm, and the thickness of the second lower electrode layer 14 formed by a single second process cycle deposition is about 0.02 nm to 0.04 nm.

[0073] In some embodiments, see the appendix Figure 2e, one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes can be used to form the third lower electrode material layer 151. The third lower electrode material layer 151 covers the surface of the second lower electrode layer 14 and the tops of the first lower electrode layer 13 and the third support layer 115. The material of the third lower electrode material layer 151 can include titanium nitride. The process for forming the third lower electrode material layer 151 can be different from the process for forming the first lower electrode material layer 131. In some specific embodiments, a deposition method and deposition parameters consistent with the first process can be used to form the third lower electrode material layer 151 at a temperature of 580 °C to 620 °C. The temperature range of the deposition process is 580 °C to 620 °C, including the endpoint values. For example, it can be 590 °C, 600 °C, 605 °C, or 610 °C. The resulting third lower electrode material layer 151 has high density, good uniformity, and good bonding with the second lower electrode layer 14, which will result in excellent electrical properties and high strength of the entire lower electrode layer 16. In addition, since the third lower electrode material layer 151 not only fills the lower electrode holes 12 but also covers the tops of the first lower electrode layer 13, the second lower electrode layer 14, and the third support layer 115, the stability of the entire lower electrode layer 16 can be enhanced. During the subsequent etching process to form the window, misalignment caused by bending or tilting of the lower electrode layer 16 can be avoided or improved, preventing the failure of forming the second window 19. Therefore, the problem that the etching solution is difficult to fully contact the first sacrificial layer 112 in the subsequent wet etching process due to the failure of forming the second window 19 is avoided, and further, the problem of capacitor fabrication failure caused by the incomplete removal of the first sacrificial layer 112 is avoided.

[0074] In the above embodiments, the first lower electrode layer 13, the second lower electrode layer 14, and the third lower electrode material layer 151 located in the lower electrode holes 12 together constitute the lower electrode layer 16, as shown in the attached Figure 2eAs shown in the dashed box, the horizontal cross-section of the columnar body of the capacitive lower electrode layer 16 is circular. In other embodiments, the horizontal cross-section of the columnar body of the capacitive lower electrode layer 16 may also be other shapes, such as oval or polygonal, etc., which are not specifically limited herein. It can be understood that the first lower electrode layer 13, the second lower electrode layer 14, and the third lower electrode material layer 151 fabricated according to the method in the above embodiments can be used as other functional elements that have requirements for both strength and resistance in addition to capacitive use, such as contact plugs, etc. In addition, the positions and shapes of the first lower electrode layer 13, the second lower electrode layer 14, and the third lower electrode material layer 151 are not specifically limited either. They can also be fabricated into a tiled film layer, and the jointly formed planar composite film layer has excellent strength and electrical properties and can be used as a contact pad, etc. The above are only examples rather than limitations of the uses of the composite film layer. The lower electrode layer 16 and its deformations in the above embodiments can be used in any other components that have requirements for strength and electrical properties.

[0075] In some embodiments, referring to the attached Figure 2f to the attached Figure 2k , after forming the third lower electrode material layer 151, it further includes: forming a first mask layer 17 (refer to the attached Figure 2f ), patterning the first mask layer 17 to expose a part of the third support layer 115 and the lower electrode layer 16 (refer to the attached Figure 2g ); etching the third support layer 115 to form a first window 18 (refer to the attached Figure 2h ); removing the second sacrificial layer 114 through the first window 18 (refer to the attached Figure 2i ); etching the second support layer 113 to form a second window 19 (refer to the attached Figure 2j ); removing the first sacrificial layer 112 through the second window 19 (refer to the attached Figure 2k ).

[0076] In some embodiments, first, one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes can be used to deposit and form the first mask layer 17, where the material of the mask layer 17 may include but is not limited to silicon oxynitride, polysilicon, amorphous carbon layer, or oxide, etc.; then, a patterned photoresist layer 20 can be used to transfer the pattern to the first mask layer 17 to form the patterned first mask layer 17, and then the third lower electrode material layer 151 is etched. For example, a plasma etching process can be used, and through etching agents Cl2 and NF3, the third support layer 115 and a part of the lower electrode layer 16 are exposed. In some specific embodiments, such as Figure 2gAs shown, after the above-mentioned etching process exposes the third support layer 115, the upper surface of the first lower electrode layer 13 and / or the second lower electrode layer 14 is flush with the upper surface of the third support layer 115. It should be understood that in some other embodiments, the upper surface of the first lower electrode layer 13 and / or the second lower electrode layer 14 may not be flush with the upper surface of the third support layer 115, and it is only necessary to expose the third support layer 115. The third support layer 115 and the second support layer 113 can be etched by, for example, a plasma etching process using an etching agent CF4 gas, and the etching depth is aimed at exposing the second sacrificial layer 114 through the first window 18 and exposing the first sacrificial layer 112 through the second window 19. As Figure 2j As shown, the second window 19 is etched and formed, and the third lower electrode material layer 151 located on the top of the third support layer 115 is removed. The remaining third lower electrode material layer 151 is the third lower electrode layer 15. The methods for removing the first sacrificial layer 112 and the second sacrificial layer 114 include, but are not limited to, using a diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F) for wet etching to selectively etch and remove the materials of the first sacrificial layer 112 and the second sacrificial layer 114, and retaining the first lower electrode layer 13, the second lower electrode layer 14, the first support layer 111, the second support layer 113, and the third support layer 115. Specifically, the first sacrificial layer 112 and the second sacrificial layer 114 are etched sequentially. First, the second sacrificial layer 114 is etched, and then the first sacrificial layer 112 is etched.

[0077] Since the lower electrode layer 16 includes three sub-layers: the first lower electrode layer 13, the second lower electrode layer 14, and the third lower electrode layer 15, and the strength of the second lower electrode layer 14 is higher than that of the first lower electrode layer 13 and the third lower electrode layer 15, this makes the strength of the lower electrode layer 16 relatively high. As a result, during the etching process, the lower electrode layer 16 is not easily bent, deformed, or even collapsed, which may cause problems such as the opening being squeezed, reduced, or even closed. Therefore, the sacrificial layer can be removed more thoroughly and it is not easy to generate residues, which may lead to capacitor failure. In addition, the top of the third lower electrode material layer 151 can also act as a partial mask layer and play a role in protecting the surfaces of the third support layer 115, the first lower electrode layer 13, and the second lower electrode layer 14 during the etching process, thereby ensuring the support effect of the third support layer 115 and the performance of the capacitor.

[0078] In some specific embodiments, the first sacrificial layer 112 and the second sacrificial layer 114 have a high etching selectivity with respect to the first lower electrode layer 13 and the third lower electrode material layer 151.

[0079] In the above embodiments, a window is formed in the support layer to remove the first sacrificial layer 112 and the second sacrificial layer 114, facilitating the subsequent process of fabricating the capacitor. The first sacrificial layer 112 and the second sacrificial layer 114 have a high etching selectivity with respect to the first lower electrode layer 13 and the third lower electrode material layer 151, such that when the first sacrificial layer 112 and the second sacrificial layer 114 are removed by wet etching, the first lower electrode layer 13 and the third lower electrode material layer 151 are substantially unaffected, and thus the performance of the capacitor is not affected.

[0080] In some embodiments, after removing the first sacrificial layer 112, referring to the attached Figure 3 , it further includes: forming a dielectric layer 21 that at least covers the surface of the lower electrode layer 16; forming an upper electrode layer 22 that covers the surface of the dielectric layer 21.

[0081] The lower electrode layer 16, the dielectric layer 21 covering the surface of the lower electrode layer 16, and the upper electrode layer 22 covering the surface of the dielectric layer 21 constitute a complete capacitor.

[0082] In some embodiments, one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes can be used to form the dielectric layer 21 and the upper electrode layer 22. In some specific embodiments, a diffusion deposition process can be used to form the dielectric layer 21, and an atomic layer deposition (ALD) process can be used to form the upper electrode layer 22. Among them, the dielectric layer 21 includes a high dielectric constant material, such as, including but not limited to, alumina, silicon nitride, silicon oxide, zirconium oxide, hafnium oxide, or a combination thereof, etc. The material of the upper electrode layer 22 can include but not limited to titanium (Ti), titanium nitride (TiN), or tungsten (W), etc.

[0083] The embodiments of the present disclosure also provide a semiconductor structure. For details, please refer to the attached Figure 3 , as shown in the figure, the semiconductor structure includes:

[0084] A substrate 100;

[0085] A support structure 24 located above the substrate 100, and the support structure 24 includes a lower electrode hole 12 passing through the support structure 24 (as shown by the dashed box in the figure);

[0086] A lower electrode layer 16 located within the lower electrode hole 12. Among them, the lower electrode layer 16 includes a first lower electrode layer 13, a second lower electrode layer 14, and a third lower electrode layer 15. The first lower electrode layer 13 covers the inner surface of the lower electrode hole 12, the second lower electrode layer 14 covers the surface of the first lower electrode layer 13, and the third lower electrode layer 15 covers the surface of the second lower electrode layer 14; among them, the strength of the second lower electrode layer 14 is greater than the strength of the first lower electrode layer 13 and the third lower electrode layer 15.

[0087] Since the first lower electrode layer 13, the second lower electrode layer 14, and the third lower electrode layer 15 together form the lower electrode layer 16, and the strength of the second lower electrode layer 14 is greater than that of the first lower electrode layer 13 and the third lower electrode layer 15, the problem that the capacitive columns are prone to bending or tilting due to the insufficient strength of the single-layer lower electrode layer can be improved.

[0088] In some embodiments, the substrate 100 includes, for example, but is not limited to, a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In some specific embodiments, refer to the attached Figure 3 , the substrate 100 includes a doped or undoped silicon substrate. The substrate 100 includes a plurality of capacitive contact pads 101, and a dielectric layer 102 is filled between the capacitive contact pads 101. The plurality of capacitive contact pads 101 may be arranged in a hexagonal array in the substrate 100. In some other embodiments, the plurality of capacitive contact pads 101 may also adopt other array arrangement methods, which are not specifically limited herein. The material of the capacitive contact pad 101 may include a conductive material, for example, any combination of one or more of the metal materials tungsten, copper, aluminum, titanium, tantalum, silver, tantalum nitride, and titanium nitride. The material of the dielectric layer 102 may include an insulating material, such as an oxide, a nitride, or a nitrogen oxide, etc. The support structure 24 includes a first support layer 111, a second support layer 113, and a third support layer 115. Among them, the materials of the first support layer 111, the second support layer 113, and the third support layer 115 include but are not limited to nitrides. The materials of the first support layer 111, the second support layer 113, and the third support layer 115 may be the same or different. Specifically, the material of the first support layer 111 may be a B-containing insulating material, such as SiBN. Since doping B can reduce the hardness of the material, the morphology of the lower electrode hole 12 formed by, for example, an etching method is better. The materials of the second support layer 113 and the third support layer 115 may be C-containing insulating materials, such as SiCN. Since the SiCN material has good hardness, it can provide good support for the lower electrode layer 16. In some specific embodiments, the materials of the first lower electrode layer 13 and the third lower electrode layer 15 may include titanium nitride, and the material of the second lower electrode layer 14 may include silicon nitride.

[0089] In the above embodiments, the first lower electrode layer 13 has good electrical properties and mainly functions as a capacitor electrode plate. The second lower electrode layer 14 has high strength and mainly plays a supporting role to improve the overall strength of the composite film layer. When the ratio of the thickness of the first lower electrode layer 13 to the thickness of the second lower electrode layer 14 is relatively large, the proportion of the thickness of the second lower electrode layer 14 is relatively small, which will cause the strength of the composite film layer to fail to reach the expected level and have limited effect on improving the bending or inclination of the capacitor column. When the ratio of the thickness of the first lower electrode layer 13 to the thickness of the second lower electrode layer 14 is relatively small, the proportion of the thickness of the first lower electrode layer 13 is relatively small, which will increase the resistance of the composite film layer and reduce the electrical properties, thus affecting the performance of the capacitor to a certain extent. Therefore, in some specific embodiments, the ratio range of the thickness of the first lower electrode layer 13 to the thickness of the second lower electrode layer 14 is 80 - 250, including the end values, for example, it can be 90, 120, 150, 180 or 230. This will enable the strength and electrical properties of the composite film layer formed by the first lower electrode layer 13 and the second lower electrode layer 14 to reach the expected levels, and can achieve beneficial effects in improving the bending or inclination of the capacitor column while taking into account the electrical properties of the capacitor structure.

[0090] In some embodiments, referring to the attached Figure 4 , the third lower electrode layer 15 includes a first sub - part 25 and a second sub - part 26. Along the direction parallel to the substrate plane, the size of the second sub - part 26 is larger than that of the first sub - part 25, and the second sub - part 26 covers the upper surfaces of the first sub - part 25 and the second lower electrode layer 14.

[0091] Here, the substrate plane is the plane where the substrate 100 is located.

[0092] Since the second sub - part 26 of the third lower electrode layer 15 covers the upper surface of the second lower electrode layer 14, the proportion of the second lower electrode layer 14 in the entire lower electrode layer 16 is appropriately reduced, and the proportion of the third lower electrode layer 15 is appropriately increased. In this way, while maintaining sufficient overall strength of the lower electrode layer 16, the electrical properties of the lower electrode layer 16 can be further enhanced, and thus the performance of the capacitor can be further enhanced.

[0093] In some embodiments, referring to the attached Figure 5 , the first lower electrode layer 13 covering the inner surface of the lower electrode hole 12 (shown as the dotted box in the figure) forms a first cavity 27, the second lower electrode layer 14 only covers the side wall of the first cavity 27 and forms a second cavity 28, and the third lower electrode layer 15 fills the second cavity 28.

[0094] The second lower electrode layer 14 only covers the side wall of the first cavity 27. Compared with the structure in the above embodiment where the second lower electrode layer 14 covers the side wall and the bottom of the first lower electrode layer 13, the proportion of the second lower electrode layer 14 in the entire lower electrode layer 16 is appropriately reduced, and the proportion of the third lower electrode layer 15 is appropriately increased. In this way, while maintaining sufficient overall strength of the lower electrode layer 16, the electrical performance of the lower electrode layer 16 can be further enhanced, and then the performance of the capacitor can be further enhanced.

[0095] In some embodiments, referring to the attached Figure 3 , the semiconductor structure further includes: a dielectric layer 21 covering the surface of the lower electrode layer 16 and the support structure 24, and an upper electrode layer 22 covering the surface of the dielectric layer 21.

[0096] In some embodiments, the material of the dielectric layer 21 may include, but is not limited to, aluminum oxide, silicon nitride, silicon oxide, zirconium oxide, hafnium oxide, or a combination thereof, etc. The material of the upper electrode layer 22 includes, but is not limited to, titanium (Ti), titanium nitride (TiN), or tungsten (W), etc. The above lower electrode layer 16, dielectric layer 21, and upper electrode layer 22 together form a complete capacitor.

[0097] In some other embodiments, referring to the attached Figure 6 , there is a gap 29 between the upper electrode layers 22. The semiconductor structure further includes: a conductive connection layer 23, and the conductive connection layer 23 fills the gap 29 and covers the top of the upper electrode layer 22.

[0098] In some embodiments, the upper electrode layer 22 can directly fill the gap between the dielectric layers 21 and cover the top of the dielectric layer 21 to electrically connect multiple capacitors, eliminating the step of forming the conductive connection layer 23. However, since the material of the upper electrode layer 22 generally uses metal materials such as titanium nitride, the stress is relatively large, the filling property is not good enough, and defects such as voids are likely to appear in the upper electrode layer 22, which will affect the performance of the capacitor. Therefore, the upper electrode layer 22 covers the dielectric layer 21 and there is a gap 29 between the upper electrode layers 22. The conductive connection layer 23 fills the gap 29 and covers the top of the upper electrode layer 22 to connect multiple capacitors into a whole. The material of the conductive connection layer 23 may include, but is not limited to, polysilicon, silicon germanium, etc. The above materials have excellent filling properties, can fully fill the gap 29, and the formed film layer has relatively small stress, which can avoid defects such as voids that may appear in the film layer, and can play a good supporting role for the capacitor. Finally, a capacitor structure with better electrical performance and higher stability is formed.

[0099] In summary, the present disclosure first provides a substrate 10, where the substrate 10 includes a stacked structure 11 and a lower electrode hole 12 penetrating the stacked structure 11. Then, a first lower electrode layer 13 covering the inner surface of the lower electrode hole 12, a second lower electrode layer 14 covering the surface of the first lower electrode layer 13, and a third lower electrode layer 15 covering the surface of the second lower electrode layer 14 are formed in the lower electrode hole 12. Since the first lower electrode layer 13, the second lower electrode layer 14, and the third lower electrode layer 15 together constitute the lower electrode layer 16, and the strength of the second lower electrode layer 14 is greater than the strength of the first lower electrode layer 13 and the third lower electrode layer 15, the problem that the capacitor column is prone to bending or tilting due to insufficient strength of the single-layer electrode plate can be improved. In the embodiment of the present disclosure, the second lower electrode layer 14 with high strength is compounded in the first lower electrode layer 13 and the third lower electrode layer 15, which can enhance the strength of the entire lower electrode layer 16, and further effectively resist the deformation caused by stress, so that the stability of the capacitor column in the process is enhanced, and the problem that the support layer cannot be normally opened due to the etching opening skew caused by the bending or tilting of the capacitor column can be improved, so that the bottom oxide layer cannot be fully removed, and sufficient space cannot be reserved for the upper electrode layer 22, resulting in the failure of the entire capacitor can be improved.

[0100] It should be noted that the manufacturing method of the semiconductor structure and the semiconductor structure provided in the embodiments of the present disclosure can be applied to any integrated circuit including this structure, such as a dynamic random access memory (DRAM). Among the technical features of the technical solutions recorded in each embodiment, any combination can be made without conflict.

[0101] The above is only a preferred embodiment of the present disclosure, and is not used to limit the protection scope of the present disclosure. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a stacked structure and a lower electrode hole penetrating the stacked structure; Forming a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer in the lower electrode hole, the first lower electrode layer covering the inner surface of the lower electrode hole, the second lower electrode layer covering the surface of the first lower electrode layer, the third lower electrode layer covering the surface of the second lower electrode layer, the first lower electrode layer, the second lower electrode layer, and the third lower electrode layer being defined as the lower electrode layer; wherein, The strength of the second lower electrode layer is greater than the strength of the first lower electrode layer and the third lower electrode layer.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, Forming the first lower electrode layer and the second lower electrode layer includes: Performing a first process cycle a first predetermined number of times to prepare the first lower electrode layer; performing a second process cycle a second predetermined number of times to prepare the second lower electrode layer; Wherein, the ratio range of the first predetermined number to the second predetermined number is 40 to 50.

3. The manufacturing method of the semiconductor structure according to claim 2, wherein, The first process cycle includes: Introducing a first gas and maintaining for a first duration; Continuing to introduce the first gas for purging, maintaining for a second duration; Introducing a second gas for deposition reaction, maintaining for a third duration; Continuing to introduce the second gas for purging, maintaining for a fourth duration.

4. The manufacturing method of the semiconductor structure according to claim 2, characterized in that, The second process cycle includes: Introducing a third gas and maintaining for a fifth duration; Continuing to introduce the third gas for purging, maintaining for a sixth duration; Introducing a fourth gas for deposition reaction, maintaining for a seventh duration; Continuing to introduce the fourth gas for purging, maintaining for an eighth duration.

5. The manufacturing method of the semiconductor structure according to any one of claims 1-4, wherein, Forming the first lower electrode layer, the second lower electrode layer, and / or the third lower electrode layer at a temperature of 580 °C to 620 °C.

6. The manufacturing method of the semiconductor structure according to claim 1, wherein Providing a substrate, including: Forming the stacked structure on a substrate, the stacked structure at least including a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer; Etching the stacked structure in a direction perpendicular to the substrate plane to expose the substrate to form the lower electrode hole.

7. The manufacturing method of the semiconductor structure according to claim 6, characterized in that, After forming the lower electrode layer, the method further includes: Forming a first mask layer and patterning the first mask layer to expose part of the third support layer and the lower electrode layer; Etching the third support layer to form a first window; Removing the second sacrificial layer through the first window; Etching the second support layer to form a second window; Removing the first sacrificial layer through the second window.

8. The manufacturing method of the semiconductor structure according to claim 7, characterized in that, After removing the first sacrificial layer, the method further includes: Forming a dielectric layer, the dielectric layer at least covering the surface of the lower electrode layer; Forming an upper electrode layer, the upper electrode layer covering the surface of the dielectric layer.

9. A semiconductor structure, characterized in that, Comprising: A substrate; A support structure located above the substrate, the support structure including a lower electrode hole penetrating the support structure; A lower electrode layer located within the lower electrode hole, wherein the lower electrode layer includes a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer. The first lower electrode layer covers the inner surface of the lower electrode hole, the second lower electrode layer covers the surface of the first lower electrode layer, and the third lower electrode layer covers the surface of the second lower electrode layer; wherein the strength of the second lower electrode layer is greater than the strength of the first lower electrode layer and the third lower electrode layer.

10. The semiconductor structure according to claim 9, wherein The ratio range of the thickness of the first lower electrode layer to the thickness of the second lower electrode layer is 80 to 250.

11. The semiconductor structure according to claim 9, wherein, The materials of the first lower electrode layer and the third lower electrode layer include titanium nitride, and the material of the second lower electrode layer includes silicon nitride.

12. The semiconductor structure according to claim 9, wherein The third lower electrode layer includes a first sub - portion and a second sub - portion. Along the direction parallel to the substrate plane, the size of the second sub - portion is larger than the size of the first sub - portion, and the second sub - portion covers the upper surfaces of the first sub - portion and the second lower electrode layer.

13. The semiconductor structure according to claim 9, wherein The first lower electrode layer covering the inner surface of the lower electrode hole forms a first cavity, the second lower electrode layer only covers the side wall of the first cavity and forms a second cavity, and the third lower electrode layer fills the second cavity.

14. The semiconductor structure according to claim 9, wherein The semiconductor structure further includes: A dielectric layer covering the surface of the lower electrode layer and the support structure, and an upper electrode layer covering the surface of the dielectric layer.

15. The semiconductor structure according to claim 14, wherein, There is a gap between the upper electrode layers, and the semiconductor structure further includes: A conductive connection layer, which fills the gap and covers the top of the upper electrode layer.

Images