Array substrate, display panel and method for testing array substrate

Abstract

An array substrate includes N test signal lines, N is an integer greater than 1; N first control signal lines; N second control signal lines; M first switch transistors; and M second switch transistors. The second electrode of the mth first switch transistor is connected to the first electrode of the mth second switch transistor, 1≤m≤M. The nth test signal line is connected to the first electrode of the (kN+n)th first switch transistor, 1≤n≤N, 0≤k<M / N. The nth first control signal line is connected to the first electrode of the (kN+n)th first switch transistor. 2 +((n‑1)*N)+1) to (kN 2 +n*N) gates of the first switch transistors, 0≤k

Description

Technical Field

[0001] The present invention relates to display technology, and in particular, to an array substrate, a display panel, and a method for testing an array substrate. Background Art

[0002] Generally, an aging process is performed on an organic light-emitting diode (OLED) device after the formation of the OLED device to eliminate bright spots and improve transistor stability. Summary of the Invention

[0003] In one aspect, the present disclosure provides an array substrate, including: N test signal lines, where N is an integer greater than 1; N first control signal lines; N second control signal lines; M first switching transistors, where M is an integer greater than N; and M second switching transistors; wherein, the second electrode of the m-th first switching transistor is connected to the first electrode of the m-th second switching transistor, 1 ≤ m ≤ M; the n-th test signal line is connected to the first electrode of the (kN + n)-th first switching transistor, 1 ≤ n ≤ N, 0 ≤ k < M / N; the n-th first control signal line is connected to the gates of the ((kN + ((n - 1)*N) + 1)-th to the (kN + n*N)-th first switching transistors, 0 ≤ k < M / N; the n-th second control signal line is connected to the gate of the (kN + n)-th second switching transistor; and the second electrode of the m-th second switching transistor is connected to the m-th array substrate signal line. 2 +((n - 1)*N)+1) to the (kN 2 +n*N) first switching transistors, 0 ≤ k < M / N; the n-th second control signal line is connected to the gate of the (kN + n)-th second switching transistor; and the second electrode of the m-th second switching transistor is connected to the m-th array substrate signal line.

[0004] Optionally, M is an integer multiple of N.

[0005] Optionally, N is the total number of sub-pixels of different colors in the array substrate, and the array substrate includes M array substrate signal lines respectively connected to the second electrodes of the M second switching transistors.

[0006] Optionally, N = 3.

[0007] Optionally, the array substrate includes: a first first control signal line, a second first control signal line and a third first control signal line; a first second control signal line, a second second control signal line and a third second control signal line; a first test signal line, a second test signal line and a third test signal line; a first first switch transistor, a second first switch transistor, a third first switch transistor, a fourth first switch transistor, a fifth first switch transistor, a sixth first switch transistor, a seventh first switch transistor, an eighth first switch transistor and a ninth first switch transistor; and a first second switch transistor, a second second switch transistor, a third second switch transistor, a fourth second switch transistor, a fifth second switch transistor, a sixth second switch transistor, a seventh second switch transistor, an eighth second switch transistor and a ninth second switch transistor; wherein the first test signal line is connected to the first electrodes of the first first switch transistor, the fourth first switch transistor and the seventh first switch transistor; and the second test signal line is connected to the second first switch transistor, the fifth first switch transistor and the eighth first switch transistor. the first electrode of the transistor; the third test signal line is connected to the first electrode of the third first switch transistor, the sixth first switch transistor and the ninth first switch transistor; the first first control signal line is connected to the gate of the first first switch transistor, the second first switch transistor and the third first switch transistor; the second first control signal line is connected to the gate of the fourth first switch transistor, the fifth first switch transistor and the sixth first switch transistor; the third first control signal line is connected to the gate of the seventh first switch transistor, the eighth first switch transistor and the ninth first switch transistor; the first second control signal line is connected to the gate of the first second switch transistor, the fourth second switch transistor and the seventh second switch transistor; the second second control signal line is connected to the gate of the second second switch transistor, the fifth second switch transistor and the eighth second switch transistor; and the third second control signal line is connected to the gate of the third second switch transistor, the sixth second switch transistor and the ninth second switch transistor.

[0008] Optionally, the array substrate includes: a semiconductor material layer, wherein the semiconductor material layer includes an active layer of the M first switching transistors and the M second switching transistors; a first conductive layer, wherein the first conductive layer includes gates of the M first switching transistors and the M second switching transistors; a second conductive layer, wherein the second conductive layer includes M first connecting lines and M second connecting lines, the M first connecting lines respectively connect the first electrodes of the M first switching transistors to the corresponding test signal lines, and the M second connecting lines respectively connect the second electrodes of the M first switching transistors to the first electrodes of the M second switching transistors; and a first signal line layer, wherein the first signal line layer includes a first sublayer of the N test signal lines, the N first control signal lines, the N second control signal lines, the first electrodes and the second electrodes of the M first switching transistors, and the first electrodes and the second electrodes of the M second switching transistors.

[0009] Optionally, the array substrate also includes: an insulating layer, which is located between the first conductive layer and the second conductive layer; an interlayer dielectric layer, which is located between the second conductive layer and the first signal line layer; and a planarization layer, which is located on the side of the first signal line layer away from the interlayer dielectric layer; wherein the corresponding first electrodes of the corresponding first switching transistors are connected to the corresponding first connecting lines through through holes extending through the interlayer dielectric layer; the corresponding first sublayers of the corresponding test signal lines are respectively connected to the corresponding first connecting lines through through holes extending through the interlayer dielectric layer; and the corresponding first control signal lines are respectively connected to the corresponding gates of the corresponding first switching transistors through through holes extending through the interlayer dielectric layer and the insulating layer.

[0010] Optionally, the corresponding second electrode of the corresponding first switching transistor is connected to the corresponding second connecting line through a through hole extending through the interlayer dielectric layer; the corresponding first electrode of the corresponding second switching transistor is connected to the corresponding second connecting line through a through hole extending through the interlayer dielectric layer; and the corresponding second control signal line is connected to the corresponding gate of the corresponding second switching transistor through through holes extending through the interlayer dielectric layer and the insulating layer, respectively.

[0011] Optionally, the array substrate also includes: a second signal line layer, wherein the second signal line layer includes a second sublayer of N test signal lines; and a planarization layer located between the first signal line layer and the second signal line layer; wherein the corresponding second sublayer of the corresponding test signal line is connected to the corresponding first sublayer of the corresponding test signal line via a through hole extending through the planarization layer.

[0012] Optionally, the corresponding first electrode of the corresponding first switching transistor is connected to the corresponding active layer of the corresponding first switching transistor through a via hole extending through the interlayer dielectric layer and the insulating layer; the corresponding second electrode of the corresponding first switching transistor is connected to the corresponding active layer of the corresponding first switching transistor through a via hole extending through the interlayer dielectric layer and the insulating layer; the corresponding first electrode of the corresponding second switching transistor is connected to the corresponding active layer of the corresponding second switching transistor through a via hole extending through the interlayer dielectric layer and the insulating layer; and the corresponding second electrode of the corresponding second switching transistor is connected to the corresponding active layer of the corresponding second switching transistor through a via hole extending through the interlayer dielectric layer and the insulating layer.

[0013] In another aspect, the present disclosure provides a display panel, including an array substrate and M array substrate signal lines, where the array substrate is the array substrate fabricated as above or by the above method, and the M array substrate signal lines are respectively connected to the second electrodes of the M second switching transistors.

[0014] Optionally, the M array substrate signal lines are M data lines.

[0015] In another aspect, the present disclosure provides a method for testing an array substrate, including: providing a test circuit, which includes N test signal lines, where N is an integer greater than 1; N first control signal lines; N second control signal lines; M first switching transistors, where M is an integer greater than N; and M second switching transistors; connecting the second electrode of the m-th first switching transistor to the first electrode of the m-th second switching transistor, where 1 ≤ m ≤ M; connecting the n-th test signal line to the first electrode of the (kN + n)-th first switching transistor, where 1 ≤ n ≤ N and 0 ≤ k < M / N; connecting the n-th first control signal line to the gates of the ((kN + ((n - 1)*N) + 1)-th to the (kN + n*N)-th first switching transistors, where 0 ≤ k < M / N; connecting the n-th second control signal line to the gate of the (kN + n)-th second switching transistor; and connecting the second electrode of the m-th second switching transistor to the m-th array substrate signal line. 2 +((n - 1)*N)+1) to the gates of the first switching transistors from the (kN 2 +n*N), where 0 ≤ k < M / N; connecting the n-th second control signal line to the gate of the (kN + n)-th second switching transistor; and connecting the second electrode of the m-th second switching transistor to the m-th array substrate signal line.

[0016] Optionally, the test is performed in a cycle including N time periods; wherein, the method includes, in the n-th time period, providing a conduction voltage signal to the n-th first control signal line, while providing a cut-off voltage signal to the first control signal lines other than the n-th first control signal line, providing a conduction voltage signal to the N second control signal lines respectively, and providing a test voltage signal to the N test signal lines respectively, so as to provide the test voltage signal to the array substrate signal lines, which are respectively connected to the (kN2 +((n-1)*N)+1) to (kN 2 +n*N) second electrodes of the second switching transistors.

[0017] Optionally, N=3; and the cycle includes a first period, a second period and a third period.

[0018] Optionally, in the first time period, the method includes providing a turn-on voltage signal to the first first control signal line, and providing a turn-off voltage signal to the second first control signal line and the third first control signal line, providing the turn-on voltage signal to the first second control signal line, the second second control signal line and the third second control signal line respectively, and providing a test voltage signal to the first test signal line, the second test signal line and the third test signal line respectively, so as to provide the test voltage signal to the array substrate signal line respectively, which is connected to the second electrode of the first second switch transistor, the second second switch transistor and the third second switch transistor respectively; in the second time period, the method includes providing a turn-on voltage signal to the second first control signal line, and providing a turn-off voltage signal to the first first control signal line and the third first control signal line, providing the turn-on voltage signal to the first second control signal line, the second second control signal line and the third second control signal line respectively, and providing the test voltage signal to the first test signal line, the second test signal line and the third test signal line respectively. A test voltage signal is provided to the first test signal line, the second test signal line and the third test signal line, respectively, so as to provide the test voltage signal to the array substrate signal line, which is respectively connected to the second electrodes of the fourth second switch transistor, the fifth second switch transistor and the sixth second switch transistor; and in the third time period, the method includes providing a turn-on voltage signal to the third first control signal line, and simultaneously providing a turn-off voltage signal to the first first control signal line and the second first control signal line, providing the turn-on voltage signal to the first second control signal line, the second second control signal line and the third second control signal line, and providing the test voltage signal to the first test signal line, the second test signal line and the third test signal line, respectively, so as to provide the test voltage signal to the array substrate signal line, which is respectively connected to the second electrodes of the seventh second switch transistor, the eighth second switch transistor and the ninth second switch transistor.

[0019] Optionally, the test is performed in a cycle including N time periods, each time period including N sub-time periods; wherein the method includes: in the nth time period, providing a turn-on voltage signal to the nth second control signal line, and providing a turn-off voltage signal to the second control signal line other than the nth second control signal line, and providing the test voltage signal to the N test signal lines respectively; in the nth sub-time period of the nth time period, providing a turn-on voltage signal to the nth first control signal line, and providing a turn-off voltage signal to the first control signal line other than the nth first control signal line, thereby providing the test voltage signal to the array substrate signal line respectively, which is connected to the (kNth) first control signal line. 2 +((n-1)*N)+n) second electrodes of the second switching transistors.

[0020] Optionally, N=3; the cycle includes a first time period, a second time period and a third time period; the first time period includes a first first sub-period, a second first sub-period and a third first sub-period; the second time period includes a first second sub-period, a second second sub-period and a third second sub-period; and the third time period includes a first third sub-period, a second third sub-period and a third third sub-period.

[0021] Optionally, in the first time period, the method includes providing a turn-on voltage signal to the first second control signal line, and providing a turn-off voltage signal to the second second control signal line and the third second control signal line, and providing the test voltage signal to the first test signal line, the second test signal line and the third test signal line respectively; in the first first sub-time period, the method includes providing a turn-on voltage signal to the first first control signal line, and providing a turn-off voltage signal to the second first control signal line and the third first control signal line, thereby providing the test voltage signal to the array substrate signal line connected to the second electrode of the first second switch transistor respectively; in the second first sub-time period , the method includes providing a turn-on voltage signal to the second first control signal line, and providing a turn-off voltage signal to the first first control signal line and the third first control signal line, so that the test voltage signal is respectively provided to the array substrate signal line connected to the second electrode of the fourth second switch transistor; in the third first sub-period, the method includes providing a turn-on voltage signal to the third first control signal line, and providing a turn-off voltage signal to the first first control signal line and the second first control signal, so that the test voltage signal is respectively provided to the array substrate signal line connected to the second electrode of the seventh second switch transistor; in the second period In the method, the method includes providing a turn-on voltage signal to the second second control signal line, and providing a turn-off voltage signal to the first second control signal line and the third second control signal line, and providing a test voltage signal to the first test signal line, the second test signal line, and the third test signal line respectively; in the first second sub-period, the method includes providing a turn-on voltage signal to the first first control signal line, and providing a turn-off voltage signal to the second first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the second second switch transistor respectively; in the second In a second sub-period, the method includes providing a turn-on voltage signal to the second first control signal line, and providing a turn-off voltage signal to the first first control signal line and the third first control signal line, so as to respectively provide the test voltage signal to the array substrate signal line connected to the second electrode of the fifth second switch transistor; in the third second sub-period, the method includes providing a turn-on voltage signal to the third first control signal line, and providing a turn-off voltage signal to the first first control signal line and the second first control signal line, so as to respectively provide the test voltage signal to the array substrate signal line connected to the second electrode of the eighth second switch transistor;In the third period, the method includes providing a turn-on voltage signal to the third second control signal line, and providing a turn-off voltage signal to the first second control signal line and the second second control signal line, and providing a test voltage signal to the first test signal line, the second test signal line and the third test signal line respectively; in the first third sub-period, the method includes providing a turn-on voltage signal to the first first control signal line, and providing a turn-off voltage signal to the second first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the third second switch transistor respectively; in the In the second third sub-period, the method includes providing a turn-on voltage signal to the second first control signal line, and providing a turn-off voltage signal to the first first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the sixth second switch transistor; and in the third third sub-period, the method includes providing a turn-on voltage signal to the third first control signal line, and providing a turn-off voltage signal to the first first control signal line and the second first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the ninth second switch transistor.;

[0022] Optionally, the array substrate further comprises M array substrate signal lines respectively connected to the second electrodes of the M second switch transistors, wherein the M array substrate signal lines are M data lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1A is a circuit diagram of a test circuit in some embodiments according to the present disclosure.

[0025] Figure 1B is a circuit diagram of a test circuit in some embodiments according to the present disclosure.

[0026] Figure 2A is a schematic diagram of the structure of a test circuit in some embodiments of the present disclosure.

[0027] Figure 2B is a schematic diagram of the structure of a semiconductor material layer in a test circuit according to some embodiments of the present disclosure.

[0028] Figure 2C is a schematic diagram of the structure of a first conductive layer in a test circuit according to some embodiments of the present disclosure.

[0029] Figure 2D is a schematic diagram of the structure of the second conductive layer in the test circuit according to some embodiments of the present disclosure.

[0030] Figure 2E is a schematic diagram of the structure of a first signal line layer in a test circuit according to some embodiments of the present disclosure.

[0031] Figure 2F is a schematic diagram of the structure of a second signal line layer in a test circuit according to some embodiments of the present disclosure.

[0032] Figure 3A is along Figure 2A Cross-sectional view along line A-A'.

[0033] Figure 3B is along Figure 2A Cross-sectional view along line BB'.

[0034] Figure 3C is along Figure 2A Cross-sectional view along line CC'.

[0035] Figure 3D is along Figure 2A Cross-sectional view along line D-D'.

[0036] Figure 3E is along Figure 2A Cross-sectional view along line E-E'.

[0037] Figure 3F is along Figure 2A Cross-sectional view along line F-F'.

[0038] Figure 3G is along Figure 2A Cross-sectional view along line G-G'.

[0039] Figure 3H is along Figure 2A Cross-sectional view along line H-H'.

[0040] Fig. 3I is along Figure 2A Cross-sectional view along line I-I'.

[0041] Figure 3J is along Figure 2A Cross-sectional view of the J-J' line in FIG.

[0042] Figure 3K is along Figure 2A Cross-sectional view of the K-K' line in .

[0043] Figure 4A is a schematic diagram of the structure of a display panel in some embodiments of the present disclosure.

[0044] Figure 4B Shows the detailed structure in the display area of a display panel according to some embodiments of the present disclosure.

[0045] Figure 4C Shows the detailed structure in the display area of a display panel according to some embodiments of the present disclosure.

[0046] Figure 4D Is a cross-sectional view along the G-G' line in a test circuit according to some embodiments of the present disclosure.

[0047] Figure 5 Is a timing diagram for operating a test circuit according to some embodiments of the present disclosure. Detailed implementation

[0048] The present disclosure will now be described more specifically with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the exact forms disclosed.

[0049] The present disclosure particularly provides an array substrate, a display panel, and a method for testing an array substrate, which substantially avoid one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes N test signal lines, where N is an integer greater than 1; N first control signal lines; N second control signal lines; M first switching transistors, where M is an integer greater than N; and M second switching transistors. In some embodiments, the second electrode of the m-th first switching transistor is connected to the first electrode of the m-th second switching transistor, where 1 ≤ m ≤ M. Optionally, the n-th test signal line is connected to the first electrode of the (kN + n)-th first switching transistor, where 1 ≤ n ≤ N and 0 ≤ k < M / N. Optionally, the n-th first control signal line is connected to the gates of the ((kN 2 +((n - 1)*N)+1)-th to the (kN 2 +n*N)-th first switching transistors, where 0 ≤ k < M / N. Optionally, the n-th second control signal line is connected to the gate of the (kN + n)-th second switching transistor. Optionally, the second electrode of the m-th second switching transistor is connected to the m-th array substrate signal line.

[0050] Figure 1A Is a circuit diagram of a test circuit according to some embodiments of the present disclosure. Refer to Figure 1A, in some embodiments, the test circuit in the array substrate includes N test signal lines TSL, where N is an integer greater than 1; N first control signal lines CSL1; N second control signal lines CSL2; M first switching transistors SW1, where M is an integer greater than N; and M second switching transistors SW2. Figure 1A The corresponding first switching transistor in is represented by a first electrode E11 (e.g., source), a second electrode E12 (e.g., drain), and a gate G1. Figure 1A The corresponding second switching transistor in is represented by a first electrode E21 (e.g., source), a second electrode E22 (e.g., drain), and a gate G2. As Figure 1A shown, in some embodiments, the second electrode E12 of the m-th first switching transistor SW1m is connected to the first electrode E21 of the m-th second switching transistor SW2m. Optionally, 1 ≤ m ≤ M. Optionally, the n-th test signal line TSLn is connected to the first electrode of the (kN + n)-th first switching transistor. Optionally, 1 ≤ n ≤ N, 0 ≤ k < M / N. Optionally, 0 ≤ k ≤ ((M / N) - 1). Optionally, the n-th first control signal line CSL1n is connected to the gates of the (kN 2 + ((n - 1)*N) + 1)-th to the (kN 2 + n*N)-th first switching transistors, 0 ≤ k < M / N. Optionally, the n-th second control signal line CSL2n is connected to the gate of the (kN + n)-th second switching transistor. Optionally, the second electrode E22 of the m-th second switching transistor is connected to the m-th array substrate signal line SLm. Optionally, M is a positive integer, N is a positive integer, m is a positive integer, n is a positive integer, and k is a positive integer. Optionally, M is an integer multiple of N.

[0051] In some embodiments, N is the total number of sub-pixels of different colors in the array substrate, and the array substrate includes M array substrate signal lines respectively connected to the second electrodes of the M second switching transistors. In one example, the array substrate includes red sub-pixels, green sub-pixels, and blue sub-pixels, and N = 3. In another example, the array substrate includes red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, and N = 4.

[0052] In one example, N = 2. In another example, N = 3. In another example, N = 4. In another example, N = 5. In another example, N = 6.

[0053] Figure 1B is a circuit diagram of the test circuit according to some embodiments of the present disclosure. Figure 1B shows an example of the test circuit where N = 3, referring to Figure 1BIn some embodiments, the test circuit includes a first first control signal line CSL1-1, a second first control signal line CSL1-2, and a third first control signal line CSL1-3; a first second control signal line CSL2-1, a second second control signal line CSL2-2, and a third second control signal line CSL2-3; a first test signal line TSL1, a second test signal line TSL2, and a third test signal line TSL3; a first first switch transistor SW1-1, a second first switch transistor SW1-2, a third first switch transistor SW1-3, a fourth first switch transistor SW1-4, a fifth first switch transistor SW1-5, a fifth first switch transistor SW1-6, a fifth first switch transistor SW1-7, a fifth first switch transistor SW1-8, a first test signal line TSL1, a second test signal line TSL2, and a third test signal line TSL3. a first switching transistor SW1-5, a sixth first switching transistor SW1-6, a seventh first switching transistor SW1-7, an eighth first switching transistor SW1-8 and a ninth first switching transistor SW1-9; and a first second switching transistor SW2-1, a second second switching transistor SW2-2, a third second switching transistor SW2-3, a fourth second switching transistor SW2-4, a fifth second switching transistor SW2-5, a sixth second switching transistor SW2-6, a seventh second switching transistor SW2-7, an eighth second switching transistor SW2-8 and a ninth second switching transistor SW2-9.

[0054] Reference Figure 1A and Figure 1B, in some embodiments, the first test signal line TSL1 is connected to the first electrode of the first first switch transistor SW1-1, the fourth first switch transistor SW1-4, and the seventh first switch transistor SW1-7. The second test signal line TSL2 is connected to the first electrode of the second first switch transistor SW1-2, the fifth first switch transistor SW1-5, and the eighth first switch transistor SW1-8. The third test signal line TSL3 is connected to the first electrode of the third first switch transistor SW1-3, the sixth first switch transistor SW1-6, and the ninth first switch transistor SW1-9. The first first control signal line CSL1-1 is connected to the gates of the first first switch transistor SW1-1, the second first switch transistor SW1-2, and the third first switch transistor SW1-3. The second first control signal line CSL1-2 is connected to the gates of the fourth first switch transistor SW1-4, the fifth first switch transistor SW1-5, and the sixth first switch transistor SW1-6. The third first control signal line CSL1-3 is connected to the gates of the seventh first switch transistor SW1-7, the eighth first switch transistor SW1-8, and the ninth first switch transistor SW1-9. The first second control signal line CSL2-1 is connected to the gates of the first second switch transistor SW2-1, the fourth second switch transistor SW2-4, and the seventh second switch transistor SW2-7. The second second control signal line CSL2-2 is connected to the gates of the second second switch transistor SW2-2, the fifth second switch transistor SW2-5, and the eighth second switch transistor SW2-8. The third second control signal line CSL2-3 is connected to the gates of the third second switch transistor SW2-3, the sixth second switch transistor SW2-6, and the ninth second switch transistor SW2-9.

[0055] In some embodiments, the test circuit includes a semiconductor material layer, a first conductive layer, a second conductive layer, a first signal line layer, and a second signal line layer. Figure 2A is a schematic diagram of the structure of a test circuit in some embodiments of the present disclosure. Figure 2B is a schematic diagram of the structure of a semiconductor material layer in a test circuit according to some embodiments of the present disclosure. Figure 2C is a schematic diagram of the structure of a first conductive layer in a test circuit according to some embodiments of the present disclosure. Figure 2D is a schematic diagram of the structure of the second conductive layer in the test circuit according to some embodiments of the present disclosure. Figure 2E is a schematic diagram of the structure of a first signal line layer in a test circuit according to some embodiments of the present disclosure. Figure 2F is a schematic diagram of the structure of a second signal line layer in a test circuit according to some embodiments of the present disclosure.

[0056] refer to Figure 2A , a corresponding first switching transistor SWr1 and a corresponding second switching transistor SWr2 are shown. Figure 2A Also shown are the first test signal line TSL1, the second test signal line TSL2, the third test signal line TSL3, the first first control signal line CSL1-1, the second first control signal line CSL1-2, the third first control signal line CSL1-3, the first second control signal line CSL2-1, the second second control signal line CSL2-2 and the third second control signal line CSL2-3.

[0057] Reference Figure 2A and Figure 2B In some embodiments, the semiconductor material layer includes active layers of M first switch transistors and M second switch transistors. The corresponding active layer of the corresponding first switch transistor SWr1 is Figure 2B In the figure, it is represented as ACTr1, and the corresponding active layer of the corresponding second switch transistor SWr2 is Figure 2B It is represented as ACTr2 in the text.

[0058] Reference Figure 2A and Figure 2C In some embodiments, the first conductive layer includes gates of M first switch transistors and M second switch transistors. The gates of the corresponding first switch transistors SWr1 are Figure 2C In the figure, Gr1 is represented, and the corresponding gate of the corresponding second switch transistor SWr2 is Figure 2C Represented as Gr2.

[0059] Reference Figure 2A and Figure 2D In some embodiments, the second conductive layer includes M first connection lines and M second connection lines, the M first connection lines respectively connect the first electrodes of the M first switch transistors to the corresponding test signal lines, and the M second connection lines respectively connect the second electrodes of the M first switch transistors to the first electrodes of the M second switch transistors. Figure 2D In the figure, it is represented as CLr1, and the corresponding second connecting line is Figure 2D It is represented as CLr2.

[0060] refer to Figure 2A and Figure 2EIn some embodiments, the first signal line layer includes a first sublayer of N test signal lines (e.g., TSL1-1, TSL2-1, and TSL3-1), N first control signal lines (e.g., CSL1-1, CSL1-2, and CSL1-3), N second control signal lines (e.g., CSL2-1, CSL2-2, and CSL2-3), first electrodes and second electrodes of M first switch transistors, and first electrodes and second electrodes of M second switch transistors. The corresponding first electrode and the corresponding second electrode of the corresponding first switch transistor SWr1 are Figure 2E In the figure, the first electrode and the second electrode of the second switching transistor SWr2 are shown as Er11 and Er12, respectively. Figure 2E Represented as Er21 and Er22.

[0061] In some embodiments, the test circuit further includes a second signal line layer. Figure 2F FIG. 1 is a schematic diagram of the structure of the second signal line layer in the test circuit according to some embodiments of the present disclosure. Figure 2A and Figure 2F In some embodiments, the second signal line layer includes a second sub-layer of N test signal lines (eg, TSL1-2, TSL2-2, and TSL3-2).

[0062] Figure 3A is along Figure 2A A cross-sectional view of the line A-A' in FIG. Figure 2A and Figure 3A In some embodiments, the test circuit includes a base substrate BS, a gate insulating layer GI located on the base substrate BS, an insulating layer IN located on the gate insulating layer GI, an interlayer dielectric layer ILD located on the insulating layer IN, and a planarization layer PLN located on the interlayer dielectric layer ILD. The gate insulating layer GI is located between the semiconductor material layer and the first conductive layer. The insulating layer IN is located between the first conductive layer and the second conductive layer. The interlayer dielectric layer ILD is located between the second conductive layer and the first signal line layer. The planarization layer is located between the first signal line layer and the second signal line layer. Figure 2A , Figure 2D , Figure 2E and Figure 3A In some embodiments, the first electrode Er11 of the first switch transistor Swr1 is connected to the first transistor via a via hole (eg, Figure 3A v1) in is connected to the corresponding first connection line CLr1.

[0063] Figure 3B is along Figure 2A Cross-sectional view of line BB' in Fig. Figure 2A , Figure 2D , Figure 2E and Figure 3B In some embodiments, the corresponding first sub-layers TSL1-1 of the corresponding test signal lines are connected through vias (eg, Figure 3B v2 in the example) is connected to the corresponding first connection line (for example, Figure 3B CLr1 in ).

[0064] Figure 3C is along Figure 2A The cross-sectional view of the line C-C' in Fig. Figure 2A , Figure 2C , Figure 2E and Figure 3C In some embodiments, the corresponding first control signal line (eg, Figure 3C The CSL1-1 in the figure is respectively connected by through holes (eg, Figure 3C v3 in the figure) is connected to the corresponding gate of the corresponding first switching transistor (for example, Figure 3C in Gr1).

[0065] Figure 3D is along Figure 2A The cross-sectional view of the line D-D' in Fig. Figure 2A , Figure 2D , Figure 2E and Figure 3D In some embodiments, the corresponding second electrode of the corresponding first switch transistor (eg, Figure 3D Er12 in) through a via extending through the interlayer dielectric layer ILD (e.g., Figure 3D v4 in) is connected to the corresponding second connection line (for example, Figure 3D CLr2 in ).

[0066] Figure 3E is along Figure 2A The cross-sectional view of the line E-E' in Fig. Figure 2A , Figure 2D , Figure 2E and Figure 3E In some embodiments, the corresponding first electrode of the corresponding second switch transistor (eg, Figure 3E Er21 in) through a via extending through the interlayer dielectric layer ILD (e.g., Figure 3E v5 in) is connected to the corresponding second connection line (for example, Figure 3E CLr2 in ).

[0067] Figure 3F is along Figure 2A The cross-sectional view of the F-F' line in Fig. Figure 2A , Figure 2C , Figure 2E and Figure 3FIn some embodiments, the corresponding second control signal line (eg, Figure 3F CSL2-1 in the figure) are respectively connected by through holes (eg, Figure 3F v6 in) is connected to the corresponding gate of the corresponding second switching transistor (eg, Figure 3F in Gr2).

[0068] Figure 3G is along Figure 2A Cross-sectional view of line G-G' in Fig. Figure 2A , Figure 2E , Figure 2F and Figure 3G In some embodiments, the corresponding second sublayer of the corresponding test signal line (eg, Figure 3G TSL1-2 in the planarization layer PLN) through a through hole (e.g., Figure 3G v7 in the figure) is connected to the corresponding first sublayer of the corresponding test signal line (for example, Figure 3G TSL1-1 in .

[0069] Figure 3H is along Figure 2A Cross-sectional view of the H-H' line in Fig. Figure 2A , Figure 2B , Figure 2E and Figure 3H In some embodiments, the corresponding first electrode of the corresponding first switch transistor (eg, Figure 3H Er11 in) is formed by a through hole (eg, Figure 3H v8 in ) is connected to the corresponding active layer of the corresponding first switching transistor (eg, Figure 3H ACTr1 in ).

[0070] Fig. 3I is along Figure 2A The cross-sectional view of the line I-I' in Fig. Figure 2A , Figure 2B , Figure 2E and Fig. 3I In some embodiments, the corresponding second electrode of the corresponding first switch transistor (eg, Fig. 3I Er12 in) is formed by a through hole (eg, Fig. 3I v9 in the figure) is connected to the corresponding active layer of the corresponding first switching transistor (for example, Fig. 3I ACTr1 in ).

[0071] Figure 3J is along Figure 2A The cross-sectional view of the J-J' line in Fig. Figure 2A , Figure 2B , Figure 2E and Figure 3J In some embodiments, the corresponding first electrode of the corresponding second switch transistor (eg, Figure 3J Er21 in) is formed by a through hole (eg, Figure 3J v10 in ) is connected to the corresponding active layer of the corresponding second switching transistor (eg, Figure 3J ACTr2 in ).

[0072] Figure 3K is along Figure 2A Cross-sectional view of the K-K' line in Fig. Figure 2A , Figure 2B , Figure 2E and Figure 3K In some embodiments, the corresponding second electrode of the corresponding second switch transistor (eg, Figure 3K Er22 in) is formed by a through hole (eg, Figure 3K v11 in ) is connected to the corresponding active layer of the corresponding second switching transistor (eg, Figure 3K ACTr2 in ).

[0073] In another aspect, the present disclosure also provides a display panel. Figure 4A 4 is a schematic diagram of the structure of a display panel according to some embodiments of the present disclosure. Referring to FIG. 4 , in some embodiments, the display panel includes a test circuit described herein or manufactured by the method described herein, and M array substrate signal lines SL respectively connected to the second electrodes of the M second switch transistors. Optionally, the M array substrate signal lines are M data lines. In some embodiments, the display panel further includes a plurality of second array substrate signal lines SL2. Optionally, the plurality of second array substrate signal lines SL2 are a plurality of gate lines.

[0074] Various embodiments of the present display panel may be practiced. Figure 4B Detailed structures in the display area of ​​the display panel in some embodiments of the present disclosure are shown. Figure 4BIn some embodiments, the display panel includes a base substrate BS (for example, a flexible base substrate) in the display area; an active layer ACT of a corresponding one of a plurality of thin film transistors TFT on the base substrate BS; a gate insulating layer GI located on a side of the active layer ACT away from the base substrate BS; a gate G and a first capacitor electrode Ce1 (both are part of a first gate metal layer) located on a side of the gate insulating layer GI away from the base substrate BS; an insulating layer IN located on a side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; and a gate electrode GI located on a side of the insulating layer IN away from the gate insulating layer GI. A second capacitor electrode Ce2 (a part of a second gate metal layer); an interlayer dielectric layer ILD located on a side of the second capacitor electrode Ce2 away from the gate insulating layer GI; a source electrode S and a drain electrode D (a part of a first SD metal layer) located on a side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a planarization layer PLN located on a side of the source electrode S and the drain electrode D away from the interlayer dielectric layer ILD; a pixel defining layer PDL, the pixel defining layer PDL defining a sub-pixel opening and located on a side of the planarization layer PLN away from the base substrate BS; and a light emitting element LE in the sub-pixel opening. The light emitting element LE includes: an anode AD located on a side of the planarization layer PLN away from the interlayer dielectric layer ILD; a light emitting layer EL located on a side of the anode AD away from the planarization layer PLN; and a cathode layer CD located on a side of the light emitting layer EL away from the anode AD. The display panel also includes an encapsulation layer EN in the display area, which encapsulates a dummy light emitting element DLE and is located on a side of the cathode layer CD away from the base substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 located on a side of the cathode layer CD away from the base substrate BS, an organic encapsulation sublayer IJP located on a side of the first inorganic encapsulation sublayer CVD1 away from the base substrate BS, and a second inorganic encapsulation sublayer CVD2 located on a side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display panel further includes a buffer layer BUF located on a side of the encapsulation layer EN away from the base substrate BS in the display area; a plurality of second electrode bridges BR2 located on a side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI located on a side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 located on a side of the touch insulating layer TI away from the buffer layer BUF; and an outer coating layer OC located on a side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.

[0075] Figure 4C Detailed structures in the display area of ​​the display panel in some embodiments of the present disclosure are shown. Figure 4CIn some embodiments, the display panel includes a base substrate BS (for example, a flexible base substrate) in the display area; an active layer ACT of a corresponding one of a plurality of thin film transistors TFT on the base substrate BS; a gate insulating layer GI located on a side of the active layer ACT away from the base substrate BS; a gate G and a first capacitor electrode Ce1 (both are part of a first gate metal layer) located on a side of the gate insulating layer GI away from the base substrate BS; an insulating layer IN located on a side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (part of a second gate metal layer) located on a side of the insulating layer IN away from the gate insulating layer GI; and an interlayer dielectric layer ILD located on a side of the second capacitor electrode Ce2 away from the gate insulating layer GI. ; a source electrode S and a drain electrode D (a part of the first SD metal layer) located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a passivation layer PVX located on the side of the source electrode S and the drain electrode D away from the interlayer dielectric layer ILD; a first planarization layer PLN1 located on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; a second planarization layer PLN2 located on the side of the first planarization layer PLN1 away from the passivation layer PVX; a relay electrode RE (a part of the second SD metal layer) located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a pixel defining layer PDL, which defines a sub-pixel opening and is located on the side of the second planarization layer PLN2 away from the base substrate BS; and a light emitting element LE in the sub-pixel opening. The light emitting element LE includes: an anode AD located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light emitting layer EL located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD located on the side of the light emitting layer EL away from the anode AD. The display panel further includes an encapsulation layer EN in the display area, which encapsulates the dummy light emitting element DLE and is located on the side of the cathode layer CD away from the base substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the base substrate BS, an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the base substrate BS, and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display panel further includes a buffer layer BUF located on the side of the encapsulation layer EN away from the base substrate BS; a plurality of second electrode bridges BR2 located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 located on the side of the touch insulating layer TI away from the buffer layer BUF; and an outer coating layer OC located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.Optionally, the display panel does not include the passivation layer PVX in the display area, for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1 .

[0076] exist Figure 4B and Figure 4C In the figure, it is shown that FIG. 2B to FIG. 2F For example, the display panel includes a semiconductor material layer SML (corresponding to Figure 2B ), the first conductive layer Gate1 (corresponding to Figure 2C ), the second conductive layer Gate2 (corresponding to Figure 2D )、the first signal line layer SLL1 (corresponding to Figure 2E ) and the second signal line layer SLL2 (corresponding to Figure 2F ).

[0077] and Figure 4B Compared to the embodiment shown in Figure 4C The embodiment shown in comprises at least one additional layer, for example a passivation layer PVX. FIG. 3A to FIG. 3K An embodiment without the passivation layer PVX is described. However, the present disclosure may be implemented in various display panels of different types. Figure 4D is a cross-sectional view of a test circuit according to some embodiments of the present disclosure. Figure 4D Corresponds to Figure 3G , except that the display panel includes additional layers. Figure 4D In some embodiments, the corresponding second sublayer of the corresponding test signal line (eg, Figure 4D TSL1-2 in the planarization layer PLN2) through a through hole (eg, Figure 4D v7' in the figure) is connected to the corresponding first sublayer of the corresponding test signal line (for example, Figure 4D TSL1-1 in .

[0078] In another aspect, the present disclosure also provides a method for testing an array substrate. In some embodiments, the method includes providing a test circuit, which includes N test signal lines, N is an integer greater than 1; N first control signal lines; N second control signal lines; M first switch transistors, M is an integer greater than N; and M second switch transistors; connecting the second electrode of the mth first switch transistor to the first electrode of the mth second switch transistor, 1≤m≤M; connecting the nth test signal line to the first electrode of the (kN+n)th first switch transistor, 1≤n≤N, 0≤k<M / N; connecting the nth first control signal line to the (kN+n)th first switch transistor. 2 +((n-1)*N)+1) to (kN 2the gates of the first switching transistors of (+n*N), where 0≤k<M / N; connecting the n-th second control signal line to the gate of the (kN + n)-th second switching transistor; and connecting the second electrode of the m-th second switching transistor to the m-th array substrate signal line.

[0079] In some embodiments, N is the total number of sub-pixels of different colors in the array substrate, and the array substrate includes M array substrate signal lines respectively connected to the second electrodes of the M second switching transistors. In one example, the array substrate includes red sub-pixels, green sub-pixels, and blue sub-pixels, and N = 3. In another example, the array substrate includes red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, and N = 4.

[0080] In one example, N = 2. In another example, N = 3. In another example, N = 4. In another example, N = 5. In another example, N = 6.

[0081] In some embodiments, the test is performed in a cycle including N periods. The method includes, in the n-th period, providing a conduction voltage signal to the n-th first control signal line, while providing a cut-off voltage signal to the first control signal lines other than the n-th first control signal line, providing a conduction voltage signal to the N second control signal lines respectively, and providing a test voltage signal to the N test signal lines respectively, so as to provide the test voltage signal to the array substrate signal lines respectively, and the array substrate signal lines are respectively connected to the second electrodes of the (kN 2 +((n - 1)*N)+1)th to the (kN 2 +n*N)th second switching transistors.

[0082] In one example, N = 3; and the cycle includes a first period, a second period, and a third period. Figure 5 is a timing diagram of operating a test circuit in some embodiments according to the present disclosure.

[0083] Refer to Figure 1B and Figure 5, in a first time period, the method includes providing an on-voltage signal ON to a first first control signal line CSL1-1, and providing an off-voltage signal OFF to a second first control signal line CSL1-2 and a third first control signal line CSL1-3, providing the on-voltage signal to the first second control signal line CSL2-1, the second second control signal line CSL2-2 and the third second control signal line CSL2-3, respectively, and providing the test voltage signal to the first test signal line TSL1, the second test signal line TSL2 and the third test signal line TSL3, respectively, so as to provide the test voltage signal to the array substrate signal line, respectively, which is connected to the second electrode of the first second switch transistor SW2-1, the second second switch transistor SW2-2 and the third second switch transistor SW2-3, respectively.

[0084] Reference Figure 1B and Figure 5 , in the second time period, the method includes providing a turn-on voltage signal ON to the second first control signal line CSL1-2, and providing a turn-off voltage signal OFF to the first first control signal line CSL1-1 and the third first control signal line CSL1-3, providing the turn-on voltage signal to the first second control signal line CSL2-1, the second second control signal line CSL2-2 and the third second control signal line CSL2-3, respectively, and providing the test voltage signal to the first test signal line TSL1, the second test signal line TSL2 and the third test signal line TSL3, respectively, so as to provide the test voltage signal to the array substrate signal line, respectively, which is connected to the second electrodes of the fourth second switch transistor SW2-4, the fifth second switch transistor SW2-5 and the sixth second switch transistor SW2-6, respectively.

[0085] Reference Figure 1B and Figure 5 , in the third time period, the method includes providing a turn-on voltage signal ON to the third first control signal line CSL1-3, and providing a turn-off voltage signal OFF to the first first control signal line CSL1-1 and the second first control signal line CSL1-2, providing the turn-on voltage signal to the first second control signal line CSL2-1, the second second control signal line CSL2-2 and the third second control signal line CSL2-3, respectively, and providing the test voltage signal to the first test signal line TSL1, the second test signal line TSL2 and the third test signal line TSL3, respectively, so as to provide the test voltage signal to the array substrate signal line, respectively, which is connected to the second electrodes of the seventh second switch transistor SW2-7, the eighth second switch transistor SW2-8 and the ninth second switch transistor SW2-9, respectively.

[0086] In some embodiments, the test is performed in a cycle including N time periods, and each time period includes N sub-time periods. In some embodiments, the method includes: in the nth time period, providing a turn-on voltage signal to the nth second control signal line, and providing a turn-off voltage signal to the second control signal line other than the nth second control signal line, and providing the test voltage signal to the N test signal lines respectively. Optionally, in the nth sub-time period of the nth time period, providing a turn-on voltage signal to the nth first control signal line, and providing a turn-off voltage signal to the first control signal line other than the nth first control signal line, so that the test voltage signal is provided to the array substrate signal line, which is connected to the (kNth) first control signal line. 2 +((n-1)*N)+n) second electrodes of the second switching transistors.

[0087] In some embodiments, the cycle includes a first period, a second period, and a third period. Optionally, the first period includes a first first sub-period, a second first sub-period, and a third first sub-period. Optionally, the second period includes a first second sub-period, a second second sub-period, and a third second sub-period. Optionally, the third period includes a first third sub-period, a second third sub-period, and a third third sub-period.

[0088] In some embodiments, in the first period, the method includes providing a turn-on voltage signal to the first second control signal line, and providing a turn-off voltage signal to the second second control signal line and the third second control signal line, and providing the test voltage signal to the first test signal line, the second test signal line and the third test signal line respectively. Optionally, in the first first sub-period, the method includes providing a turn-on voltage signal to the first first control signal line, and providing a turn-off voltage signal to the second first control signal line and the third first control signal line, so that the test voltage signal is provided to the array substrate signal line connected to the second electrode of the first second switch transistor. Optionally, in the second first sub-period, the method includes providing a turn-on voltage signal to the second first control signal line, and providing a turn-off voltage signal to the first first control signal line and the third first control signal line, so that the test voltage signal is provided to the array substrate signal line connected to the second electrode of the fourth second switch transistor. Optionally, in the third first sub-period, the method includes providing an on-voltage signal to the third first control signal line, and simultaneously providing an off-voltage signal to the first first control signal line and the second first control signal, thereby providing the test voltage signal to the array substrate signal line connected to the second electrode of the seventh second switching transistor, respectively.

[0089] In some embodiments, in the second period, the method includes providing a turn-on voltage signal to the second second control signal line, and providing a turn-off voltage signal to the first second control signal line and the third second control signal line, and providing the test voltage signal to the first test signal line, the second test signal line, and the third test signal line, respectively. Optionally, in the first second sub-period, the method includes providing a turn-on voltage signal to the first first control signal line, and providing a turn-off voltage signal to the second first control signal line and the third first control signal line, so that the test voltage signal is provided to the array substrate signal line connected to the second electrode of the second second switch transistor, respectively. Optionally, in the second second sub-period, the method includes providing a turn-on voltage signal to the second first control signal line, and providing a turn-off voltage signal to the first first control signal line and the third first control signal line, so that the test voltage signal is provided to the array substrate signal line connected to the second electrode of the fifth second switch transistor, respectively. Optionally, in the third second sub-period, the method includes providing an on-voltage signal to the third first control signal line, and simultaneously providing an off-voltage signal to the first first control signal line and the second first control signal line, thereby providing the test voltage signal to the array substrate signal line connected to the second electrode of the eighth second switching transistor, respectively.

[0090] In some embodiments, in the third period, the method includes providing a turn-on voltage signal to the third second control signal line, and providing a turn-off voltage signal to the first second control signal line and the second second control signal line, and providing the test voltage signal to the first test signal line, the second test signal line and the third test signal line respectively. Optionally, in the first third sub-period, the method includes providing a turn-on voltage signal to the first first control signal line, and providing a turn-off voltage signal to the second first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the third second switch transistor respectively. Optionally, in the second third sub-period, the method includes providing a turn-on voltage signal to the second first control signal line, and providing a turn-off voltage signal to the first first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the sixth second switch transistor respectively. Optionally, in the third sub-period, the method includes providing an on-voltage signal to the third first control signal line, and simultaneously providing an off-voltage signal to the first first control signal line and the second first control signal line, thereby providing the test voltage signal to the array substrate signal line connected to the second electrode of the ninth second switching transistor, respectively.

[0091] In some embodiments, the method for testing an array substrate can be implemented in an aging process of an array substrate having an OLED device. During the aging process, a large stress is applied to the array substrate, especially when a large current is required to test a high-resolution array substrate. A large current often causes the circuit to burn out or the circuit to not respond. The test circuit and the method for testing an array substrate greatly improve the flexibility of testing the array substrate, and effectively avoid the circuit burning out or the circuit not responding when a large current is used during the test process.

[0092] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described in order to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising: N test signal lines, where N is an integer greater than 1; N first control signal lines; N second control signal lines; M first switch transistors, where M is an integer greater than N; as well as M second switching transistors; wherein the second electrode of the mth first switch transistor is connected to the first electrode of the mth second switch transistor, 1≤m≤M; The nth test signal line is connected to the first electrode of the kN+nth first switch transistor, 1≤n≤N, 0≤k<M / N; The nth first control signal line is connected to the kNth 2 +((n-1)*N)+1 to kNth 2 +n*N gates of the first switch transistors, 0≤k <M / N; The nth second control signal line is connected to the gate of the kN+nth second switch transistor; as well as The second electrode of the mth second switch transistor is connected to the mth array substrate signal line.

2. The array substrate according to claim 1, wherein: M is an integer multiple of N.

3. The array substrate according to claim 1, wherein: N is the total number of sub-pixels of different colors in the array substrate, and the array substrate includes M array substrate signal lines respectively connected to the second electrodes of the M second switch transistors.

4. The array substrate according to any one of claims 1 to 3, wherein: N＝3。 5. The array substrate according to claim 4, comprising: a first first control signal line, a second first control signal line, and a third first control signal line; a first second control signal line, a second second control signal line, and a third second control signal line; a first test signal line, a second test signal line, and a third test signal line; a first first switch transistor, a second first switch transistor, a third first switch transistor, a fourth first switch transistor, a fifth first switch transistor, a sixth first switch transistor, a seventh first switch transistor, an eighth first switch transistor and a ninth first switch transistor; as well as a first second switching transistor, a second second switching transistor, a third second switching transistor, a fourth second switching transistor, a fifth second switching transistor, a sixth second switching transistor, a seventh second switching transistor, an eighth second switching transistor and a ninth second switching transistor; Wherein, the first test signal line is connected to the first electrodes of the first first switch transistor, the fourth first switch transistor and the seventh first switch transistor; The second test signal line is connected to the first electrodes of the second first switch transistor, the fifth first switch transistor and the eighth first switch transistor; The third test signal line is connected to the first electrodes of the third first switch transistor, the sixth first switch transistor and the ninth first switch transistor; The first first control signal line is connected to the gates of the first first switch transistor, the second first switch transistor and the third first switch transistor; The second first control signal line is connected to the gates of the fourth first switch transistor, the fifth first switch transistor and the sixth first switch transistor; The third first control signal line is connected to the gates of the seventh first switch transistor, the eighth first switch transistor and the ninth first switch transistor; The first second control signal line is connected to the gates of the first second switch transistor, the fourth second switch transistor and the seventh second switch transistor; The second second control signal line is connected to gates of the second second switching transistor, the fifth second switching transistor, and the eighth second switching transistor; and The third second control signal line is connected to gates of the third second switching transistor, the sixth second switching transistor, and the ninth second switching transistor.

6. The array substrate according to any one of claims 1 to 3, comprising: A semiconductor material layer, wherein the semiconductor material layer includes active layers of the M first switch transistors and the M second switch transistors; A first conductive layer, wherein the first conductive layer includes gates of the M first switch transistors and the M second switch transistors; a second conductive layer, wherein the second conductive layer comprises M first connecting lines and M second connecting lines, the M first connecting lines respectively connecting the first electrodes of the M first switch transistors to the corresponding test signal lines, and the M second connecting lines respectively connecting the second electrodes of the M first switch transistors to the first electrodes of the M second switch transistors; and A first signal line layer, wherein the first signal line layer includes a first sublayer of the N test signal lines, the N first control signal lines, the N second control signal lines, the first electrodes and the second electrodes of the M first switch transistors, and the first electrodes and the second electrodes of the M second switch transistors.

7. The array substrate according to claim 6, further comprising: an insulating layer, located between the first conductive layer and the second conductive layer; an interlayer dielectric layer, located between the second conductive layer and the first signal line layer; as well as A planarization layer, which is located on a side of the first signal line layer away from the interlayer dielectric layer; wherein a corresponding first electrode of a corresponding first switch transistor is connected to a corresponding first connection line through a through hole extending through the interlayer dielectric layer; The corresponding first sub-layers of the corresponding test signal lines are respectively connected to the corresponding first connection lines through vias extending through the interlayer dielectric layer; as well as The corresponding first control signal lines are connected to the corresponding gates of the corresponding first switch transistors through vias extending through the interlayer dielectric layer and the insulating layer, respectively.

8. The array substrate according to claim 7, wherein: a respective second electrode of the respective first switch transistor connected to a respective second connection line via a via extending through the interlayer dielectric layer; a respective first electrode of a respective second switch transistor connected to the respective second connection line through a via extending through the interlayer dielectric layer; and The corresponding second control signal lines are connected to the corresponding gates of the corresponding second switch transistors through vias extending through the interlayer dielectric layer and the insulating layer.

9. The array substrate according to claim 7, further comprising: A second signal line layer, wherein the second signal line layer includes a second sub-layer of N test signal lines; and a planarization layer located between the first signal line layer and the second signal line layer; The corresponding second sub-layer of the corresponding test signal line is connected to the corresponding first sub-layer of the corresponding test signal line through a through hole extending through the planarization layer.

10. The array substrate according to claim 7, wherein: a respective first electrode of a respective first switch transistor connected to a respective active layer of the respective first switch transistor through a via extending through the interlayer dielectric layer and the insulating layer; a respective second electrode of a respective first switch transistor connected to the respective active layer of the respective first switch transistor through a via extending through the interlayer dielectric layer and the insulating layer; a respective first electrode of a respective second switch transistor connected to a respective active layer of the respective second switch transistor through a via extending through the interlayer dielectric layer and the insulating layer; as well as A respective second electrode of a respective second switch transistor is connected to the respective active layer of the respective second switch transistor through a via extending through the interlayer dielectric layer and the insulating layer. 11 . A display panel, comprising the array substrate according to claim 1 , and M array substrate signal lines respectively connected to the second electrodes of the M second switch transistors.

12. The display panel according to claim 11, wherein: The M array substrate signal lines are M data lines.

13. A method for testing an array substrate, comprising: Providing a test circuit, which includes N test signal lines, where N is an integer greater than 1; N first control signal lines; N second control signal lines; M first switch transistors, where M is an integer greater than N; and M second switch transistors; Connecting the second electrode of the mth first switch transistor to the first electrode of the mth second switch transistor, 1≤m≤M; Connecting the nth test signal line to the first electrode of the kN+nth first switch transistor, 1≤n≤N, 0≤k<M / N; Connect the nth first control signal line to the kNth 2 +((n-1)*N)+1 to kNth 2 +n*N gates of the first switch transistors, 0≤k <M / N; Connecting the nth second control signal line to the gate of the (kN+n)th second switch transistor; as well as The second electrode of the mth second switch transistor is connected to the mth array substrate signal line.

14. The method according to claim 13, wherein: The test is performed in a loop comprising N time periods; The method includes, in an nth time period, providing a conduction voltage signal to the nth first control signal line, and providing a cutoff voltage signal to the first control signal line other than the nth first control signal line, providing the conduction voltage signal to the N second control signal lines respectively, and providing the test voltage signal to the N test signal lines respectively, thereby providing the test voltage signal to the array substrate signal lines respectively, and the array substrate signal lines are respectively connected to the kNth 2 +((n-1)*N)+1 to kNth 2 +n*N second electrodes of the second switching transistors.

15. The method according to claim 14, wherein: N = 3; and The cycle includes a first period, a second period, and a third period.

16. The method according to claim 15, wherein: In the first period, the method includes providing a turn-on voltage signal to a first first control signal line, and providing a turn-off voltage signal to a second first control signal line and a third first control signal line, respectively providing the turn-on voltage signal to a first second control signal line, a second second control signal line and a third second control signal line, and respectively providing a test voltage signal to a first test signal line, a second test signal line and a third test signal line, so as to respectively provide the test voltage signal to an array substrate signal line, which is respectively connected to a second electrode of a first second switch transistor, a second second switch transistor and a third second switch transistor; In the second period, the method includes providing a turn-on voltage signal to the second first control signal line, and providing a turn-off voltage signal to the first first control signal line and the third first control signal line, respectively providing the turn-on voltage signal to the first second control signal line, the second second control signal line and the third second control signal line, and respectively providing a test voltage signal to the first test signal line, the second test signal line and the third test signal line, so as to respectively provide the test voltage signal to the array substrate signal line, which is respectively connected to the second electrode of the fourth second switch transistor, the fifth second switch transistor and the sixth second switch transistor; as well as In the third time period, the method includes providing a turn-on voltage signal to the third first control signal line, and simultaneously providing a turn-off voltage signal to the first first control signal line and the second first control signal line, providing the turn-on voltage signal to the first second control signal line, the second second control signal line and the third second control signal line, respectively, and providing a test voltage signal to the first test signal line, the second test signal line and the third test signal line, respectively, so as to provide the test voltage signal to the array substrate signal line, respectively, which is connected to the second electrodes of the seventh second switching transistor, the eighth second switching transistor and the ninth second switching transistor, respectively.

17. The method according to claim 13, wherein: The test is performed in a cycle including N time periods, each time period including N sub-time periods; The method comprises: in an nth time period, providing a turn-on voltage signal to the nth second control signal line, and providing a turn-off voltage signal to the second control signal lines other than the nth second control signal line, and providing a test voltage signal to the N test signal lines respectively; In the nth sub-period of the nth period, a turn-on voltage signal is provided to the nth first control signal line, and a turn-off voltage signal is provided to the first control signal line other than the nth first control signal line, so that the test voltage signal is provided to the array substrate signal line respectively, and the array substrate signal line is connected to the kNth 2 +((n-1)*N)+n second electrodes of the second switching transistors.

18. The method according to claim 17, wherein: N＝3； The cycle includes a first period, a second period and a third period; The first period includes a first first sub-period, a second first sub-period and a third first sub-period; The second period includes a first second sub-period, a second second sub-period and a third second sub-period; and The third period includes a first third sub-period, a second third sub-period and a third third sub-period.

19. The method according to claim 18, wherein: In the first period, the method includes providing an on-voltage signal to a first second control signal line, providing an off-voltage signal to a second second control signal line and a third second control signal line, and providing a test voltage signal to a first test signal line, a second test signal line, and a third test signal line, respectively; In the first first sub-period, the method includes providing an on-voltage signal to a first first control signal line, and providing an off-voltage signal to a second first control signal line and a third first control signal line, so that the test voltage signal is provided to the array substrate signal line connected to the second electrode of the first second switch transistor, respectively; In the second first sub-period, the method includes providing an on-voltage signal to the second first control signal line, and providing an off-voltage signal to the first first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the fourth second switch transistor respectively; In the third first sub-period, the method includes providing an on-voltage signal to the third first control signal line, and providing an off-voltage signal to the first first control signal line and the second first control signal, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the seventh second switch transistor, respectively; In the second period, the method includes providing an on-voltage signal to the second second control signal line, providing an off-voltage signal to the first second control signal line and the third second control signal line, and providing a test voltage signal to the first test signal line, the second test signal line, and the third test signal line, respectively; In the first second sub-period, the method includes providing an on-voltage signal to the first first control signal line, and providing an off-voltage signal to the second first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the second second switch transistor respectively; In the second second sub-period, the method includes providing an on-voltage signal to the second first control signal line, and providing an off-voltage signal to the first first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the fifth second switch transistor respectively; In the third second sub-period, the method includes providing an on-voltage signal to the third first control signal line, and providing an off-voltage signal to the first first control signal line and the second first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the eighth second switch transistor respectively; In the third period, the method includes providing an on-voltage signal to the third second control signal line, providing an off-voltage signal to the first second control signal line and the second second control signal line, and providing a test voltage signal to the first test signal line, the second test signal line and the third test signal line respectively; In the first third sub-period, the method includes providing an on-voltage signal to the first first control signal line, and providing an off-voltage signal to the second first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the third second switch transistor respectively; In the second third sub-period, the method includes providing an on-voltage signal to the second first control signal line, and providing an off-voltage signal to the first first control signal line and the third first control signal line, so as to provide the test voltage signal to the array substrate signal line connected to the second electrode of the sixth second switch transistor respectively; as well as In the third third sub-period, the method includes providing an on-voltage signal to the third first control signal line, and simultaneously providing an off-voltage signal to the first first control signal line and the second first control signal line, thereby providing the test voltage signal to the array substrate signal line connected to the second electrode of the ninth second switching transistor, respectively.

20. The method according to claim 13, wherein: The array substrate further includes M array substrate signal lines respectively connected to the second electrodes of the M second switch transistors, wherein the M array substrate signal lines are M data lines.

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