Array substrate, mask plate and display panel

Abstract

The array substrate disclosed in the present invention comprises: a substrate and a first conductive layer and a second conductive layer sequentially stacked on the substrate, the orthographic projection of the first conductive layer on the substrate and the orthographic projection of the second conductive layer on the substrate having an overlapping area, the first conductive layer and the second conductive layer in the overlapping area forming a first conductive pattern, the first conductive pattern having a pattern extending along a first direction, the first conductive layer located outside the overlapping area comprising a second conductive pattern and a third conductive pattern, the second conductive pattern and the third conductive pattern having a gap therebetween, the second conductive pattern and the third conductive pattern being respectively connected to the first conductive pattern, the second conductive pattern and the third conductive pattern being located on the same side of the first conductive pattern and extending along the second direction, the first spacing between the first areas of the second conductive pattern and the third conductive pattern close to the first conductive pattern being greater than the second spacing between the second areas of the second conductive pattern and the third conductive pattern far from the first conductive pattern.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and specifically relate to an array substrate, a mask plate, and a display panel. Background Art

[0002] As people's requirements for the image quality of LCD products increase, the screen resolution needs to be improved. Therefore, without changing the size of the display area, the pixels tend to become smaller and smaller. On the other hand, the transmittance requirement must be taken into account, so the line width and line spacing on the pixel layout will be reduced. This can easily lead to some short circuit defects during motherboard production. Summary of the invention

[0003] Embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, a mask plate, and a display panel.

[0004] In a first aspect, an embodiment of the present disclosure provides an array substrate, comprising: a substrate and a first conductive layer and a second conductive layer sequentially stacked on the substrate, wherein an orthographic projection of the first conductive layer on the substrate and an orthographic projection of the second conductive layer on the substrate have an overlapping area, the first conductive layer and the second conductive layer in the overlapping area constitute a first conductive pattern, the first conductive pattern has a pattern extending along a first direction, the first conductive layer located outside the overlapping area comprises a second conductive pattern and a third conductive pattern, there is a gap between the second conductive pattern and the third conductive pattern, and the second conductive pattern and the third conductive pattern are respectively connected to the first conductive pattern, the second conductive pattern and the third conductive pattern are located on the same side of the first conductive pattern and extend along a second direction, a first spacing between first regions of the second conductive pattern and the third conductive pattern close to the first conductive pattern is greater than a second spacing between second regions of the second conductive pattern and the third conductive pattern away from the first conductive pattern, the spacing area between the first regions of the second conductive pattern and the third conductive pattern comprises a first sub-region and a second sub-region, the first sub-region and the second sub-region are arranged sequentially away from the first conductive pattern along the second direction, and the orthographic projection shape of the second sub-region on the substrate is a trapezoid;

[0005] The shorter bottom side of the second sub-region is farther away from the first conductive pattern than the longer bottom side of the second sub-region.

[0006] In some embodiments, the orthographic projection shape of the first sub-region on the substrate is a rectangle.

[0007] In some embodiments, edge lines on opposite sides of the spacing region between the second conductive pattern and the first region of the third conductive pattern are semicircular arc shapes.

[0008] In some embodiments, the second conductive pattern and the third conductive pattern have the same shape and size, and the second conductive pattern and the third conductive pattern are mirror-symmetrical about a center line of the interval.

[0009] In some embodiments, a size ratio between the first region and the second region along the second direction ranges from 1 / 20 to 1.

[0010] In some embodiments, the size ratio of the second spacing to the first spacing ranges from X / (X+L' / 5) to X / (X+L' / 10), where X is the size of the second spacing, and L' is the width of the second region of the second conductive pattern and the third conductive pattern along the first direction.

[0011] In some embodiments, widths of the first regions of the second conductive pattern and the third conductive pattern along the first direction are both in a range of 9L' / 10 to 19L' / 20.

[0012] In some embodiments, a dimension of the first region along the second direction is greater than or equal to 5 μm.

[0013] In some embodiments, the first pitch is greater than or equal to 20 μm.

[0014] In some embodiments, the second pitch has a size of 16 μm, and the first pitch has a size of 23 μm.

[0015] In some embodiments, the first conductive pattern is a common electrode signal line, and the second conductive pattern and the third conductive pattern are common electrodes respectively located in adjacent pixel areas;

[0016] The array substrate further comprises an insulating layer and a data line, wherein the insulating layer and the data line are sequentially stacked on a side of the second conductive layer away from the substrate;

[0017] The orthographic projection of the insulating layer on the substrate covers the entire substrate, and the orthographic projection of the data line on the substrate is located in the spacing area between the second conductive pattern and the third conductive pattern, and extends to intersect with the first conductive pattern.

[0018] In a second aspect, an embodiment of the present disclosure provides a display panel, comprising the array substrate and the opposite substrate in the above embodiment.

[0019] In a third aspect, an embodiment of the present disclosure provides a mask plate, comprising a first semi-transparent area, a second semi-transparent area and a third area, the third area having a pattern extending along a first direction, a gap between the first semi-transparent area and the second semi-transparent area, and the first semi-transparent area and the second semi-transparent area are respectively connected to the third area, the first semi-transparent area and the second semi-transparent area are located on the same side of the third area and extend along a second direction, and a first spacing between first parts of the first semi-transparent area and the second semi-transparent area close to the third area is greater than a second spacing between second parts of the two away from the third area.

[0020] In some embodiments, a spacing area between the first semi-light-transmitting area and the first portion of the second semi-light-transmitting area is rectangular in shape.

[0021] In some embodiments, edge lines on opposite sides of the spacing area between the first semi-light-transmitting area and the first portion of the second semi-light-transmitting area are in the shape of semicircular arcs.

[0022] In some embodiments, the first semi-light-transmitting area and the second semi-light-transmitting area have the same shape and size, and the first semi-light-transmitting area and the second semi-light-transmitting area are mirror-symmetrical with the center line of the interval as the axis.

[0023] In some embodiments, a size ratio of the first portion to the second portion along the second direction ranges from 1 / 20 to 1.

[0024] In some embodiments, the size ratio of the second spacing to the first spacing is in the range of X / (X+L / 5) to X / (X+L / 10), wherein X is the size of the second spacing, and L is the width of the first semi-transparent area and the second part of the second semi-transparent area along the first direction.

[0025] In some embodiments, widths of the first portion of the first semi-light-transmitting area and the first portion of the second semi-light-transmitting area along the first direction are both in a range of 9L / 10 to 19L / 20.

[0026] In some embodiments, a dimension of the first portion along the second direction is greater than or equal to 5 μm.

[0027] In some embodiments, a size of the first spacing is greater than or equal to 20 μm.

[0028] In some embodiments, the second pitch has a size of 16 μm, and the first pitch has a size of 23 μm.

[0029] In a fourth aspect, an embodiment of the present disclosure provides a method for preparing an array substrate, comprising:

[0030] sequentially forming a first conductive layer film and a second conductive layer film on a substrate, and forming a photoresist on the second conductive layer film;

[0031] The photoresist-coated substrate is exposed by using the mask plate, and after development, the photoresist in the substrate area corresponding to the interval area between the first semi-light-transmitting area and the second semi-light-transmitting area is removed, the photoresist in the substrate area corresponding to the first semi-light-transmitting area and the second semi-light-transmitting area is partially retained, and the photoresist in the substrate area corresponding to the third area is completely retained;

[0032] Etching and removing the second conductive layer film and the first conductive layer film in the substrate region corresponding to the interval region between the first semi-light-transmitting region and the second semi-light-transmitting region;

[0033] Completely removing the photoresist corresponding to the first semi-light-transmitting area and the second semi-light-transmitting area, and removing a portion of the completely retained photoresist corresponding to the third area;

[0034] Etching and removing the second conductive layer film in the substrate area corresponding to the first semi-light-transmitting area and the second semi-light-transmitting area to form a second conductive pattern and a third conductive pattern;

[0035] The remaining portion of the photoresist that is completely retained corresponding to the third region is removed to form a first conductive pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0037] Figure 1a A top view of the local structure of a semi-transparent film mask;

[0038] Figure 1b To adopt Figure 1a A top view of a local structure of an array substrate formed by exposure using a semi-transparent film mask;

[0039] Figure 2 A pixel design plane top view of an ADS type array substrate and an enlarged view of point A therein;

[0040] Figure 3 To adopt Figure 1a The semi-transparent film mask is exposed and etched to form Figure 2 A schematic diagram of the process of common electrodes and common electrode signal lines on the array substrate, Figure 3 During the preparation process Figure 2 Partial cross-sectional view of the PP section line at A in the middle;

[0041] Figure 4 A top view of a local structure of a mask plate in an exemplary embodiment of the present disclosure;

[0042] Figure 5 A top view of a local structure of another mask plate in an exemplary embodiment of the present disclosure;

[0043] Figure 6 In the exemplary embodiment of the present disclosure, Figure 4 A top view of a local structure of an array substrate formed by exposing the mask plate in FIG.

[0044] Figure 7 For along Figure 6 Partial section view of the SS section line;

[0045] Figure 8 In the exemplary embodiment of the present disclosure, Figure 5 A top view of the local structure of the array substrate formed by exposing the mask plate in FIG.

[0046] The accompanying drawings are denoted as follows:

[0047] 1. First semi-transparent area; 2. Second semi-transparent area; 3. Third area; 101. First part; 102. Second part; 4. Substrate; 5. First conductive layer; 6. Second conductive layer; 7. First conductive pattern; 8. Second conductive pattern; 9. Third conductive pattern; 201. First area; 202. Second area; 10. Semi-transparent film area; 11. Shading film area; 12. Common electrode; 13. Common electrode signal line; 14. Transparent conductive film layer; 15. Gate metal film layer; 16. PR glue; 17. Semi-transparent film mask; 18. Completely transparent area; 19. Gate; 20. Gate line; 21. Fourth area; 22. Data line; E. First direction; F. Second direction. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a mask plate, an array substrate, a preparation method thereof, and a display panel provided by the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0049] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as being limited to the embodiments set forth in the present disclosure. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0050] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions, but are not intended to be limiting.

[0051] For 0+X Mask process products, 0 refers to HGA Mask (Half tone gate Mask, semi-transparent mask), which is used to expose and simultaneously obtain the patterns of the transparent common electrode and opaque common electrode lines of the ADS array substrate. Figure 1a and Figure 1b As shown, on the HGA Mask, the "three-sided surrounded by mountains" portion composed of the semi-transparent film area 10 (Half tone mask, HTM) / shading film area 11 (Cr, chrome film area) / semi-transparent film area 10 (Half tone mask, HTM) is used to simultaneously expose and form adjacent light-transmitting common electrodes 12 and opaque common electrode signal lines 13. In addition, the shading film area 11 is also used to simultaneously expose and form gates 19 and gate lines 20. The completely transparent area 18 surrounded by the semi-transparent film area 10 and the shading film area 11 is used to expose and form the spacing area between adjacent common electrodes 12, the spacing area between the common electrode signal lines 13 and the gate lines 20, and other areas where no conductive patterns need to be formed. In the process of simultaneously forming the common electrode 12 and the common electrode signal line 13 by one exposure, two wet etching processes are required. After the wet etching, the etching solution is likely to remain in the "three-sided surrounded by mountains" area where the light-transmitting conductive film layer and the light-opaque conductive film layer overlap each other, corroding the edge of the light-opaque conductive film layer located on the upper layer in the area to form conductive metal particles. Since the spacing z between adjacent semi-permeable film areas 10 on adjacent semi-permeable film mask plates is small, the spacing z' between adjacent common electrodes 12 is also small, which easily leads to the rapid accumulation of conductive metal particles in the narrow "three-sided surrounded by mountains" area, so that the subsequently deposited conductive film layer (such as the data line film layer) is likely to short-circuit with the light-opaque conductive film layer in this area.

[0052] For example, for ADS (Advanced Super Dimension Switch) display products, Figure 2It is a conventional pixel design plan view of an array substrate in the related art. The common electrode 12 and the common electrode signal line 13 formed on the substrate earlier are formed simultaneously by a one-step patterning process, wherein the common electrode 12 is composed of a transparent conductive material layer located at a relatively bottom layer, and the common electrode signal line 13 is composed of a laminated layer of a transparent conductive material layer located at a relatively bottom layer and a gate metal material layer located at a relatively top layer, and the gate 19 and the gate line 20 are formed simultaneously with the common electrode 12 and the common electrode signal line 13. When the HGA Mask (Half-Tone-Gate Mask, semi-transparent film mask) is used to form the patterns of the common electrode 12 and the common electrode signal line 13, the pattern of the common electrode 12 is formed by the semi-transparent film area 10 (Halftone mask, HTM) of the mask in FIG. 1, and the pattern of the common electrode signal line 13 is formed by the light-shielding film area 11 of the mask in FIG. 1. The light-shielding film area 11 is formed with a light-shielding film, for example, the material is chromium. The spacing area pattern between the common electrode 12 and the common electrode signal line 13 is formed corresponding to the completely light-transmitting area 18 of the mask plate in FIG. 1 . Figure 2 A in the figure corresponds to the exposure of the "three-sided mountain" portion of the mask composed of the semi-transparent film area 10 / light-shielding film area 11 / semi-transparent film area 10 in FIG. 1.

[0053] Figure 3The following is an exemplary exposure and etching process when a common electrode and a common electrode signal line pattern are formed on a substrate using a HGA Mask (Half-Tone-Gate Mask). (a) First, a transparent conductive film layer 14 and a gate metal film layer 15 are formed on a substrate 4 in sequence by a sputtering process. The material of the substrate 4 can be glass. (b) Then, PR glue 16 (photoresist) is coated on the gate metal film layer 15; under the exposure of the semi-transparent film mask plate 17, different exposure light amounts through the semi-transparent film mask plate 17 affect the PR glue 16; (c) Under the action of the developer, the PR glue in the area corresponding to the completely transparent area 18 (the area where neither the semi-transparent film nor the light-shielding film is set) on the semi-transparent film mask plate 17 is completely peeled off, the PR glue 16 in the area corresponding to the semi-transparent film area 10 (the area where only the semi-transparent film is set) is partially peeled off (for example, the PR glue is peeled off by 1 / 3 of the thickness), and the PR glue 16 in the area corresponding to the light-shielding film area 11 (the area where the light-shielding film is set) is completely retained; (d) By selecting different etching solutions, the gate metal film layer 15 in the area not covered by the PR glue on the substrate 4 is sequentially etched. and the transparent conductive film layer 14 are etched; (e) by Ashing, the remaining PR glue 16 is peeled off by 2 / 3 of the thickness, so that the PR glue in the area corresponding to the semi-transparent film area 10 on the original semi-transparent film mask plate 17 is completely peeled off, and the PR glue 16 in the area corresponding to the shading film area 11 remains about 1 / 3 of the thickness; (f) an etching liquid is selected to etch the gate metal film layer 15 in the area not covered by the PR glue on the substrate 4, and finally only the transparent conductive film layer exists in the substrate area corresponding to the semi-transparent film area 10 on the semi-transparent film mask plate 17, thereby forming the pattern of the common electrode 12; (g) finally, the PR glue in the substrate area corresponding to the shading film area 11 on the semi-transparent film mask plate 17 is peeled off to form the pattern of the common electrode signal line 13.

[0054] In the exposure and etching process of forming the common electrode and the common electrode signal line pattern on the substrate using the HGA Mask (Half-Tone-Gate Mask, semi-transparent film mask plate), since the boundary position of the semi-transparent film area 10 (Halftone mask, HTM) / light-shielding film area 11 (chrome film area) / semi-transparent film area 10 (Half tone mask, HTM) on the semi-transparent film mask plate is a "three-sided mountain" design, when the distance z between the two semi-transparent film areas 10 is relatively small (such as z≤20 microns), since the corresponding "three-sided mountain" position formed on the substrate will undergo two wet etching processes, the etching solution will remain and gather at the "three-sided mountain" position during the two wet etching processes, causing corrosion to the edge of the gate metal film layer at the "three-sided mountain" position, generating metal particles (such as copper particles, Cu When z is relatively small, the metal particles generated by corrosion accumulate in a space with a relatively small width, and are likely to form metal particle deposits with a relatively sharp shape, which are likely to penetrate the insulating layer subsequently formed on the gate metal film layer and come into contact with the source-drain metal layer formed after the insulating layer. Since the positive projection of the data line 22 formed simultaneously with the source-drain metal layer on the substrate is just located in the interval area between the two common electrodes 12, and the data line 22 is also extended to intersect with the common electrode signal line 13 in space, it is very easy to cause a short circuit between the data line 22 and the common electrode signal line 13.

[0055] To address the problem that the conductive film layer with a "three-sided mountain" area formed by the semi-transparent film mask plate is prone to short-circuit with the subsequently formed conductive film layer in the area, the illustrative embodiments of the present invention provide an array substrate and a preparation method thereof, a mask plate and a display panel.

[0056] An exemplary embodiment of the present invention provides a mask plate, such as Figure 4 As shown, it includes a first semi-transparent area 1, a second semi-transparent area 2 and a third area 3, the third area 3 has a pattern extending along the first direction E, there is a gap between the first semi-transparent area 1 and the second semi-transparent area 2, and the first semi-transparent area 1 and the second semi-transparent area 2 are respectively connected to the third area 3, the first semi-transparent area 1 and the second semi-transparent area 2 are located on the same side of the third area 3 and extend along the second direction F, and the first spacing between the first parts 101 of the first semi-transparent area 1 and the second semi-transparent area 2 close to the third area 3 is greater than the second spacing between the second parts 102 of the first semi-transparent area 1 and the second semi-transparent area 2 away from the third area 3.

[0057] Among them, an ADS (Advanced Super Dimension Switch) type array substrate is formed after exposure using the mask. The first semi-transparent area 1 and the second semi-transparent area 2 are respectively used for exposure to form the pattern of the common electrode in the pixel area on the array substrate, and the third area 3 is used for exposure to form the pattern of the common electrode signal line on the array substrate. In addition, the mask also includes a fourth area 21, and the fourth area 21 is used for exposure to form the spacing area between the common electrodes on the array substrate. It should be noted that when the photoresist used during exposure is a positive photoresist, the third area 3 of the mask is a light-shielding area, and the fourth area 21 of the mask is a completely light-transmitting area; when the photoresist used during exposure is a negative photoresist, the third area 3 of the mask is a light-transmitting area, and the fourth area 21 of the mask is a completely light-shielding area. In this embodiment, a positive photoresist is used during exposure, so the third area 3 is a light-shielding area, and the fourth area 21 is a completely light-transmitting area. The second spacing between the first semi-transparent area 1 and the second part 102 of the second semi-transparent area 2 away from the third area 3 is designed to be relatively small, such as the second spacing is generally designed to be less than 20 microns. With such a configuration, compared with the mask plate in which the spacing between the first semi-transparent area 1 and the second semi-transparent area 2 is all set to the second spacing, the area of ​​the first semi-transparent area 1 and the second semi-transparent area 2 can be increased, thereby increasing the area of ​​the common electrode in the pixel area on the array substrate, and then increasing the opening area of ​​the pixel area to increase the transmittance of the pixel area, and finally ensuring that the array substrate has a higher resolution while improving its aperture ratio and transmittance.

[0058] By making the first spacing between the first part 101 of the first semi-transparent area 1 and the second semi-transparent area 2 close to the third area 3 larger than the second spacing between the second parts 102 of the first semi-transparent area 1 and the second semi-transparent area 2 far from the third area 3, the width of the part of the "three-sided mountain-surrounded" position area close to the third area 3 formed by the first semi-transparent area 1, the second semi-transparent area 2 and the third area 3 can be increased relative to the width of the part far from the third area 3, so that when the mask is used for exposure and etching to simultaneously form the patterns of the common electrode and the common electrode signal line on the array substrate, the width range of the part of the "three-sided mountain-surrounded" position area close to the common electrode signal line where the etching liquid remaining in the two wet etchings is located is increased, and after the residual etching liquid corrodes the edge of the gate metal film layer, the distribution range of the metal particles generated is increased, thereby reducing the sharpness of the appearance of the metal particle deposits formed by the accumulation of metal particles, improving or avoiding the situation where the metal particles penetrate the insulating layer subsequently formed on the gate metal film layer and contact the source and drain metal layer formed after the insulating layer, so as to finally improve or avoid the short circuit between the data line and the common electrode line. At present, after the application of this mask plate, the defect of short circuit between the data line and the common electrode line has been reduced from 0.50% to 0.10%.

[0059] Optionally, the first semi-transparent area 1 and the second semi-transparent area 2 have the same shape and size, and the first semi-transparent area 1 and the second semi-transparent area 2 are mirror-symmetrical with the center line of the interval as the axis; the size ratio of the first part 101 and the second part 102 along the second direction F is in the range of 1 / 20 to 1. That is, the length of the first semi-transparent area 1 and the second semi-transparent area 2 along the direction away from the third area 3 is divided into 20 parts, and the length of the first part 101 along the direction away from the third area 3 accounts for a proportion in the range of 1 to 10. Such a configuration can not only ensure that the array substrate has a high resolution, but also improve its aperture ratio and transmittance, and after the residual etching solution corrodes the edge of the gate metal film layer, it can increase the distribution range of the generated metal particles, thereby reducing the sharpness of the shape of the metal particle deposits formed by the accumulation of metal particles, and better improve or avoid the situation where the metal particles penetrate the insulating layer subsequently formed on the gate metal film layer and contact the source and drain metal layer formed after the insulating layer, so as to better improve or avoid the situation where the data line and the common electrode line are short-circuited.

[0060] Further optionally, in this embodiment, a size of the first portion 101 along the second direction F is greater than or equal to 5 μm.

[0061] In this embodiment, further optionally, the size ratio X / m of the second spacing to the first spacing is in the range of X / (X+L / 5) to X / (X+L / 10), wherein X is the size of the second spacing, m is the size of the first spacing, and L is the width size of the second portion 102 of the first semi-transparent area 1 and the second semi-transparent area 2 along the first direction E; the width size range of the first portion 101 of the first semi-transparent area 1 and the second semi-transparent area 2 along the first direction E is 9L / 10 to 19L / 20. The first portion 101 of the first semi-transparent area 1 and the second semi-transparent area 2 are both rectangular in shape, and the second portion 102 of the first semi-transparent area 1 and the second semi-transparent area 2 are also rectangular in shape. The width of the second part 102 of the first semi-transparent area 1 is divided into 20 parts, and the width of the second part 102 of the second semi-transparent area 2 is also divided into 20 parts, the size of each part is L / 20, the size of the second spacing is X unchanged, and the size m of the first spacing is in the range of X+L / 20+L / 20 to X+L / 10+L / 10, that is, the size m of the first spacing is in the range of X+L / 10 to X+L / 5. In this way, the width of the first part 101 of the first semi-transparent area 1 and the second semi-transparent area 2 is sacrificed to enlarge the distance between the first parts 101 of the two. On the one hand, compared with the mask plate in which the distance between the first semi-transparent area 1 and the second semi-transparent area 2 is entirely set to the second distance of size X, it can improve its aperture ratio and transmittance while ensuring that the array substrate has a higher resolution; on the other hand, after the residual etching solution corrodes the edge of the gate metal film layer, the distribution range of the generated metal particles can be increased, thereby reducing the sharpness of the appearance of the metal particle deposits formed by the accumulation of metal particles, and better improving or avoiding the situation in which the metal particles penetrate the insulating layer subsequently formed on the gate metal film layer and contact the source and drain metal layer formed after the insulating layer, so as to better improve or avoid the short circuit between the data line and the common electrode line.

[0062] Further optionally, in this embodiment, the size of the first spacing is greater than or equal to 20 μm. For example, in this embodiment, the size of the second spacing is 16 μm, and the size of the first spacing is 23 μm.

[0063] In addition, the shape of the spacing area between the first semi-transparent area 1 and the first part 101 of the second semi-transparent area 2 close to the third area 3 is a rectangle, wherein the first spacing is the width of the rectangular spacing area along the first direction E. In this way, not only the mask can be better prepared by the traditional preparation process, but also the patterns of the common electrode and the common electrode signal line on the array substrate can be more easily prepared by the traditional process, and the rectangular spacing area can better increase the width range of the part close to the common electrode signal line in the "three-sided mountain" position area where the etching liquid remaining in the two wet etchings on the array substrate is located, thereby better increasing the distribution range of the metal particles generated after the residual etching liquid corrodes the edge of the gate metal film layer, thereby better improving or avoiding the occurrence of short circuits between the data line and the common electrode line.

[0064] Further optionally, if Figure 5 As shown, the shape of the edge lines on the opposite sides of the spacing area between the first semi-transparent area 1 and the first part 101 of the second semi-transparent area 2 can also be semicircular arcs. Wherein, m is the maximum size of the spacing area between the first semi-transparent area 1 and the first part 101 of the second semi-transparent area 2 along the first direction E. In this way, not only can the mask be better prepared by the traditional preparation process, but also the patterns of the common electrode and the common electrode signal line on the array substrate can be more easily prepared by the traditional process, and the spacing area of ​​the above shape can better increase the width range of the part close to the common electrode signal line in the "three-sided mountain" position area where the etching liquid remaining in the two wet etchings on the array substrate is located, so as to better increase the distribution range of the metal particles generated after the residual etching liquid corrodes the edge of the gate metal film layer, thereby better improving or avoiding the occurrence of short circuits between the data line and the common electrode line.

[0065] The mask provided in the exemplary embodiment can increase the width of the portion of the "three-sided mountain" position area formed by the first semi-transparent area, the second semi-transparent area and the third area and close to the third area relative to the width of the portion away from the third area by making the first spacing between the first portions of the first semi-transparent area and the second semi-transparent area close to the third area greater than the second spacing between the second portions of the two areas away from the third area. Therefore, when the mask is used for exposure and etching to simultaneously form the patterns of the common electrode and the common electrode signal line on the array substrate, the width range of the portion of the "three-sided mountain" position area close to the common electrode signal line where the etching liquid remaining in the two wet etchings is located is increased, and the distribution range of the metal particles generated after the residual etching liquid corrodes the edge of the gate metal film layer is increased, thereby reducing the sharpness of the appearance of the metal particle deposits formed by the accumulation of the metal particles, improving or avoiding the situation where the metal particles penetrate the insulating layer subsequently formed on the gate metal film layer and contact the source and drain metal layer formed after the insulating layer, so as to finally improve or avoid the situation where the data line and the common electrode line are short-circuited.

[0066] Another exemplary embodiment of the present invention provides an array substrate, such as Figure 6 and Figure 7 As shown, it includes a substrate 4 and a first conductive layer 5 and a second conductive layer 6 sequentially stacked on the substrate 4, the orthographic projection of the first conductive layer 5 on the substrate 4 and the orthographic projection of the second conductive layer 6 on the substrate 4 have an overlapping area, the first conductive layer 5 and the second conductive layer 6 in the overlapping area constitute a first conductive pattern 7, the first conductive pattern 7 has a figure extending along a first direction E, the first conductive layer 5 located outside the overlapping area includes a second conductive pattern 8 and a third conductive pattern 9, the second conductive pattern 8 and the third conductive pattern 9 are spaced apart, and the second conductive pattern 8 and the third conductive pattern 9 are respectively connected to the first conductive pattern 7, the second conductive pattern 8 and the third conductive pattern 9 are located on the same side of the first conductive pattern 7 and extend along the second direction F, and the first spacing between the first area 201 of the second conductive pattern 8 and the third conductive pattern 9 close to the first conductive pattern 7 is greater than the second spacing between the second area 202 of the second conductive pattern 8 and the third conductive pattern 9 away from the first conductive pattern 7.

[0067] The array substrate is prepared and formed by using the mask plate in the above embodiment to be exposed. Specifically, the first semi-transparent area and the second semi-transparent area of ​​the mask plate are respectively used to form the patterns of the second conductive pattern 8 and the third conductive pattern 9 on the array substrate through exposure, the third area of ​​the mask plate is used to form the pattern of the first conductive pattern 7 on the array substrate through exposure, and the spacing area between the first semi-transparent area and the second semi-transparent area on the mask plate is used to form the spacing area between the second conductive pattern 8 and the third conductive pattern 9 on the array substrate through exposure.

[0068] The array substrate can make the width of the portion of the "three-sided mountain-surrounded" position area formed by the second conductive pattern 8, the third conductive pattern 9 and the first conductive pattern 7 close to the first conductive pattern 7 larger than the width of the portion far from the first conductive pattern 7, so that when the second conductive pattern 8, the third conductive pattern 9 and the first conductive pattern 7 are formed by exposure and etching using the mask plate in the above embodiment to form the second conductive pattern 8, the third conductive pattern 9 and the first conductive pattern 7 on the array substrate, The width of the portion of the "three-sided mountain-surrounded" position area near the first conductive pattern 7 where the residual etching solution in the two wet etchings is located increases. After the residual etching solution corrodes the edge of the first conductive layer 5 and / or the second conductive layer 6, the distribution range of the generated metal particles increases, thereby reducing the sharpness of the shape of the metal particle deposits formed by the accumulation of metal particles, improving or avoiding the situation where the metal particles penetrate the insulating layer subsequently formed on the second conductive layer 6 and contact the third metal layer formed after the insulating layer, so as to ultimately improve or avoid the short circuit between the third metal layer and the first conductive layer 5 and / or the second conductive layer 6.

[0069] In this embodiment, the array substrate is an ADS (Advanced Super Dimension Switch) type array substrate. The first conductive layer 5 is a transparent conductive film layer, such as an ITO film layer, and the second conductive layer 6 is a metal conductive film layer, such as a gate metal film layer. The second conductive layer 6 of the array substrate is stacked with an insulating layer and a third metal layer (such as a source-drain metal layer) in sequence along the direction away from the substrate 4 on the side away from the substrate 4, and the third metal layer includes a pattern of a data line. Among them, the first conductive pattern 7 is a common electrode signal line, and the second conductive pattern 8 and the third conductive pattern 9 are common electrodes located in adjacent pixel areas respectively; the array substrate also includes an insulating layer and a data line, and the insulating layer and the data line are stacked in sequence on the side of the second conductive layer 6 away from the substrate 4; the orthographic projection of the insulating layer on the substrate 4 covers the entire substrate 4, and the orthographic projection of the data line on the substrate 4 is located in the interval area between the second conductive pattern 8 and the third conductive pattern 9, and extends to intersect with the first conductive pattern 7.

[0070] It should also be noted that the array substrate further includes a gate 19 and a gate line 20, which are made of the same two-layer conductive material structure as the first conductive pattern 7 and are formed simultaneously with the first conductive pattern 7. The gate 19 is connected to the gate line 20, and the gate 19 and the gate line 20 are spaced apart from the first conductive pattern 7, thereby being insulated from each other.

[0071] In the present embodiment, the array substrate makes the first spacing between the first area 201 of the second conductive pattern 8 and the third conductive pattern 9 close to the first conductive pattern 7 larger than the second spacing between the second area 202 of the second conductive pattern 8 and the third conductive pattern 9 far from the first conductive pattern 7. On the one hand, relative to the array substrate in which the spacing between the second conductive pattern 8 and the third conductive pattern 9 is all set to the second spacing, the area of ​​the second conductive pattern 8 and the third conductive pattern 9 can be increased, thereby increasing the area of ​​the common electrode in the pixel area on the array substrate, and then increasing the opening area of ​​the pixel area to increase the transmittance of the pixel area, and ultimately ensuring that the array substrate has a higher resolution while improving its aperture ratio and transmittance; on the other hand, it can make the area close to the "three-sided mountain surrounded" position formed by the common electrode and the common electrode signal line The width of the portion of the common electrode signal line is increased relative to the width of the portion away from the common electrode signal line, so that when the mask plate in the above embodiment is used to expose and etch to form the pattern of the common electrode and the common electrode signal line on the array substrate, the width range of the portion of the "three-sided mountain" position area near the common electrode signal line where the residual etching solution in the two wet etchings is located is increased, and after the residual etching solution corrodes the edge of the gate metal film layer, the distribution range of the generated metal particles is increased, thereby reducing the sharpness of the shape of the metal particle deposits formed by the accumulation of metal particles, improving or avoiding the situation where the metal particles penetrate the insulating layer subsequently formed on the gate metal film layer and contact the source and drain metal layer formed after the insulating layer, so as to finally improve or avoid the short circuit between the data line and the common electrode line. At present, after the preparation of the array substrate using the mask plate in the above embodiment, the defect of short circuit between the data line and the common electrode line has been reduced from 0.50% to 0.10%.

[0072] It should be noted that the arrangement of the various film layers on the array substrate is not limited to the above situation in this embodiment. The various film layers and conductive patterns on the array substrate that need to be prepared after exposure using the mask plate in the above embodiment may also be other situations that are different from but similar to the above situation in this embodiment.

[0073] Optionally, in this embodiment, the second conductive pattern 8 and the third conductive pattern 9 have the same shape and size, the second conductive pattern 8 and the third conductive pattern 9 are mirror-symmetric with the center line of the interval as the axis, and the size ratio of the first area 201 and the second area 202 along the second direction F is in the range of 1 / 20 to 1. That is, the length of the second conductive pattern 8 and the third conductive pattern 9 along the second direction F is divided into 20 parts, and the length of the first area 201 along the second direction F accounts for a proportion in the range of 1 to 10. Such a configuration can not only ensure that the array substrate has a high resolution, but also improve its aperture ratio and transmittance, and after the residual etching solution corrodes the edge of the gate metal film layer, it can increase the distribution range of the generated metal particles, thereby reducing the sharpness of the shape of the metal particle deposits formed by the accumulation of metal particles, and better improve or avoid the situation where the metal particles penetrate the insulating layer subsequently formed on the gate metal film layer and contact the source and drain metal layer formed after the insulating layer, so as to better improve or avoid the situation where the data line and the common electrode line are short-circuited.

[0074] Further optionally, in this embodiment, a size of the first region 201 along the second direction F is greater than or equal to 5 μm.

[0075] In this embodiment, further optionally, the size ratio X / m of the second spacing to the first spacing is in the range of X / (X+L' / 5) to X / (X+L' / 10), wherein X is the size of the second spacing, m is the size of the first spacing, and L' is the width size of the second region 202 of the second conductive pattern 8 and the third conductive pattern 9 along the first direction E; the width size range of the first region 201 of the second conductive pattern 8 and the third conductive pattern 9 along the first direction E is 9L' / 10 to 19L' / 20. The second region 202 of the second conductive pattern 8 and the third conductive pattern 9 are both rectangular in shape. The width of the second region 202 of the second conductive pattern 8 is divided into 20 parts, and the width of the second region 202 of the third conductive pattern 9 is also divided into 20 parts, each of which has a size of L' / 20. The size of the second spacing is X and remains unchanged, and the size m of the first spacing is in the range of X+L' / 20+L' / 20 to X+L' / 10+L' / 10, that is, the size m of the first spacing is in the range of X+L' / 10 to X+L' / 5. In this way, the width of part of the first area 201 of the second conductive pattern 8 and the third conductive pattern 9 is sacrificed to increase the distance between the first areas 201 of the two. On the one hand, compared with the array substrate in which the distance between the second conductive pattern 8 and the third conductive pattern 9 is entirely set to the second distance, the aperture ratio and light transmittance of the array substrate can be improved while ensuring that the array substrate has a higher resolution. On the other hand, after the residual etching solution corrodes the edge of the gate metal film layer, the distribution range of the generated metal particles can be increased, thereby reducing the sharpness of the appearance of the metal particle deposits formed by the accumulation of metal particles, and better improving or avoiding the situation in which the metal particles penetrate the insulating layer subsequently formed on the gate metal film layer and contact the source and drain metal layer formed after the insulating layer, so as to better improve or avoid the short circuit between the data line and the common electrode line.

[0076] Further optionally, in this embodiment, the size of the first spacing m is greater than or equal to 20 μm. For example, in this embodiment, the size of the second spacing n is 16 μm, and the size of the first spacing m is 23 μm.

[0077] Optionally, in the present embodiment, the spacing area between the second conductive pattern 8 and the first area 201 of the third conductive pattern 9 includes a first sub-area 301 and a second sub-area 302, and the first sub-area 301 and the second sub-area 302 are arranged in sequence away from the first conductive pattern 7 along the second direction F. Among them, the orthographic projection shape of the first sub-area 301 on the substrate 4 is a rectangle, and the orthographic projection shape of the second sub-area 302 on the substrate 4 is a trapezoid; the shorter base of the second sub-area 302 is farther away from the first conductive pattern 7 than its longer base. It should be noted here that m indicates the maximum spacing between the second conductive pattern 8 and the first area 201 of the third conductive pattern 9 along the first direction E. The spacing area between the second conductive pattern 8 and the first area 201 of the third conductive pattern 9 of the above-mentioned shape corresponds to Figure 4 The mask plate in the array substrate is exposed and formed, which not only makes it easier to prepare the patterns of the common electrode and the common electrode signal line on the array substrate through traditional processes, but also the rectangular spacing area can better increase the width range of the portion of the "three-sided mountain" position area close to the common electrode signal line where the etching liquid remaining in the two wet etchings on the array substrate is located, thereby better increasing the distribution range of the metal particles generated after the residual etching liquid corrodes the edge of the gate metal film layer, thereby better improving or avoiding the short circuit between the data line and the common electrode line.

[0078] Further optionally, if Figure 8 As shown, the edge lines on both sides of the spacing area between the second conductive pattern 8 and the first area 201 of the third conductive pattern 9 are semicircular. Wherein, m indicates the maximum spacing between the first area 201 of the second conductive pattern 8 and the third conductive pattern 9 along the first direction E. The spacing area between the second conductive pattern 8 and the first area 201 of the third conductive pattern 9 of the above shape corresponds to Figure 5 The middle mask plate is exposed and formed, which not only makes it easier to prepare the patterns of the common electrode and the common electrode signal line on the array substrate through traditional processes, but also the spacing area of ​​the above shape can better increase the width range of the part close to the common electrode signal line in the "three-sided mountain" position area where the etching liquid remaining in the two wet etchings on the array substrate is located, thereby better increasing the distribution range of metal particles generated after the residual etching liquid corrodes the edge of the gate metal film layer, thereby better improving or avoiding the short circuit between the data line and the common electrode line.

[0079] Based on the above structure of the array substrate, an exemplary embodiment of the present invention provides a method for preparing the array substrate, including:

[0080] Step S1: forming a first conductive layer film and a second conductive layer film on a substrate in sequence, and forming a photoresist on the second conductive layer film.

[0081] In this step, the first conductive layer film is made of transparent conductive material, such as ITO, IZO material. The second conductive layer film is made of copper or copper alloy. The first conductive layer film and the second conductive layer film can be formed on the substrate by magnetron sputtering, and the photoresist is coated on the second conductive layer film.

[0082] Step S2: Use the mask plate in the above embodiment to expose the substrate formed with photoresist, and after development, remove the photoresist in the substrate area corresponding to the interval area between the first semi-transparent area and the second semi-transparent area, partially retain the photoresist in the substrate area corresponding to the first semi-transparent area and the second semi-transparent area, and completely retain the photoresist in the substrate area corresponding to the third area.

[0083] Step S3: etching and removing the second conductive layer film and the first conductive layer film in the substrate region corresponding to the interval region between the first semi-transparent region and the second semi-transparent region.

[0084] In this step, different etching solutions are used to etch and remove the second conductive layer film and the first conductive layer film in the area not covered by the photoresist. In this step, the etching solution will remain in the area after the second conductive layer film and the first conductive layer film in the area not covered by the photoresist on the substrate are etched and removed, and will cause more or less corrosion to the edge of the second conductive layer film formed after etching, forming copper particles.

[0085] In this step, after etching, the substrate is cleaned with plasma water.

[0086] Step S4: completely remove the photoresist corresponding to the first semi-transparent area and the second semi-transparent area, and remove part of the completely retained photoresist corresponding to the third area.

[0087] In this step, ashing is performed to remove a portion of the photoresist remaining on the substrate, and to remove a portion of the photoresist completely remaining on the substrate.

[0088] Step S5: etching and removing the second conductive layer film in the substrate area corresponding to the first semi-transparent area and the second semi-transparent area to form a second conductive pattern and a third conductive pattern.

[0089] In this step, the etching solution will remain in the "three-sided surrounded by mountains" area surrounded by the second conductive pattern, the third conductive pattern and the part of the conductive layer film covered by the photoresist after the second conductive pattern and the third conductive pattern are formed, and will cause more or less corrosion to the edge of the second conductive layer film formed after etching, forming copper particles.

[0090] In this step, after etching, the substrate is cleaned with plasma water.

[0091] Step S6: removing the remaining portion of the photoresist that is completely retained corresponding to the third region to form a first conductive pattern.

[0092] In this step, the remaining portion of the photoresist completely retained on the substrate is stripped off to form a first conductive pattern, and a pattern including a gate electrode and a gate line is also formed.

[0093] In this embodiment, the method for preparing the array substrate further includes the steps of sequentially forming an insulating layer and a data line after step S6, wherein the data line is located in the spacing area between the second conductive pattern and the third conductive pattern, and the data line also extends to intersect with the first conductive pattern in space, and by increasing the spacing between the second conductive pattern and the first area of ​​the third conductive pattern, the defect of short circuit between the data line and the common electrode line has been reduced from 0.50% to 0.10%. There is basically no short circuit between the data line and the first conductive pattern. Since the preparation of the insulating layer and the data line adopts traditional processes, the specific preparation process will not be repeated here.

[0094] In the preparation method of the array substrate, during the two etching processes of step S3 and step S5, there will be residual etching liquid, which will corrode the edge of the second conductive layer film and form copper particles. By using the mask plate in the above embodiment, the width of the portion of the "three-sided mountain" position area surrounded by the second conductive pattern, the third conductive pattern and the first conductive pattern close to the first conductive pattern can be increased relative to the width of the portion far from the first conductive pattern, so that the width range of the portion of the "three-sided mountain" position area close to the first conductive pattern where the residual etching liquid in the two wet etchings is located is increased. After the residual etching liquid corrodes the edge of the second conductive layer, the distribution range of the generated metal particles is increased, thereby reducing the sharpness of the appearance of the metal particle deposits formed by the accumulation of metal particles, improving or avoiding the situation that the metal particles penetrate the insulating layer subsequently formed on the second conductive layer and contact the third metal layer formed after the insulating layer, so as to finally improve or avoid the situation that the third metal layer and the second conductive layer are short-circuited.

[0095] In the array substrate provided in the exemplary embodiment, by making the first spacing between the first areas of the second conductive pattern and the third conductive pattern close to the first conductive pattern larger than the second spacing between the second areas of the second conductive pattern and the third conductive pattern far from the first conductive pattern, the width of the portion of the "three-sided mountain-surrounded" position area formed by the second conductive pattern, the third conductive pattern and the first conductive pattern close to the first conductive pattern can be increased relative to the width of the portion far from the first conductive pattern, so that when the second conductive pattern, the third conductive pattern and the first conductive pattern on the array substrate are formed by exposure and etching using the mask plate in the above embodiment, the width range of the portion of the "three-sided mountain-surrounded" position area close to the first conductive pattern where the etching liquid remaining in the two wet etchings is located is increased, and after the residual etching liquid corrodes the edge of the first conductive layer and / or the second conductive layer, the distribution range of the generated metal particles is increased, thereby reducing the sharpness of the appearance of the metal particle deposit formed by the accumulation of the metal particles, improving or avoiding the situation that the metal particles penetrate the insulating layer subsequently formed on the second conductive layer and contact the third metal layer formed after the insulating layer, so as to finally improve or avoid the situation that the third metal layer and the first conductive layer and / or the second conductive layer are short-circuited.

[0096] Another exemplary embodiment of the present invention provides a display panel, comprising the array substrate and the opposite substrate in the above embodiment.

[0097] The array substrate and the counter substrate are aligned, and the gap formed by the alignment is filled with liquid crystal molecules. The counter substrate may be a color filter substrate.

[0098] By adopting the array substrate in the above embodiment, on the one hand, the aperture ratio and light transmittance of the display panel are improved while ensuring a higher resolution. On the other hand, the circuit breakage between the upper and lower conductive layers can be improved or avoided, thereby improving the yield and quality of the display panel.

[0099] The display panel provided in the exemplary embodiment of the present invention may be any product or component having a display function, such as an LCD panel, an LCD television, a display, a mobile phone, a navigator, or the like.

[0100] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. An array substrate, comprising: A substrate and a first conductive layer and a second conductive layer sequentially stacked on the substrate, wherein an orthographic projection of the first conductive layer on the substrate and an orthographic projection of the second conductive layer on the substrate have an overlapping area, the first conductive layer and the second conductive layer in the overlapping area constitute a first conductive pattern, the first conductive pattern has a pattern extending along a first direction, the first conductive layer located outside the overlapping area includes a second conductive pattern and a third conductive pattern, there is a gap between the second conductive pattern and the third conductive pattern, and the second conductive pattern and the third conductive pattern are respectively connected to the first conductive pattern, the second conductive pattern and the third conductive pattern are located on the same side of the first conductive pattern and extend along a second direction, characterized in that a first spacing between first areas of the second conductive pattern and the third conductive pattern close to the first conductive pattern is greater than a second spacing between second areas of the second conductive pattern and the third conductive pattern away from the first conductive pattern, the spacing area between the first areas of the second conductive pattern and the third conductive pattern includes a first sub-area and a second sub-area, the first sub-area and the second sub-area are arranged sequentially away from the first conductive pattern along the second direction, and the orthographic projection shape of the second sub-area on the substrate is a trapezoid; The shorter bottom side of the second sub-region is farther away from the first conductive pattern than the longer bottom side of the second sub-region.

2. The array substrate according to claim 1, characterized in that: The orthographic projection shape of the first sub-area on the substrate is a rectangle.

3. The array substrate according to claim 1, characterized in that: The edge lines on opposite sides of the spacing area between the second conductive pattern and the first region of the third conductive pattern are in the shape of semicircular arcs.

4. The array substrate according to claim 1, characterized in that: The second conductive pattern and the third conductive pattern have the same shape and size, and the second conductive pattern and the third conductive pattern are mirror-symmetrical with respect to the middle line of the interval as an axis.

5. The array substrate according to claim 1, characterized in that: A size ratio between the first region and the second region along the second direction ranges from 1 / 20 to 1.

6. The array substrate according to claim 1, characterized in that: The size ratio of the second spacing to the first spacing is in the range of X / (X+L' / 5) to X / (X+L' / 10), wherein X is the size of the second spacing, and L' is the width of the second region of the second conductive pattern and the third conductive pattern along the first direction.

7. The array substrate according to claim 1, characterized in that: The width of the first region of the second conductive pattern and the third conductive pattern along the first direction is in a range of 9L' / 10 to 19L' / 20.

8. The array substrate according to claim 1, characterized in that: A size of the first region along the second direction is greater than or equal to 5 μm.

9. The array substrate according to claim 1, characterized in that: The first interval is greater than or equal to 20 μm.

10. The array substrate according to claim 1, characterized in that: The first conductive pattern is a common electrode signal line, and the second conductive pattern and the third conductive pattern are common electrodes respectively located in adjacent pixel areas; The array substrate further comprises an insulating layer and a data line, wherein the insulating layer and the data line are sequentially stacked on a side of the second conductive layer away from the substrate; The orthographic projection of the insulating layer on the substrate covers the entire substrate, and the orthographic projection of the data line on the substrate is located in the spacing area between the second conductive pattern and the third conductive pattern, and extends to intersect with the first conductive pattern.

11. A display panel, characterized in that: It comprises the array substrate and the counter substrate as described in any one of claims 1 to 10.

12. A mask plate for preparing an array substrate as claimed in any one of claims 1 to 10, comprising a first semi-transparent area, a second semi-transparent area and a third area, wherein the third area has a pattern extending along a first direction, there is a gap between the first semi-transparent area and the second semi-transparent area, and the first semi-transparent area and the second semi-transparent area are respectively connected to the third area, the first semi-transparent area and the second semi-transparent area are located on the same side of the third area and extend along a second direction, characterized in that: A first distance between first portions of the first semi-light-transmissive region and the second semi-light-transmissive region close to the third region is greater than a second distance between second portions of the first semi-light-transmissive region and the second semi-light-transmissive region far from the third region.

13. The mask plate according to claim 12, characterized in that: The shape of the interval area between the first semi-light-transmitting area and the first part of the second semi-light-transmitting area is rectangular.

14. The mask plate according to claim 12, characterized in that: The edge lines on opposite sides of the interval area between the first semi-light-transmitting area and the first part of the second semi-light-transmitting area are in the shape of semicircular arcs.

15. The mask plate according to claim 12, characterized in that: The first semi-light-transmitting area and the second semi-light-transmitting area have the same shape and size, and the first semi-light-transmitting area and the second semi-light-transmitting area are mirror-symmetrical with the center line of the interval as the axis.

16. The mask plate according to claim 12, characterized in that: The size ratio of the first portion to the second portion along the second direction ranges from 1 / 20 to 1.

17. The mask plate according to claim 12, characterized in that: The size ratio of the second spacing to the first spacing is in the range of X / (X+L / 5) to X / (X+L / 10), wherein X is the size of the second spacing, and L is the width of the first semi-transparent area and the second part of the second semi-transparent area along the first direction.

18. The mask plate according to claim 12, characterized in that: The widths of the first parts of the first semi-light-transmitting area and the second semi-light-transmitting area along the first direction are both in the range of 9L / 10 to 19L / 20.

19. The mask plate according to claim 12, characterized in that: A size of the first portion along the second direction is greater than or equal to 5 μm.

20. The mask plate according to claim 12, characterized in that: The first spacing has a size greater than or equal to 20 μm.

Images