Overlay error correction method and device, electronic device and storage medium

Abstract

The disclosure relates to a method and device for correcting overlay error, electronic equipment and computer readable storage medium, and belongs to the technical field of semiconductor production and manufacturing, and can be applied to the scene of correcting overlay error in the case of damaged overlay error identification. The method comprises: obtaining a current batch wafer, determining a plurality of alignment marks corresponding to the current batch wafer, and overlay error and overlay error deviation of each alignment mark; determining the mark quality value of each alignment mark based on the overlay error and the overlay error deviation; based on the mark quality value, screening the plurality of alignment marks to determine the target alignment mark; based on the target alignment mark, determining the error correction result corresponding to the current batch wafer, and performing exposure alignment processing on the next batch wafer based on the error correction result. The disclosure can determine the overlay error based on the target alignment mark which is not damaged, thereby effectively controlling the overlay error generated in the process.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to an overlay error correction method, an overlay error correction device, an electronic device, and a computer-readable storage medium. Background Technology

[0002] In semiconductor manufacturing processes, the pattern after exposure and development (i.e., the current layer) must be aligned with the existing pattern on the wafer substrate (i.e., the previous layer) to ensure correct connections between devices. The relative position between the current layer and the previous layer of the exposed pattern is called overlay error. Excessive overlay error will cause short circuits or open circuits in devices, affecting product yield.

[0003] Currently, the control and reduction of overlay error is achieved through the coordinated work of three parts: lithography machine alignment operation and exposure; measurement of photoresist pattern overlay error; model calculation to determine correctable items, and feedback to the lithography machine.

[0004] In actual manufacturing processes, different locations at varying distances from the wafer center may exhibit different overlay errors, leading to variations in the measurement patterns obtained from different locations. Overlay errors during wafer measurement are influenced by numerous factors, and feeding back these affected overlay errors to the exposure equipment can potentially interfere with its exposure behavior.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a method, apparatus, electronic device, and computer-readable storage medium for overlay error correction, thereby at least to some extent overcoming the problem that incomplete or damaged graphic markings may occur in the wafer fabrication process, leading to incorrect overlay errors and feeding back the incorrect overlay errors to the exposure equipment, thus affecting the overall wafer yield.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0008] According to a first aspect of this disclosure, a method for correcting overlay errors is provided, comprising: acquiring a current batch of wafers; determining a plurality of alignment marks corresponding to the current batch of wafers, and overlay errors and overlay error deviations corresponding to each alignment mark; determining a mark quality value corresponding to each alignment mark based on the overlay errors and overlay error deviations of each alignment mark; filtering the plurality of alignment marks based on the determined mark quality value to determine a target alignment mark; and determining an error correction result corresponding to the current batch of wafers based on the target alignment mark, so as to perform exposure alignment processing on the next batch of wafers based on the error correction result.

[0009] In one exemplary embodiment of this disclosure, obtaining the current batch of wafers includes: obtaining an overlay error identifier corresponding to the current batch of wafers; obtaining a reference identifier signal and an actual identifier signal corresponding to the overlay error identifier; determining the identifier integrity of the overlay error identifier based on the actual identifier signal and the reference identifier signal; if the identifier integrity is less than an integrity threshold, configuring multiple graphic selection boxes to determine multiple alignment marks based on the multiple graphic selection boxes; if the identifier integrity is greater than or equal to the integrity threshold, configuring one graphic selection box to determine the alignment mark based on the graphic selection box.

[0010] In one exemplary embodiment of this disclosure, the number of alignment marks is multiple, and determining the multiple alignment marks corresponding to the current batch of wafers includes: determining the graphic selection position corresponding to the current batch of wafers; obtaining the number of positions of the graphic selection position, configuring a corresponding number of graphic selection boxes according to the number of positions; and performing graphic marking processing on the current batch of wafers based on the determined graphic selection position and the graphic selection box to obtain multiple alignment marks.

[0011] In one exemplary embodiment of this disclosure, determining the pattern selection position corresponding to the current batch of wafers includes: obtaining the identifier type of the overlay error identifier of the current batch of wafers; determining the symmetry center point corresponding to the current batch of wafers; determining at least one pattern selection direction corresponding to the current test product based on the symmetry center point; and determining the pattern selection position corresponding to each pattern selection direction based on the identifier type.

[0012] In one exemplary embodiment of this disclosure, determining the graphic selection position corresponding to each graphic selection direction based on the identifier type includes: determining the graphic identifier features of the current batch of wafers based on the identifier type; determining the inner border graphic selection position in each graphic selection direction based on the graphic identifier features; and determining the outer border graphic selection position of the current batch of wafers based on the graphic identifier features.

[0013] In one exemplary embodiment of this disclosure, determining the mark quality value corresponding to each alignment mark includes: determining the overprinting error corresponding to each alignment mark; determining the overprinting error deviation and the standard deviation of the overprinting error deviation corresponding to each alignment mark based on the overprinting error; determining the mark quality value according to the overprinting error, the overprinting error deviation, and the standard deviation of the overprinting error deviation; the mark quality value Wherein, MQ represents the mark quality value of the alignment mark, OVL represents the overprinting error of the alignment mark, Qmerit represents the overprinting error deviation of the alignment mark, and Qmeritδ² represents the standard deviation of the overprinting error deviation of the alignment mark.

[0014] In one exemplary embodiment of this disclosure, determining the overlay error deviation and standard deviation of the overlay error corresponding to each alignment mark based on the overlay error includes: determining the overlay error derivative corresponding to the overlay error; determining the overlay error deviation based on the overlay error and the overlay error derivative; determining the standard deviation of the overlay error deviation based on the overlay error deviation; the overlay error deviation Qmerit = OVL' - OVL; where Qmerit represents the overlay error deviation of the alignment mark, OVL represents the overlay error of the alignment mark, and OVL' represents the overlay error derivative of the alignment mark.

[0015] In one exemplary embodiment of this disclosure, the number of alignment marks is multiple, and the step of filtering the multiple alignment marks based on the determined mark quality value to determine the target alignment mark includes: determining the average mark quality value corresponding to the multiple mark quality values; and taking the alignment mark whose mark quality value is less than the average mark quality value as the target alignment mark.

[0016] In one exemplary embodiment of this disclosure, determining the error correction result corresponding to the current batch of wafers based on the target alignment mark includes: determining the target mark signal of the target alignment mark; analyzing and processing the target mark signal to determine the target center point corresponding to the target alignment mark; determining the target overlay error value corresponding to the target alignment mark based on the target center point; performing simulation calculation on the target overlay error value to determine the overlay error compensation value corresponding to the current batch of wafers; and using the overlay error compensation value as the error correction result.

[0017] In one exemplary embodiment of this disclosure, determining the target overprinting error value corresponding to the target alignment mark based on the target center point includes: obtaining the graphic alignment direction corresponding to the current test product; the graphic alignment direction includes a first alignment direction and a second alignment direction; determining a first overprinting error value corresponding to the first alignment direction based on the target center point; determining a second overprinting error value corresponding to the second alignment direction based on the target center point; and generating the target overprinting error value based on the first overprinting error value and the second overprinting error value.

[0018] In one exemplary embodiment of this disclosure, the step of performing exposure alignment processing on the next batch of wafers based on the error correction result includes: sending the error correction result to an exposure alignment device; and controlling the exposure alignment device to adjust the corresponding pattern alignment parameters based on the error correction result, so that the exposure alignment device performs exposure alignment processing on the next batch of wafers based on the pattern alignment parameters.

[0019] According to a second aspect of this disclosure, an overlay error correction system is provided, comprising: an exposure alignment device for acquiring an initial current batch of wafers and performing exposure alignment processing on the initial current batch of wafers to obtain a current batch of wafers; a marking error measurement device for determining a specified number of alignment marks based on the integrity of the overlay error markings of the current batch of wafers and determining an overlay error deviation value corresponding to the current batch of wafers based on the alignment marks; and a calculation device for determining an overlay error compensation value based on the overlay error deviation value and sending the overlay error compensation value to the exposure alignment device.

[0020] According to a third aspect of this disclosure, an overlay error correction apparatus is provided, comprising: an alignment mark determination module, configured to acquire a current batch of wafers, determine a plurality of alignment marks corresponding to the current batch of wafers, and an overlay error and an overlay error deviation corresponding to each alignment mark; a mark measurement value determination module, configured to determine a mark quality value corresponding to each alignment mark based on the overlay error and the overlay error deviation of each alignment mark; a mark filtering module, configured to filter the plurality of alignment marks based on the determined mark quality value to determine a target alignment mark; and an error correction module, configured to determine an error correction result corresponding to the current batch of wafers based on the target alignment mark, and to perform exposure alignment processing on the next batch of wafers based on the error correction result.

[0021] In one exemplary embodiment of this disclosure, the overlay error correction device further includes a graphics library configuration module, configured to: acquire an overlay error identifier corresponding to the current batch of wafers; acquire a reference identifier signal and an actual identifier signal corresponding to the overlay error identifier respectively; determine the identifier integrity of the overlay error identifier based on the actual identifier signal and the reference identifier signal; if the identifier integrity is less than an integrity threshold, configure multiple graphic selection boxes to determine multiple alignment marks based on the multiple graphic selection boxes; if the identifier integrity is greater than or equal to the integrity threshold, configure one graphic selection box to determine the alignment mark based on the graphic selection box.

[0022] In one exemplary embodiment of this disclosure, the number of alignment marks is multiple, and the alignment mark determination module includes a test mark determination unit, configured to: determine the pattern selection position corresponding to the current batch of wafers; obtain the number of positions of the pattern selection position, configure a corresponding number of pattern selection boxes according to the number of positions; and perform pattern marking processing on the current batch of wafers based on the determined pattern selection position and the pattern selection box to obtain multiple alignment marks.

[0023] In one exemplary embodiment of this disclosure, the test identifier determination unit includes a pattern position determination unit, configured to: obtain the identifier type of the overlay error identifier of the current batch of wafers; determine the symmetry center point corresponding to the current batch of wafers; determine at least one pattern selection direction corresponding to the current test product based on the symmetry center point; and determine the pattern selection position corresponding to each pattern selection direction based on the identifier type.

[0024] In one exemplary embodiment of this disclosure, the graphic position determination unit includes a graphic position determination subunit, configured to: determine the graphic identification features of the current batch of wafers based on the identification type; determine the inner border graphic selection position in each graphic selection direction based on the graphic identification features; and determine the outer border graphic selection position of the current batch of wafers based on the graphic identification features.

[0025] In one exemplary embodiment of this disclosure, the mark measurement value determination module includes a mark measurement value determination unit, configured to: determine the overprinting error corresponding to each alignment mark; determine the overprinting error deviation and the standard deviation of the overprinting error deviation corresponding to each alignment mark based on the overprinting error; determine the mark quality value according to the overprinting error, the overprinting error deviation, and the standard deviation of the overprinting error deviation; the mark quality value Wherein, MQ represents the mark quality value of the alignment mark, OVL represents the overprinting error of the alignment mark, Qmerit represents the overprinting error deviation of the alignment mark, and Qmeritδ² represents the standard deviation of the overprinting error deviation of the alignment mark.

[0026] In one exemplary embodiment of this disclosure, the identification measurement value determination unit includes an overlay error parameter determination subunit, configured to: determine the overlay error derivative corresponding to the overlay error; determine the overlay error deviation based on the overlay error and the overlay error derivative; determine the standard deviation of the overlay error deviation based on the overlay error deviation; the overlay error deviation Qmerit=OVL'-OVL; where Qmerit represents the overlay error deviation of the alignment mark, OVL represents the overlay error of the alignment mark, and OVL' represents the overlay error derivative of the alignment mark.

[0027] In one exemplary embodiment of this disclosure, the number of alignment marks is multiple, and the mark filtering module includes an identifier filtering unit, configured to: determine the average mark quality value corresponding to the multiple mark quality values; and select alignment marks whose mark quality value is less than the average mark quality value as the target alignment marks.

[0028] In one exemplary embodiment of this disclosure, the error correction module includes an error correction unit, configured to: determine a target mark signal of the target alignment mark; analyze and process the target mark signal to determine a target center point corresponding to the target alignment mark; determine a target overlay error value corresponding to the target alignment mark based on the target center point; perform simulation calculation on the target overlay error value to determine an overlay error compensation value corresponding to the current batch of wafers; and use the overlay error compensation value as the error correction result.

[0029] In one exemplary embodiment of this disclosure, the error correction unit includes an error correction subunit, configured to: obtain the graphic alignment direction corresponding to the current test product; the graphic alignment direction includes a first alignment direction and a second alignment direction; determine a first overlay error value corresponding to the first alignment direction based on the target center point; determine a second overlay error value corresponding to the second alignment direction based on the target center point; and generate the target overlay error value according to the first overlay error value and the second overlay error value.

[0030] In one exemplary embodiment of this disclosure, the overlay error correction device includes a correction result feedback module, configured to: send the error correction result to the exposure alignment device; and control the exposure alignment device to adjust the corresponding pattern alignment parameters based on the error correction result, so that the exposure alignment device performs exposure alignment processing on the next batch of wafers based on the pattern alignment parameters.

[0031] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory storing computer-readable instructions that, when executed by the processor, implement the overlay error correction method according to any one of the preceding claims.

[0032] According to a fifth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the overlay error correction method according to any one of the preceding claims.

[0033] The technical solution provided in this disclosure may include the following beneficial effects:

[0034] The overlay error correction method in the exemplary embodiments of this disclosure, on the one hand, calculates the overlay error based on target alignment marks selected from multiple mark quality values, which can reduce the problem of overlay error accuracy being affected by damage to the alignment marks. On the other hand, using the error correction result calculated based on the target alignment marks in the exposure alignment process of the next batch of wafers can effectively improve product yield.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0037] Figure 1 A flowchart illustrating an overlay error correction method according to an exemplary embodiment of the present disclosure is shown schematically;

[0038] Figure 2 The illustration shows schematic diagrams of graphic identifiers corresponding to different identifier types according to exemplary embodiments of the present disclosure;

[0039] Figure 3The illustration schematically shows a diagram of determining a graphical selection box based on a current test product according to an exemplary embodiment of the present disclosure;

[0040] Figure 4 The diagram illustrates the results of various derivatives of the overlay error according to an exemplary embodiment of the present disclosure;

[0041] Figure 5 The illustration schematically depicts a process of determining a target alignment mark from a plurality of alignment marks according to an exemplary embodiment of the present disclosure;

[0042] Figure 6 The diagram illustrates the variation of the overprinting error and overprinting error deviation values ​​after identification and screening according to an exemplary embodiment of the present disclosure.

[0043] Figure 7 The illustration schematically shows a diagram of determining overlay error deviation values ​​based on target alignment marks according to an exemplary embodiment of the present disclosure;

[0044] Figure 8 A schematic diagram of an overlay error correction system according to an exemplary embodiment of the present disclosure is shown.

[0045] Figure 9 A block diagram of an overlay error correction device according to an exemplary embodiment of the present disclosure is shown schematically;

[0046] Figure 10 A block diagram of an electronic device according to an exemplary embodiment of the present disclosure is shown schematically;

[0047] Figure 11 The illustration shows a schematic diagram of a computer-readable storage medium according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0048] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0049] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0050] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0051] Overlay errors in wafer measurement can be affected by many factors, such as instability in the photolithography process and signal interference in the measurement target pattern (IMAGE) acquired by the measurement equipment. These factors can cause the overlay errors to be fed back to the exposure equipment, thereby interfering with the exposure behavior of the exposure equipment.

[0052] During wafer fabrication, incomplete or damaged images often appear at the edges. For example, during actual measurement, overlay errors caused by process variations may be destroyed, or the intervals between overlay errors may be disrupted. Because of these damaged images, the measured overlay errors may be incorrect. This feedback to the exposure equipment will cause the equipment to behave in the wrong direction, thus affecting the overall wafer yield.

[0053] Based on this, the present disclosure provides a method for correcting overprinting errors, a system for correcting overprinting errors, a device for correcting overprinting errors, an electronic device, and a computer-readable storage medium.

[0054] It should be noted that the terminology used in this disclosure, including Region of Interest (ROI), can refer to the region to be processed in machine vision and image processing, which is delineated from the image being processed using methods such as rectangles, circles, ellipses, and irregular polygons.

[0055] In this example embodiment, a method for correcting overprinting errors is first provided. The overprinting error correction method of this disclosure can be implemented using a server or using a terminal device. The terminal described in this disclosure may include mobile terminals such as mobile phones, tablets, laptops, handheld computers, and personal digital assistants (PDAs), as well as fixed terminals such as desktop computers. Figure 1 A schematic diagram illustrating the flow of an overlay error correction method according to some embodiments of the present disclosure is provided. Reference Figure 1 The overlay error correction method may include the following steps:

[0056] Step S110: Obtain the current batch of wafers, determine the multiple alignment marks corresponding to the current batch of wafers, and the overlay error and overlay error deviation corresponding to each alignment mark.

[0057] According to some exemplary embodiments of this disclosure, the current batch of wafers may be the wafer product currently undergoing exposure alignment processing. An alignment mark may be an identifier determined based on the alignment pattern on the substrate in the current batch of wafers, and the alignment mark is used to determine the overlay error of the current batch of wafers. Overlay error (OVL) may be the alignment deviation of the relative position between the current layer pattern and the previous layer pattern in the current batch of wafers. Overlay error deviation (Qmerit) may be a parameter used to measure the quality of the overlay error of the alignment mark.

[0058] In integrated circuit manufacturing, the relative position between the current layer (photoresist pattern) and the reference layer (substrate pattern) on the wafer is a key indicator for monitoring the quality of the photolithography process. In photolithography, wafers to be processed arrive at the lithography machine in batches so that the machine can align and expose the wafers in the current batch. A particular batch of wafers arriving at the lithography machine can be referred to as the current batch of wafers. After obtaining the current batch of wafers, it is necessary to determine the overlay error corresponding to the current batch. Therefore, multiple alignment marks can be identified from the measurement target pattern (IMAGE) corresponding to the current batch of wafers, and the overlay error is measured based on these identified alignment marks.

[0059] For example, when determining alignment marks, it can be done based on the Region of Interest (ROI) selection box, using the ROI box to select multiple alignment marks from the measurement target image (IMAGE) of the current batch of wafers.

[0060] Step S120: Based on the overprinting error and overprinting error deviation of each alignment mark, determine the mark quality value corresponding to each alignment mark.

[0061] According to some exemplary embodiments of this disclosure, the mark quality value can be the quality of the ROI box used to select alignment marks, and the mark quality value can be represented as (mark quality, MQ).

[0062] After identifying multiple alignment marks, in order to determine the quality of the alignment marks selected by each ROI box, the mark quality value corresponding to each alignment mark can be determined. Specifically, the mark quality value of each alignment mark can be determined based on the overlay error and overlay error deviation corresponding to each alignment mark. The overlay error deviation can be a parameter used to measure whether the quality of the alignment mark is good or bad.

[0063] Step S130: Based on the determined mark quality value, filter multiple alignment marks to determine the target alignment mark.

[0064] According to some exemplary embodiments of this disclosure, a target alignment mark (robust IMAGE) may be an alignment mark that meets specific conditions and is selected from alignment marks based on the mark quality value. For example, a target alignment mark may be an alignment mark whose mark quality value is less than the average of all mark quality values.

[0065] After determining the marker quality values ​​corresponding to all alignment markers, multiple alignment markers can be filtered based on these quality values ​​to obtain target alignment markers that meet specific conditions. For example, the average value corresponding to all marker quality values ​​can be determined, and alignment markers with quality values ​​greater than the average value can be filtered out, leaving the remaining alignment markers as target alignment markers. Alternatively, target alignment markers that meet specific conditions can be obtained by using other filtering methods based on the magnitude relationship between multiple marker quality values.

[0066] Step S140: Based on the target alignment mark, determine the error correction result corresponding to the current batch of wafers, and perform exposure alignment processing on the next batch of wafers based on the error correction result.

[0067] According to some exemplary embodiments of this disclosure, the error correction result can be a compensation value for the overlay error of the current batch of wafers determined based on the target alignment mark. The next batch of wafers can be the product to be processed next to be sent to the exposure alignment equipment for exposure alignment processing. Exposure alignment processing can be a process in which the exposure alignment equipment (such as a lithography machine) performs alignment and exposure operations on the product.

[0068] After identifying the target alignment mark, the offset of the overlay error for the current batch of wafers can be determined based on the target alignment mark. The error correction result, i.e., the overlay error compensation value, is determined based on the offset of the overlay error. After obtaining the error correction result, it can be fed back to the lithography machine so that the lithography machine can perform exposure alignment processing on the next batch of wafers based on the error correction result.

[0069] According to the overlay error correction method in this example embodiment, on the one hand, calculating the overlay error based on the target alignment mark obtained by screening multiple mark quality values ​​can reduce the problem of affecting the accuracy of overlay error due to the destruction of the alignment mark. On the other hand, using the error correction result calculated based on the target alignment mark in the exposure alignment process of the next batch of wafers can effectively improve the product yield.

[0070] The overprinting error correction method in this example embodiment will be further explained below.

[0071] In one exemplary embodiment of this disclosure, an overlay error identifier corresponding to the current batch of wafers is obtained; a reference identifier signal and an actual identifier signal corresponding to the overlay error identifier are obtained respectively; the identifier integrity of the overlay error identifier is determined based on the actual identifier signal and the reference identifier signal; if the identifier integrity is less than the integrity threshold, multiple graphic selection boxes are configured to determine multiple alignment marks based on the multiple graphic selection boxes; if the identifier integrity is greater than or equal to the integrity threshold, a graphic selection box is configured to determine the alignment mark based on the graphic selection box.

[0072] The overprinting error identifier can be a graphic identifier used to calculate the overprinting error in the current test product. The reference identifier signal can be an ideal state signal reflecting the integrity of the overprinting error identifier. The actual identifier signal can be an actual state signal reflecting the integrity of the overprinting error identifier. Identification integrity can be a parameter value indicating whether the overprinting error identifier has been damaged or is still in an intact state. The integrity threshold can be a pre-configured data value used for comparison calculation with the identification integrity. The graphic selection box can be a graphic box used to select alignment marks.

[0073] Before determining the alignment marks corresponding to the current batch of wafers, the integrity of the overlay marks corresponding to the current batch of wafers can be determined first. The specific processing steps are as follows: Obtain the overlay error mark corresponding to the current batch of wafers. After obtaining the overlay error mark, the reference mark signal and the actual mark signal corresponding to the overlay error mark can be obtained separately. Among them, the reference mark signal can be the mark signal of the overlay error mark under ideal conditions, and the actual mark signal can be the mark signal actually corresponding to the overlay error mark.

[0074] After identifying the reference marker signal and the actual marker signal, the two signals can be compared to determine their similarity, thus obtaining the marker integrity corresponding to the overlay error marker. The determined marker integrity is then compared with an integrity threshold. If the marker integrity is less than the integrity threshold, it is considered that the overlay error marker may have been damaged during the manufacturing process. In this case, multiple graphic selection boxes (ROI boxes) can be configured, and multiple alignment marks can be determined based on the configured graphic selection boxes.

[0075] If the integrity of the marking is greater than or equal to the integrity threshold, the overlay error marking is considered to have not been damaged during the manufacturing process and has a completion level that meets the threshold. In this case, overlay error measurement can be performed directly based on the overlay error marking. Therefore, only one graphic selection box needs to be configured in this situation, and the alignment mark can be determined based on this graphic selection box. By determining the integrity of the overlay error marking, the number of graphic selection boxes that need to be configured can be determined according to the specific value of the integrity, so that the corresponding alignment mark can be selected according to the corresponding number of graphic selection boxes.

[0076] In one exemplary embodiment of this disclosure, for step S110, determining the multiple alignment marks corresponding to the current batch of wafers can be performed through the following steps: determining the graphic selection position corresponding to the current batch of wafers; obtaining the number of graphic selection positions, configuring a corresponding number of graphic selection boxes according to the number of positions; and performing graphic marking processing on the current batch of wafers based on the determined graphic selection positions and graphic selection boxes to obtain multiple alignment marks.

[0077] The graphic selection location can be the specific location within the current test product used to select alignment marks. The number of locations can be the specific number of graphic selection locations. The graphic mark processing can be the process of selecting alignment marks within the current test product.

[0078] When the integrity of the overlay error mark is less than the preset integrity, multiple graphic selection boxes can be configured to select the alignment mark. Before determining the alignment mark, the graphic selection position can be determined in the current batch of wafers according to requirements. For example, the graphic selection position corresponding to the current batch of wafers can be determined based on the product graphic distribution characteristics of the current batch of wafers. After determining the graphic selection position, the specific number of graphic selection positions, i.e., the number of positions, can be obtained. For example, the number of positions in a current batch of wafers can be 8, 10, 25, etc.

[0079] After obtaining the number of locations, the corresponding graphic selection box can be configured according to the number of locations. That is, one graphic selection box is configured for each graphic selection location. For example, the shape of the image selection box can be a rectangle.

[0080] After configuring the graphic selection box, graphic marking can be performed on the selected locations on the wafers of the current batch. The graphic selection box selects multiple rectangular areas at the corresponding graphic selection locations. The graphic signals of the rectangular areas selected in the ROI are used as alignment marks; for example, the grayscale signals selected in the ROI are used as alignment marks. After determining multiple alignment marks, the selected alignment marks can be used as the data basis for measuring the overlay error of the wafers of the current batch, and the corresponding measurement results can be obtained.

[0081] In one exemplary embodiment of this disclosure, the pattern selection position corresponding to the current batch of wafers is determined by the following steps: obtaining the identifier type of the overlay error identifier of the current batch of wafers; determining the symmetry center point corresponding to the current batch of wafers; determining at least one pattern selection direction corresponding to the current test product based on the symmetry center point; and determining the pattern selection position corresponding to each pattern selection direction based on the identifier type.

[0082] The marking type can be a specific type of overprint error marking. The symmetry center point can be the center point corresponding to the current test product. The graphic selection direction can be the specific direction used to select the alignment mark in the exposure graphic of the current test product.

[0083] Before determining the pattern selection location in the current batch of wafers, you can first determine the marking type of the overlay error marking for the current batch of wafers; for example, refer to Figure 2 , Figure 2 The illustration schematically depicts graphic identifiers corresponding to different identifier types according to exemplary embodiments of the present disclosure. Identifier types may include box-in-box identifiers, advanced image metric (AIM) identifiers, and so on. Figure 2 As shown, Figure 2 (a) The Box in Box logo is presented in a rectangular shape. The Box in Box logo consists of a large outer alignment mark rectangle and a small inner alignment mark rectangle. Figure 2 (b) The AIM marker is presented as a raised bar shape; the AIM marker includes an inner alignment mark that is immediately adjacent to both the horizontal and vertical coordinate axes and an outer alignment mark that is outside the inner alignment mark.

[0084] After determining the identification type corresponding to the current batch of wafers, the center point of symmetry for the graphic identification can be further determined based on the identification type. For example, the center point of symmetry for a Box in Box identification can be the center of a rectangular identification; the center point of symmetry for an AIM identification can be the center of multiple bar graphic identifications in different areas. After determining the center point of symmetry for the graphic identification, one or more graphic selection directions corresponding to the current test product can be determined based on the center point of symmetry.

[0085] After determining the pattern selection direction, the pattern selection position for each pattern selection direction in the current batch of wafers can be determined based on the pattern features corresponding to the identifier type. That is, the position of each raised bar-shaped pattern in each pattern selection direction is considered a pattern selection position, so that alignment marks can be determined subsequently based on the pattern selection position. By determining the identifier pattern features according to the identifier type, the pattern selection position for the bounding box alignment mark can be determined based on the identifier pattern features.

[0086] In one exemplary embodiment of this disclosure, determining the graphic selection position corresponding to each graphic selection direction based on the identifier type includes: determining the graphic identifier features of the current batch of wafers based on the identifier type; determining the inner border graphic selection position in each graphic selection direction based on the graphic identifier features; and determining the outer border graphic selection position of the current batch of wafers based on the graphic identifier features.

[0087] The graphic identifier feature can be the specific feature corresponding to the graphic identifier of the current batch of wafers. The inner border graphic selection position can be the graphic selection position used to determine the graphic identifier of the current layer. The outer border graphic selection position can be the graphic selection position used to determine the graphic identifier of the previous layer.

[0088] After determining the identifier type corresponding to the current batch of wafers, the pattern selection position in each pattern selection direction within the current batch of wafers can be determined based on the identifier type. (Continue to refer to...) Figure 2 For the "Box in Box" label, the graphic characteristic of the overprinting error label is that it is displayed in a rectangular shape. Using the center point of the rectangle as a reference, the position of the outer border graphic is used as the selected position for the outer border graphic, and the position of the inner border graphic is used as the selected position for the inner border graphic. The deviation between the center points of the outer and inner border graphics is the overprinting error.

[0089] For AIM signage, a coordinate system can be established with the center point of symmetry as the origin, the horizontal axis as the X-axis, and the vertical axis as the Y-axis. The first and third quadrants of this coordinate system can be used as one direction for graphic selection, while the second and fourth quadrants can be used as another. In the first direction, the signage closest to the X-axis is used as the inner border, and the selection position is determined based on the graphic characteristics of this closest signage. Similarly, in the second direction, the signage closest to the Y-axis is used as the inner border, and the selection position is determined based on the graphic characteristics of this closest signage.

[0090] For the outer border of the AIM logo, in both the first and second graphic selection directions, the graphic adjacent to the inner border graphic can be used as the outer border graphic, and the selection position of the outer border graphic can be determined on the outer border graphic. After determining multiple graphic selection positions, a graphic selection box (ROI box) can be configured for each graphic selection position, as shown in the reference. Figure 3 , Figure 3 The illustration schematically shows a diagram of determining a graphical selection box based on a current test product according to an exemplary embodiment of the present disclosure. Figure 3 It can include 3 graphic selection boxes. Configuring multiple ROI boxes for identification selection is to select a higher quality image and eliminate the impact on measurement and overlay errors when the image is damaged in the middle of the process.

[0091] In one exemplary embodiment of this disclosure, determining the mark quality value corresponding to each alignment mark includes: determining the overlay error corresponding to each alignment mark; determining the overlay error deviation and the standard deviation of the overlay error deviation corresponding to each alignment mark based on the overlay error; determining the mark quality value according to the overlay error, the overlay error deviation, and the standard deviation of the overlay error deviation; the mark quality value. Where MQ represents the mark quality value of the alignment mark, OVL represents the overprinting error of the alignment mark, Qmerit represents the overprinting error deviation of the alignment mark, and Qmeritδ² represents the standard deviation of the overprinting error deviation of the alignment mark.

[0092] Among them, the standard deviation of the overprinting error can be used as a parameter value to measure whether the quality of the marking is stable.

[0093] After identifying multiple alignment marks corresponding to the current batch of wafers, the overlay error for each alignment mark can be determined. Specifically, the overlay error for each alignment mark can be represented using OVL (Optical Value Level). When calculating the overlay error for an alignment mark, the grayscale signal selected within the inner frame and the grayscale signal selected within the outer frame of that alignment mark can be determined. The overlay deviations of these two grayscale signals relative to the X and Y axes are then determined, and the overlay error for the alignment mark is determined based on these X and Y axis overlay deviations.

[0094] After determining the overlay error of each alignment mark, the overlay error deviation and standard deviation of the overlay error deviation corresponding to each alignment mark can be determined based on the determined overlay error. The overlay error deviation can reflect the quality of the alignment mark and can be represented by Qmerit; the standard deviation of the overlay error deviation can reflect the stability of the alignment mark and can be represented by Qmeritδ².

[0095] After determining the above data, the mark quality (MQ) can be determined based on the overlay error, overlay error deviation and overlay error deviation standard deviation corresponding to each alignment mark, as shown in Formula 1.

[0096] (Formula 1)

[0097] Wherein, MQ can represent the mark quality value of the alignment mark, OVL can represent the overprinting error of the alignment mark, Qmerit can be the overprinting error deviation of the alignment mark, and Qmeritδ² can be the standard deviation of the overprinting error deviation of the alignment mark. The standard deviation of the overprinting error deviation can be obtained by using the standard deviation calculation formula.

[0098] Based on the determined mark quality value, the quality of the alignment mark determined for each ROI box can be determined, and it can be determined whether the alignment mark was damaged during the manufacturing process.

[0099] In one exemplary embodiment of this disclosure, the overlay error deviation and standard deviation of the overlay error corresponding to each alignment mark are determined based on the overlay error, which can be performed through the following steps: determining the overlay error derivative corresponding to the overlay error; determining the overlay error deviation based on the overlay error and the overlay error derivative; determining the standard deviation of the overlay error deviation based on the overlay error deviation; the overlay error deviation Qmerit = OVL' - OVL; where Qmerit represents the overlay error deviation of the alignment mark, OVL represents the overlay error of the alignment mark, and OVL' represents the overlay error derivative of the alignment mark.

[0100] The overlay error derivative can be any derivative of the overlay error. For example, the overlay error derivative can be the first derivative of the overlay error.

[0101] After determining the overlay error corresponding to each alignment mark, the derivative of the overlay error corresponding to each alignment mark can be determined based on the overlay error. For example, the first derivative, second derivative, and other derivatives of the overlay error corresponding to the alignment mark can be determined. (Reference) Figure 4 , Figure 4A schematic diagram illustrates the results of various derivatives of the overlay error according to an exemplary embodiment of this disclosure. From Figure 4 As can be seen from this, after calculating the derivatives of each order for the overlay error, there is a difference between the ideal state and the actual state of the overlay error corresponding to each derivative.

[0102] Based on the differences in the derivatives of the overlay error, the first derivative of the overlay error can be used as the data basis for calculating the overlay error deviation. After determining the derivative of the overlay error, the overlay error deviation can be determined based on the overlay error and its derivative. Specifically, the calculation method for the overlay error deviation is shown in Formula 2.

[0103] Qmerit=OVL'-OVL (Formula 2)

[0104] Where Qmerit can represent the overprinting error deviation of the alignment mark, OVL can represent the overprinting error of the alignment mark, and OVL' can represent the derivative of the overprinting error of the alignment mark.

[0105] After determining the overprinting error deviation, the standard deviation of the overprinting error deviation can be determined based on the overprinting error deviation. The determined overprinting error deviation and the standard deviation of the overprinting error deviation can be used as the data basis for calculating the mark quality value.

[0106] In one exemplary embodiment of this disclosure, step S130, based on the determined marker quality value, filters multiple alignment markers to determine the target alignment marker, including: determining the average marker quality value corresponding to the multiple marker quality values; and taking the alignment marker with a marker quality value less than the average marker quality value as the target alignment marker.

[0107] The average mark quality can be a value obtained by averaging the mark quality values ​​corresponding to multiple alignment marks.

[0108] After determining the marker quality values ​​corresponding to all alignment markers, the alignment markers can be filtered based on the calculated marker quality values ​​to obtain the target alignment markers. For example, the average of all calculated marker quality values ​​can be calculated to obtain the average marker quality. For marker quality values, the smaller the value, the better the alignment marker quality. After obtaining the average marker quality, alignment markers with marker quality values ​​greater than or equal to the average marker quality (i.e., low-quality images) can be filtered out, and alignment markers with marker quality values ​​less than the average marker quality can be selected as the target alignment markers.

[0109] refer to Figure 5 , Figure 5 This schematically illustrates a process of determining a target alignment mark from a plurality of alignment marks according to an exemplary embodiment of the present disclosure. Figure 5 As can be seen, after the identifier filtering process, target alignment markers numbered 1-4 were obtained, and... Figure 5 The image shows the graphic identifiers of the ROIs selected by the boxes corresponding to numbers 3 and 4, as well as the graphic identifiers selected by the outer border.

[0110] In addition, the median of the mark quality values ​​of multiple alignment marks can be determined as the median quality value. Alignment marks with mark quality values ​​less than the median quality value are used as target alignment marks. Based on the determined target alignment marks, the overlay error statistics corresponding to the current batch of wafers can be performed, resulting in more accurate measurement data.

[0111] refer to Figure 6 , Figure 6 The diagram illustrates the variation of the overprinting error and overprinting error deviation values ​​after identification and screening according to an exemplary embodiment of the present disclosure. Figure 6 The example illustrates the overlay error (OVX) in the X-axis direction of the current batch of wafers, showing the data variation relationship between the overlay error (OVX) in the X-axis direction and the overlay error deviation (QMERIT_IN_OVX) in the X-axis direction of the current batch of wafers. Figure 6 As can be seen, in the relevant schemes, the overlay error and overlay error deviation are calculated based on the overlay error marks of the current batch of wafers. However, since the overlay error marks may be damaged or intermittently damaged, the calculated overlay error deviation deviates from the trend of the overlay error. The proposed solution, after calculating the mark quality values ​​of multiple alignment marks, selects target alignment marks whose mark quality values ​​meet specific conditions. Because the selected target alignment marks meet the specific conditions and have high quality, the trend of the overlay error deviation calculated based on the target alignment marks is closer to the trend of the overlay error, and the data change is more stable.

[0112] In one exemplary embodiment of this disclosure, step S140, determining the error correction result corresponding to the current batch of wafers based on the target alignment mark, includes: determining the target mark signal of the target alignment mark; analyzing and processing the target mark signal to determine the target center point corresponding to the target alignment mark; determining the target overlay error value corresponding to the target alignment mark based on the target center point; performing simulation calculation on the target overlay error value to determine the overlay error compensation value corresponding to the current batch of wafers; and using the overlay error compensation value as the error correction result.

[0113] The target marker signal can be the signal representation corresponding to the target alignment mark; for example, the target marker signal can be the grayscale signal of the target alignment mark. The target center point can be the center position point determined based on the target alignment mark. The target overprinting error value can be the overprinting error value determined based on the target alignment mark. The overprinting error compensation value can be the overprinting error offset value determined to correct the target overprinting error value.

[0114] After identifying the robust image, the target marker signal corresponding to it can be acquired, i.e., the grayscale signal of the robust image. A grayscale signal divides the brightness variation between the brightest and darkest areas into several segments. After obtaining the grayscale signal of the robust image, it is analyzed and processed. Based on the signal analysis results, the target center point corresponding to the robust image is determined. (Reference) Figure 7 , Figure 7 This illustration schematically depicts a method for determining overlay error deviation values ​​based on target alignment marks according to an exemplary embodiment of the present disclosure. Figure 7 As shown, after performing signal analysis and processing on the grayscale signal of the target alignment mark, the target center point corresponding to the grayscale signal can be determined.

[0115] After determining the target center point, the target overlay error value corresponding to the target alignment mark can be determined based on the target center point. Specifically, the target overlay error value can be calculated based on the pattern alignment direction corresponding to the current test product. After determining the target overlay error value for the current batch of wafers, the target overlay error value can be transmitted to the computing center, where it will perform simulation calculations to determine the overlay error compensation value for the current batch of wafers. The overlay error compensation value is used as the error correction result so that it can be applied to the exposure alignment process of the next batch of wafers.

[0116] In one exemplary embodiment of this disclosure, determining the target overlay error value corresponding to the target alignment mark based on the target center point includes: obtaining the graphic alignment direction corresponding to the current test product; the graphic alignment direction includes a first alignment direction and a second alignment direction; determining the first overlay error value corresponding to the first alignment direction based on the target center point; determining the second overlay error value corresponding to the second alignment direction based on the target center point; and generating the target overlay error value based on the first overlay error value and the second overlay error value.

[0117] The alignment direction can be a specific direction used for aligning the graphics. The first alignment direction can be an alignment direction along a first coordinate axis determined based on the target center point. The second alignment direction can be an alignment direction along a second coordinate axis determined based on the target center point. The first overprinting error value can be an overprinting error value determined based on the first alignment direction. The second overprinting error value can be an overprinting error value determined based on the second alignment direction.

[0118] After the target alignment mark is determined, the pattern alignment direction corresponding to the current test product can be obtained. For the current batch of wafers disclosed herein, based on the determined target center point, two pattern alignment directions, namely the first alignment direction and the second alignment direction, can be determined. The first alignment direction can be the pattern alignment direction corresponding to the X-axis, and the second alignment direction can be the pattern alignment direction corresponding to the Y-axis.

[0119] For the current batch of wafers, the first set of etching error values ​​corresponding to the first alignment direction can be determined based on the target center point. (Continue to refer to...) Figure 7 After performing signal analysis and processing on the grayscale signals corresponding to the inner and outer borders of the target alignment mark, the target center point corresponding to the inner border and the target center point corresponding to the outer border can be determined respectively. The difference between the target center point corresponding to the inner border and the target center point corresponding to the outer border is the overlay error value of the current batch of wafers in the first alignment direction (X-axis). Figure 7 In As shown, this is the first overlay error value (overlay error value in the X-axis direction). Similarly, based on the target center point, the second overlay error value (overlay error value in the Y-axis direction) corresponding to the second alignment direction can be determined. express.

[0120] After determining the first set of engraving error values ​​corresponding to the first alignment direction and the second alignment direction respectively. Error value compared with the second set of engravings Then, based on the first set of engraving error values Error value compared with the second set of engravings The process generates a target overlay error value, which is then used to determine the overlay error compensation value for the next batch of wafers. Specifically, by calculating the grayscale signal of the selected ROI, the overlay error is simulated and analyzed on the corresponding data to obtain the overlay error compensation value. This compensation value serves as the error correction result, which is then used for compensation processing during wafer exposure to improve product yield.

[0121] In one exemplary embodiment of this disclosure, step S140, which involves performing exposure alignment processing on the next batch of wafers based on the error correction result, includes: sending the error correction result to the exposure alignment device; and controlling the exposure alignment device to adjust the corresponding pattern alignment parameters based on the error correction result, so that the exposure alignment device performs exposure alignment processing on the next batch of wafers based on the pattern alignment parameters.

[0122] The exposure alignment equipment can be an operating device used to align and expose the product to be processed. The graphic alignment parameters can be specific parameters used to guide the alignment of the current graphic layer with the previous graphic layer.

[0123] After obtaining the error correction results, these results can be fed back to the exposure alignment equipment. Upon receiving the error correction results, the system can control the exposure alignment equipment to adjust the corresponding pattern alignment parameters based on the error correction results. After completing the pattern alignment parameter adjustment operation, the exposure alignment equipment can perform exposure alignment processing on the next batch of wafers based on the adjusted pattern alignment parameters, thereby improving product yield.

[0124] It should be noted that the terms "first" and "second" used in this disclosure are only for distinguishing different graphic alignment directions and different overprinting errors, and should not impose any limitations on this disclosure.

[0125] In summary, the overlay error correction method disclosed herein involves: acquiring the current batch of wafers; identifying multiple alignment marks corresponding to the current batch of wafers; determining the mark quality value corresponding to each alignment mark; determining the mark quality value based on the overlay error and overlay error deviation of each alignment mark; filtering the multiple alignment marks based on the determined mark quality value to identify the target alignment mark; and determining the error correction result corresponding to the current batch of wafers based on the target alignment mark, and then performing exposure alignment processing on the next batch of wafers based on the error correction result. On the one hand, calculating the overlay error based on the target alignment mark obtained by filtering multiple mark quality values ​​can reduce the problem of affecting the accuracy of overlay error due to damage to the alignment marks. On the other hand, using the error correction result calculated based on the target alignment mark in the exposure alignment processing of the next batch of wafers can effectively improve product yield.

[0126] It should be noted that although the steps of the method in this invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0127] Furthermore, in this example embodiment, an overlay error correction system is also provided. (See reference...) Figure 8 The overlay error correction system 800 may include: an exposure alignment device 810, a marking error measuring device 820, and a calculation device 830.

[0128] Specifically, the exposure alignment device 810 is used to acquire the initial current batch of wafers, perform exposure alignment processing on the initial current batch of wafers, and obtain the current batch of wafers.

[0129] The marking error measurement device 820 is used to determine a specified number of alignment marks based on the integrity of the overlay error markings of the current batch of wafers, and to determine the overlay error deviation value corresponding to the current batch of wafers based on the alignment marks. The device acquires the overlay error markings corresponding to the current batch of wafers, and in step S810, determines whether the overlay error markings are damaged, thus obtaining the integrity of the overlay error markings. In step S820, if the integrity of the overlay error markings is greater than an integrity threshold (i.e., the overlay error markings are not damaged), a graphic selection box is configured to select an alignment mark; in step S830, if the integrity of the overlay error markings is less than or equal to the integrity threshold (i.e., the overlay error markings are damaged), multiple graphic selection boxes are configured to select alignment marks. Then, a target alignment mark is obtained by filtering based on the mark quality values ​​of multiple alignment marks, and the overlay error deviation value of the current batch of wafers is calculated based on the target alignment mark.

[0130] The computing device 830 is used to determine the overprinting error compensation value based on the overprinting error deviation value and send the overprinting error compensation value to the exposure alignment device. Through the overprinting error correction system described above, the impact of damaged alignment marks on the overprinting error accuracy can be eliminated, thereby improving the overprinting error accuracy and ultimately increasing the product yield.

[0131] Furthermore, in this example embodiment, an overlay error correction device is also provided. (See reference...) Figure 9 The overlay error correction device 900 may include: an alignment mark determination module 910, a mark measurement value determination module 920, a mark screening module 930, and an error correction module 940.

[0132] Specifically, the alignment mark determination module 910 is used to acquire the current batch of wafers, determine multiple alignment marks corresponding to the current batch of wafers, and the overlay error and overlay error deviation corresponding to each alignment mark; the mark measurement value determination module 920 is used to determine the mark quality value corresponding to each alignment mark based on the overlay error and overlay error deviation of each alignment mark; the mark filtering module 930 is used to filter multiple alignment marks based on the determined mark quality value to determine the target alignment mark; and the error correction module 940 is used to determine the error correction result corresponding to the current batch of wafers based on the target alignment mark, so as to perform exposure alignment processing on the next batch of wafers based on the error correction result.

[0133] In one exemplary embodiment of this disclosure, the overlay error correction device 900 further includes a graphics library configuration module, configured to: acquire overlay error identifiers corresponding to the current batch of wafers; acquire reference identifier signals and actual identifier signals corresponding to the overlay error identifiers respectively; determine the identifier integrity of the overlay error identifiers based on the actual identifier signals and reference identifier signals; if the identifier integrity is less than an integrity threshold, configure multiple graphic selection boxes to determine multiple alignment marks based on the multiple graphic selection boxes; if the identifier integrity is greater than or equal to the integrity threshold, configure one graphic selection box to determine alignment marks based on the graphic selection box.

[0134] In one exemplary embodiment of this disclosure, the number of alignment marks is multiple, and the alignment mark determination module 910 includes a test mark determination unit, used to: determine the pattern selection position corresponding to the current batch of wafers; obtain the number of position selection positions, configure a corresponding number of pattern selection boxes according to the number of positions; and perform pattern marking processing on the current batch of wafers based on the determined pattern selection positions and pattern selection boxes to obtain multiple alignment marks.

[0135] In one exemplary embodiment of this disclosure, the test identifier determination unit includes a pattern position determination unit, configured to: obtain the identifier type of the overlay error identifier of the current batch of wafers; determine the symmetry center point corresponding to the current batch of wafers; determine at least one pattern selection direction corresponding to the current test product based on the symmetry center point; and determine the pattern selection position corresponding to each pattern selection direction based on the identifier type.

[0136] In one exemplary embodiment of this disclosure, the graphic position determination unit includes a graphic position determination subunit, configured to: determine the graphic identification features of the current batch of wafers based on the identification type; determine the inner border graphic selection position in each graphic selection direction based on the graphic identification features; and determine the outer border graphic selection position of the current batch of wafers based on the graphic identification features.

[0137] In one exemplary embodiment of this disclosure, the mark measurement value determination module 920 includes a mark measurement value determination unit, configured to: determine the overprinting error corresponding to each alignment mark; determine the overprinting error deviation and the standard deviation of the overprinting error deviation corresponding to each alignment mark based on the overprinting error; determine the mark quality value according to the overprinting error, the overprinting error deviation, and the standard deviation of the overprinting error deviation; the mark quality value Where MQ represents the mark quality value of the alignment mark, OVL represents the overprinting error of the alignment mark, Qmerit represents the overprinting error deviation of the alignment mark, and Qmeritδ² represents the standard deviation of the overprinting error deviation of the alignment mark.

[0138] In one exemplary embodiment of this disclosure, the identification measurement value determination unit includes an overlay error parameter determination subunit, used for: determining the overlay error derivative corresponding to the overlay error; determining the overlay error deviation based on the overlay error and the overlay error derivative; determining the standard deviation of the overlay error deviation based on the overlay error deviation; the overlay error deviation Qmerit=OVL'-OVL; where Qmerit represents the overlay error deviation of the alignment mark, OVL represents the overlay error of the alignment mark, and OVL' represents the overlay error derivative of the alignment mark.

[0139] In one exemplary embodiment of this disclosure, the number of alignment marks is multiple, and the mark filtering module 930 includes an identifier filtering unit for: determining the average mark quality value corresponding to multiple mark quality values; and selecting alignment marks with mark quality values ​​less than the average mark quality value as target alignment marks.

[0140] In one exemplary embodiment of this disclosure, the error correction module 940 includes an error correction unit, configured to: determine the target mark signal of the target alignment mark; analyze and process the target mark signal to determine the target center point corresponding to the target alignment mark; determine the target overlay error value corresponding to the target alignment mark based on the target center point; perform simulation calculation on the target overlay error value to determine the overlay error compensation value corresponding to the current batch of wafers; and use the overlay error compensation value as the error correction result.

[0141] In one exemplary embodiment of this disclosure, the error correction unit includes an error correction subunit, configured to: obtain the graphic alignment direction corresponding to the current test product; the graphic alignment direction includes a first alignment direction and a second alignment direction; determine a first overlay error value corresponding to the first alignment direction based on the target center point; determine a second overlay error value corresponding to the second alignment direction based on the target center point; and generate a target overlay error value based on the first overlay error value and the second overlay error value.

[0142] In one exemplary embodiment of this disclosure, the overlay error correction device 900 includes a correction result feedback module, used to: send the error correction result to the exposure alignment device; and control the exposure alignment device to adjust the corresponding pattern alignment parameters based on the error correction result, so that the exposure alignment device performs exposure alignment processing on the next batch of wafers based on the pattern alignment parameters.

[0143] The specific details of the virtual modules of each overlay error correction device mentioned above have been described in detail in the corresponding overlay error correction methods, so they will not be repeated here.

[0144] It should be noted that although several modules or units of the overprinting error correction device have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0145] Furthermore, in an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0146] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented as entirely hardware embodiments, entirely software embodiments (including firmware, microcode, etc.), or embodiments combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.”

[0147] The following reference Figure 10 To describe an electronic device 1000 according to such an embodiment of the present disclosure. Figure 10 The electronic device 1000 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0148] like Figure 10 As shown, the electronic device 1000 is manifested in the form of a general-purpose computing device. The components of the electronic device 1000 may include, but are not limited to: at least one processing unit 1010, at least one storage unit 1020, a bus 1030 connecting different system components (including storage unit 1020 and processing unit 1010), and a display unit 1040.

[0149] The storage unit stores program code that can be executed by the processing unit 1010, causing the processing unit 1010 to perform the steps described in the "Exemplary Methods" section above according to various exemplary embodiments of this disclosure.

[0150] Storage unit 1020 may include readable media in the form of volatile storage units, such as random access memory (RAM) 1021 and / or cache memory 1022, and may further include read-only memory (ROM) 1023.

[0151] Storage unit 1020 may also include a program / utility 1024 having a set (at least one) program module 1025, such program module 1025 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0152] Bus 1030 can represent one or more of several types of bus structures, including memory cell bus or memory cell controller, peripheral bus, graphics acceleration port, processing unit, or local bus using any of the multiple bus structures.

[0153] Electronic device 1000 can also communicate with one or more external devices 1070 (e.g., keyboard, pointing device, Bluetooth device, etc.), one or more devices that enable a user to interact with electronic device 1000, and / or any device that enables electronic device 1000 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1050. Furthermore, electronic device 1000 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1060. As shown, network adapter 1060 communicates with other modules of electronic device 1000 via bus 1030. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0154] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0155] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section above.

[0156] refer to Figure 11 As shown, a program product 1100 for implementing the above-described method according to an embodiment of the present invention is described. It may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0157] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0158] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0159] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0160] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0161] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0162] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0163] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method of overlay error correction, the method comprising: include: Obtain the current batch of wafers, determine the multiple alignment marks corresponding to the current batch of wafers, and the overlay error and overlay error deviation corresponding to each alignment mark; Based on the overprinting error and overprinting error deviation of each alignment mark, the mark quality value corresponding to each alignment mark is determined, including: determining the overprinting error corresponding to each alignment mark; determining the overprinting error deviation and overprinting error deviation standard deviation corresponding to each alignment mark based on the overprinting error; and determining the mark quality value according to the overprinting error, the overprinting error deviation and the overprinting error deviation standard deviation. the marker mass value ; Wherein, MQ represents the mark quality value of the alignment mark, OVL represents the overprinting error of the alignment mark, Qmerit represents the overprinting error deviation of the alignment mark, and Qmeritδ² represents the standard deviation of the overprinting error deviation of the alignment mark. Based on the determined quality value of the marker, multiple alignment markers are filtered to determine the target alignment marker; Based on the target alignment mark, the error correction result corresponding to the current batch of wafers is determined, and the next batch of wafers is exposed and aligned based on the error correction result.

2. The method of claim 1, wherein, The process of obtaining the current batch of wafers includes: Obtain the overlay error identifier corresponding to the current batch of wafers; The reference marking signal and the actual marking signal corresponding to the overlay error marking are obtained respectively; The integrity of the overlay error mark is determined based on the actual mark signal and the reference mark signal; If the integrity of the identifier is less than the integrity threshold, then multiple graphic selection boxes are configured to determine multiple alignment marks based on the multiple graphic selection boxes; If the integrity of the identifier is greater than or equal to the integrity threshold, then a graphic selection box is configured to determine the alignment mark based on the graphic selection box.

3. The method of claim 1, wherein, The number of alignment marks is multiple, and determining the multiple alignment marks corresponding to the current batch of wafers includes: Determine the pattern selection position corresponding to the current batch of wafers; Obtain the number of positions of the graphic selection location, and configure a corresponding number of graphic selection boxes according to the number of positions; Based on the determined graphic selection position and the graphic selection box, graphic marking processing is performed on the current batch of wafers to obtain multiple alignment marks.

4. The method of claim 3, wherein, Determining the pattern selection position corresponding to the current batch of wafers includes: Obtain the identifier type of the overlay error identifier for the current batch of wafers; Determine the center point of symmetry corresponding to the current batch of wafers; Based on the symmetry center point, at least one pattern selection direction corresponding to the current batch of wafers is determined; Based on the identifier type, determine the graphic selection position corresponding to each graphic selection direction.

5. The method of claim 4, wherein, The step of determining the graphic selection position corresponding to each graphic selection direction based on the identifier type includes: The graphic identification features of the current batch of wafers are determined based on the identification type; Based on the graphic identifier features, determine the inner border graphic selection position in each graphic selection direction; Based on the graphic identifier features, the selection position of the outer border graphic of the current batch of wafers is determined.

6. The method of claim 1, wherein, The step of determining the overlay error deviation and standard deviation of the overlay error corresponding to each alignment mark based on the overlay error includes: Determine the overlay error derivative corresponding to the overlay error; The overprinting error deviation is determined based on the overprinting error and its derivative. The standard deviation of the overlay error deviation is determined based on the overlay error deviation. The overlay error deviation Qmerit = OVL' - OVL; Where Qmerit represents the overprinting error deviation of the alignment mark, OVL represents the overprinting error of the alignment mark, and OVL' represents the derivative of the overprinting error of the alignment mark.

7. The method of claim 1, wherein, The number of alignment marks is multiple, and the process of filtering the multiple alignment marks based on the determined mark quality value to determine the target alignment mark includes: Determine the average marker quality corresponding to the plurality of marker quality values; Alignment marks whose quality value is less than the average quality value of the marks are used as the target alignment marks.

8. The method of claim 1, wherein, The step of determining the error correction result corresponding to the current batch of wafers based on the target alignment mark includes: Determine the target alignment mark signal; The target marker signal is analyzed and processed to determine the target center point corresponding to the target alignment mark; Based on the target center point, determine the target overlay error value corresponding to the target alignment mark; The target overlay error value is simulated and calculated to determine the overlay error compensation value corresponding to the current batch of wafers; The overlay error compensation value is used as the error correction result.

9. The method of claim 8, wherein, The step of determining the target overlay error value corresponding to the target alignment mark based on the target center point includes: Obtain the pattern alignment direction corresponding to the current batch of wafers; the pattern alignment direction includes a first alignment direction and a second alignment direction; Based on the target center point, determine the first set of engraving error values ​​corresponding to the first alignment direction; Based on the target center point, determine the second set of engraving error values ​​corresponding to the second alignment direction; The target overlay error value is generated based on the first overlay error value and the second overlay error value.

10. The method of claim 1, wherein, The exposure alignment process for the next batch of wafers based on the error correction result includes: The error correction result is sent to the exposure alignment device; The exposure alignment device is controlled to adjust the corresponding pattern alignment parameters based on the error correction result, so that the exposure alignment device performs exposure alignment processing on the next batch of wafers based on the pattern alignment parameters.

11. An overlay error correction device, characterized by, include: The alignment mark determination module is used to acquire the current batch of wafers, determine multiple alignment marks corresponding to the current batch of wafers, and the overlay error and overlay error deviation corresponding to each alignment mark; A marker measurement value determination module is used to determine the marker quality value corresponding to each alignment mark based on the overprinting error and overprinting error deviation of each alignment mark, including: determining the overprinting error corresponding to each alignment mark; determining the overprinting error deviation and overprinting error deviation standard deviation corresponding to each alignment mark based on the overprinting error; and determining the marker quality value according to the overprinting error, the overprinting error deviation, and the overprinting error deviation standard deviation. the marker mass value ; Wherein, MQ represents the mark quality value of the alignment mark, OVL represents the overprinting error of the alignment mark, Qmerit represents the overprinting error deviation of the alignment mark, and Qmeritδ² represents the standard deviation of the overprinting error deviation of the alignment mark. The marker filtering module is used to filter multiple alignment markers based on the determined marker quality value to determine the target alignment marker; An error correction module is used to determine the error correction result corresponding to the current batch of wafers based on the target alignment mark, so as to perform exposure alignment processing on the next batch of wafers based on the error correction result.

12. An electronic device, comprising: include: processor; as well as A memory storing computer-readable instructions that, when executed by the processor, implement the overlay error correction method according to any one of claims 1 to 10.

13. A computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the overlay error correction method according to any one of claims 1 to 10.

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