Reference current temperature compensation circuit and reference current temperature compensation control method

Abstract

The application discloses a reference current temperature compensation circuit and a reference current temperature compensation control method, and the reference current temperature compensation circuit comprises a PTAT current generation circuit, a temperature compensation module and a CTAT current output module; the PTAT current generation circuit is used for generating a PTAT current; the temperature compensation module is used for generating a temperature coefficient current; and the CTAT current output module is used for outputting to a set output end through current mirror mirroring. The reference current temperature compensation circuit and the reference current temperature compensation control method can complete the temperature compensation of the current by using a few devices without affecting the reference voltage in the band gap reference circuit, obtain a reference current with zero temperature coefficient, or directly generate a reference current with zero temperature coefficient by using a PTAT current, thereby saving the area of the chip and reducing the production cost to a certain extent. In addition, the current has high stability and is less affected by a power supply voltage, and can well adapt to market needs.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronic circuit, and relates to a temperature compensation circuit, in particular to a reference current temperature compensation circuit and a reference current temperature compensation control method. BACKGROUND

[0002] In circuit design, the use of reference voltage and reference current is very extensive. Such so-called reference voltage and current is generally a direct current, and the relationship with temperature is determined, for example, PTAT (proportional to absolute temperature) voltage and current and CTAT (compensated to absolute temperature) voltage and current.

[0003] Generally speaking, the use of bandgap reference is very common in circuit design to design reference voltage and reference current. Taking reference voltage as an example, the general idea is to add two voltages with opposite temperature coefficients with appropriate weights for the purpose of zero temperature coefficient, and the sum of the voltages is a voltage with zero temperature coefficient: for voltages V1 and V2 that change in opposite directions with temperature, select appropriate α and β to satisfy the condition Thus, the voltage obtained by adding the weights α and β of voltages V1 and V2 has the characteristic of zero temperature coefficient, that is, V REF = αV1 + βV2.

[0004] In a bandgap reference voltage circuit, the difference between the base-emitter voltages of bipolar transistors working at unequal current densities is usually selected as a positive temperature coefficient voltage V1 proportional to absolute temperature, and the base-emitter voltage of a bipolar transistor is selected as a negative temperature coefficient voltage V2 inversely proportional to absolute temperature, and a reference voltage value V REF is obtained by adding the two voltages with appropriate weight values α and β.

[0005] Taking the classical bandgap reference circuit shown in Figure 1 , for example, the third transistor Q3 and the fourth transistor Q4 matched in size, which are connected in diode connection in the circuit, are selected, so the current density of their work is 1:N. Then the resistor R3 is connected at the junction of the collector and the base of the fourth transistor Q4, the other end of the resistor R3 is marked as point Y, and the junction of the collector and the base of the third transistor Q3 is marked as point X. Point X and point Y are connected as inputs to the operational amplifier A1, and the output is connected to the gates of the first P-channel MOS field effect transistor PM1 and the second P-channel MOS field effect transistor PM2, the purpose is to clamp the voltages of point X and point Y to equal voltages and provide bias voltage for the first P-channel MOS field effect transistor PM1 and the second P-channel MOS field effect transistor PM2.

[0006] The above structure realizes equivalent of the voltage difference of the third transistor Q3 and the fourth transistor Q4 with positive temperature coefficient to the voltage across the resistor R3, and the PTAT current of the second P-type channel MOS field effect transistor PM2 is mirrored to the branch of the third P-type channel MOS field effect transistor PM3 through the current mirror structure composed of the second P-type channel MOS field effect transistor PM2 and the third P-type channel MOS field effect transistor PM3, and is added to the resistor R4 to form the reference voltage V REF .

[0007] The conventional reference current circuit uses the above band-gap reference circuit to generate an adjustable positive temperature coefficient reference voltage at the Y point and combines the resistor R3 with positive temperature coefficient to obtain a zero temperature coefficient current with certain weight value, or uses the above band-gap reference circuit to generate an adjustable negative temperature coefficient reference voltage at the Y point and combines the resistor R3 with positive temperature coefficient to obtain a zero temperature coefficient current with certain weight value.

[0008] The above conventional band-gap reference voltage circuit cannot conveniently obtain the reference current while obtaining the reference voltage, and the above conventional reference current circuit uses a relatively complex circuit, uses a large number of devices, occupies a large chip area, and sacrifices the reference voltage in order to obtain a zero temperature coefficient current.

[0009] Therefore, there is an urgent need to design a new reference current circuit to overcome at least part of the above defects of the existing reference current circuit. SUMMARY

[0010] The present application provides a reference current temperature compensation circuit and a reference current temperature compensation control method, which can generate a reference current with zero temperature coefficient without affecting the generation of a reference voltage with zero temperature coefficient by a band-gap reference circuit, and can effectively resist the influence of power supply voltage fluctuation on the reference current.

[0011] To solve the above technical problems, according to one aspect of the present application, the following technical solution is adopted:

[0012] A reference current temperature compensation circuit, comprising:

[0013] a PTAT current generation circuit for generating a PTAT current;

[0014] a temperature compensation module for generating a temperature coefficient current; and

[0015] a CTAT current output module for outputting to a set output end through current mirroring.

[0016] As an embodiment of the present application, the temperature compensation module comprises:

[0017] a positive temperature coefficient current generation circuit for generating a positive temperature coefficient current; and

[0018] a negative temperature coefficient current generation circuit for generating a negative temperature coefficient current.

[0019] As an embodiment of the present application, the temperature compensation module comprises: a first transistor Q1, a second transistor Q2, a first N-type MOS transistor NM1, a second N-type MOS transistor NM2, a first resistor R1;

[0020] a gate of the first N-type MOS transistor NM1 is connected to the PTAT current generation circuit, a collector of the first transistor Q1, and a gate of the second N-type MOS transistor NM2, respectively;

[0021] a drain of the first N-type MOS transistor NM1 is connected to the CTAT current output module and a drain of the second N-type MOS transistor NM2, respectively;

[0022] a source of the first N-type MOS transistor NM1 is connected to a base of the first transistor Q1, a base of the second transistor Q2, and a first end of the first resistor R1, respectively;

[0023] a source of the second N-type MOS transistor NM2 is connected to a collector of the second transistor Q2, and an emitter of the first transistor Q1, a second end of the first resistor R1, and an emitter of the second transistor Q2 are grounded, respectively.

[0024] As an embodiment of the present application, the CTAT current output module comprises a low-voltage cascode current mirror for copying a reference current and outputting.

[0025] As an embodiment of the present application, the low-voltage cascode current mirror comprises a fifth P-type MOS transistor PM5, a sixth P-type MOS transistor PM6, a seventh P-type MOS transistor PM7, an eighth P-type MOS transistor PM8, and a second resistor R2;

[0026] a power supply voltage VCC is connected to a source of the fifth P-type MOS transistor PM5 and a source of the sixth P-type MOS transistor PM6, a drain of the fifth P-type MOS transistor PM5 is connected to a source of the seventh P-type MOS transistor PM7, and a drain of the sixth P-type MOS transistor PM6 is connected to a source of the eighth P-type MOS transistor PM8;

[0027] a gate of the fifth P-type MOS transistor PM5 is connected to a gate of the sixth P-type MOS transistor PM6, a drain of the seventh P-type MOS transistor PM7, and a first end of the second resistor R2;

[0028] The gate of the seventh P-type MOS PM7 is connected with the gate of the eighth P-type MOS PM8, the second end of the second resistor R2 and the temperature compensation module; the drain of the eighth P-type MOS PM8 is connected with the output port.

[0029] As an embodiment of the present application, the PTAT current generating circuit comprises a PTAT current source I1, a first P-type MOS PM1 and a second P-type MOS PM2, wherein the PTAT current source I1 is used to generate a PTAT current;

[0030] The positive pole of the PTAT current source I1 is connected with the drain of the first P-type MOS PM1, the gate of the first P-type MOS PM1 and the gate of the second P-type MOS PM2 respectively, and the negative pole of the PTAT current source I1 is grounded.

[0031] The power supply voltage VCC is connected with the source of the first P-type MOS PM1 and the source of the second P-type MOS PM2 respectively; and the drain of the second P-type MOS PM2 is connected with the temperature compensation module.

[0032] As an embodiment of the present application, the PTAT current generating circuit is realized by a bandgap reference circuit, which is used to generate a reference voltage and a PTAT current.

[0033] The bandgap reference circuit comprises a first operational amplifier A1, a first P-type MOS PM1, a second P-type MOS PM2, a third P-type MOS PM3, a fourth P-type MOS PM4, a third transistor Q3, a fourth transistor Q4, a third resistor R3 and a fourth resistor R4.

[0034] The power supply voltage VCC is connected with the source of the first P-type MOS PM1, the source of the second P-type MOS PM2, the source of the third P-type MOS PM3 and the source of the fourth P-type MOS PM4 respectively.

[0035] The gate of the first P-type MOS PM1 is connected with the gate of the second P-type MOS PM2, the gate of the third P-type MOS PM3, the gate of the fourth P-type MOS PM4 and the output end of the first operational amplifier A1 respectively.

[0036] The drain of the first P-type MOS PM1 is connected with the inverting input end of the first operational amplifier A1, the base of the third transistor Q3 and the collector of the third transistor Q3 respectively.

[0037] The drain of the second P-type MOS PM2 is connected with the non-inverting input end of the first operational amplifier A1 and the first end of the third resistor R3 respectively; the second end of the third resistor R3 is connected with the base of the fourth transistor Q4 and the collector of the fourth transistor Q4 respectively.

[0038] The drain of the third P-type MOS transistor PM3 is connected to the first end of the fourth resistor R4, and the drain of the fourth P-type MOS transistor PM4 is connected to the temperature compensation module.

[0039] The emitter of the third transistor Q3 is grounded, the emitter of the fourth transistor Q4 is grounded, and the second end of the fourth resistor R4 is grounded.

[0040] As an embodiment of the present application, the reference current temperature compensation circuit further comprises a reference voltage generating circuit configured to generate a reference voltage.

[0041] According to another aspect of the present application, a reference current temperature compensation control method is provided, which comprises the following steps:

[0042] In step S1, a PTAT current generating circuit generates a PTAT current.

[0043] In step S2, a temperature compensation module generates a temperature coefficient current according to the PTAT current generated by the PTAT current generating circuit.

[0044] In step S3, a CTAT current output module mirrors and outputs the temperature coefficient current generated by the temperature compensation module to a set output end.

[0045] The reference current temperature compensation circuit and the reference current temperature compensation control method provided by the present application can complete the temperature compensation of the current by using a small number of devices without affecting the reference voltage in the bandgap reference circuit, so as to obtain a reference current with zero temperature coefficient, or directly generate a reference current with zero temperature coefficient by using a PTAT current, thereby saving the chip area and reducing the production cost to a certain extent. In addition, the current has high stability and is less affected by the power supply voltage, and can well meet the market demand. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 FIG. 1 is a circuit schematic diagram of a traditional bandgap reference circuit.

[0047] Figure 2 FIG. 2 is a circuit schematic diagram of a reference current temperature compensation circuit according to an embodiment of the present application.

[0048] Figure 3 FIG. 3 is a circuit schematic diagram of a reference current temperature compensation circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0049] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0050] For further understanding of the present application, the preferred embodiments of the present application are described below in conjunction with the examples, but it should be understood that the description is only for further illustrating the features and advantages of the present application, and is not a limitation on the claims of the present application.

[0051] The description of this part is only for several typical embodiments, and the present application is not limited to the scope of the embodiment description. The same or similar prior art means and some technical features in the embodiments are replaced with each other, which is within the description and protection of the present application.

[0052] The description of the steps in each embodiment in the specification is only for convenience, and the implementation of the present application is not limited by the order of the steps.

[0053] In the specification, "connection" includes direct connection and indirect connection, such as connection through some active devices, passive devices or electrically conductive media; it can also include the connection of other active devices or passive devices known to those skilled in the art on the basis of achieving the same or similar functional purposes, such as the connection of circuits or components such as switches, follower circuits, etc.

[0054] The present application discloses a reference current temperature compensation circuit, Figure 2 、 Figure 3 The circuit schematic diagram of the reference current temperature compensation circuit in an embodiment of the present application is shown in Figure 1. Figure 2 、 Figure 3 The reference current temperature compensation circuit includes a PTAT current generation circuit 1, a temperature compensation module 2 and a CTAT current output module 3. The PTAT current generation circuit 1 is used to generate a PTAT current; the temperature compensation module 2 is used to generate a temperature coefficient current; and the CTAT current output module 3 is used to mirror output to a set output end through a current mirror.

[0055] In an embodiment of the present application, the temperature compensation module 2 includes a positive temperature coefficient current generation circuit and a negative temperature coefficient current generation circuit. The positive temperature coefficient current generation circuit is used to generate a positive temperature coefficient current; and the negative temperature coefficient current generation circuit is used to generate a negative temperature coefficient current.

[0056] The circuit schematic diagram of the reference current temperature compensation circuit in an embodiment of the present application is shown in Figure 1. Figure 2 、 Figure 3The temperature compensation module 2 comprises a first triode Q1, a second triode Q2, a first N-type MOS tube NM1, a second N-type MOS tube NM2, and a first resistor R1. The gate of the first N-type MOS tube NM1 is connected to the PTAT current generation circuit, the collector of the first triode Q1, and the gate of the second N-type MOS tube NM2, respectively. The drain of the first N-type MOS tube NM1 is connected to the CTAT current output module and the drain of the second N-type MOS tube NM2. The source of the first N-type MOS tube NM1 is connected to the base of the first triode Q1, the base of the second triode Q2, and the first end of the first resistor R1, respectively. The source of the second N-type MOS tube NM2 is connected to the collector of the second triode Q2. The emitter of the first triode Q1, the second end of the first resistor R1, and the emitter of the second triode Q2 are grounded.

[0057] In an embodiment of the present application, the CTAT current output module 3 comprises a low-voltage cascode current mirror for copying a reference current and outputting. In an embodiment, as shown in Figure 2 , Figure 3 The low-voltage cascode current mirror comprises a fifth P-type MOS tube PM5, a sixth P-type MOS tube PM6, a seventh P-type MOS tube PM7, an eighth P-type MOS tube PM8, and a second resistor R2. The power supply voltage VCC is connected to the source of the fifth P-type MOS tube PM5 and the source of the sixth P-type MOS tube PM6, respectively. The drain of the fifth P-type MOS tube PM5 is connected to the source of the seventh P-type MOS tube PM7, and the drain of the sixth P-type MOS tube PM6 is connected to the source of the eighth P-type MOS tube PM8. The gate of the fifth P-type MOS tube PM5 is connected to the gate of the sixth P-type MOS tube PM6, the drain of the seventh P-type MOS tube PM7, and the first end of the second resistor R2. The gate of the seventh P-type MOS tube PM7 is connected to the gate of the eighth P-type MOS tube PM8, the second end of the second resistor R2, and the temperature compensation module. The drain of the eighth P-type MOS tube PM8 is connected to the output port.

[0058] Please refer to Figure 2 In an embodiment of the present application, the PTAT current generation circuit 1 comprises a PTAT current source I1, a first P-type MOS tube PM1, and a second P-type MOS tube PM2. The PTAT current source I1 is used to generate a PTAT current. The positive electrode of the PTAT current source I1 is connected to the drain of the first P-type MOS tube PM1, the gate of the first P-type MOS tube PM1, and the gate of the second P-type MOS tube PM2, respectively. The negative electrode of the PTAT current source I1 is grounded. The power supply voltage VCC is connected to the source of the first P-type MOS tube PM1 and the source of the second P-type MOS tube PM2, respectively. The drain of the second P-type MOS tube PM2 is connected to the temperature compensation module.

[0059] Referring to Figure 3 In an embodiment of the present application, the PTAT current generating circuit is implemented by a bandgap reference circuit, which is used to generate a reference voltage and a PTAT current. The bandgap reference circuit comprises a first operational amplifier A1, a first P-type MOS PM1, a second P-type MOS PM2, a third P-type MOS PM3, a fourth P-type MOS PM4, a third transistor Q3, a fourth transistor Q4, a third resistor R3 and a fourth resistor R4. A power supply voltage VCC is connected to the source of the first P-type MOS PM1, the source of the second P-type MOS PM2, the source of the third P-type MOS PM3 and the source of the fourth P-type MOS PM4, respectively. The gate of the first P-type MOS PM1 is connected to the gate of the second P-type MOS PM2, the gate of the third P-type MOS PM3, the gate of the fourth P-type MOS PM4 and the output of the first operational amplifier A1, respectively. The drain of the first P-type MOS PM1 is connected to the inverting input of the first operational amplifier A1, the base of the third transistor Q3 and the collector of the third transistor Q3, respectively. The drain of the second P-type MOS PM2 is connected to the non-inverting input of the first operational amplifier A1 and the first end of the third resistor R3, respectively; the second end of the third resistor R3 is connected to the base of the fourth transistor Q4 and the collector of the fourth transistor Q4, respectively. The drain of the third P-type MOS PM3 is connected to the first end of the fourth resistor R4, and the drain of the fourth P-type MOS PM4 is connected to a temperature compensation module. The emitter of the third transistor Q3 is grounded, the emitter of the fourth transistor Q4 is grounded, and the second end of the fourth resistor R4 is grounded.

[0060] In addition, the reference current temperature compensation circuit can further comprise a reference voltage generating circuit, which is used to generate a reference voltage.

[0061] The above describes the composition of the reference current temperature compensation circuit in the embodiment of the present application. The working principle of the reference current temperature compensation circuit in the embodiment of the present application is further described below.

[0062] Figure 2 FIG. 1 is a circuit schematic diagram of the reference current temperature compensation circuit in an embodiment of the present application; referring to Figure 2 In an embodiment of the present application, the PTAT current source I1 can be provided by a bandgap reference circuit, which aims to generate a current with a positive temperature coefficient for generating a current with a zero temperature coefficient. The current mirror structure composed of the first P-type MOS PM1 and the second P-type MOS PM2 aims to mirror and transmit the current provided by the PTAT current source I1 to the subsequent structure.

[0063] The current mirror structure composed of the first transistor Q1 and the second transistor Q2, wherein: the collector of the first transistor Q1 and the drain of the second P-type MOS tube are connected together, and the joint point is marked as point A; the base of the first transistor Q1 and the base of the second transistor Q2 are connected together, and the joint point is marked as point B; the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are connected together to the ground. The purpose of designing the structure is to mirror the current flowing through the first transistor Q1 to the second transistor Q2, and to provide the second transistor Q2 with the current having a positive temperature coefficient.

[0064] The gate of the first N-type MOS tube NM1 is connected at point A; the source is connected at point B; the drain and the drain of the second N-type MOS tube NM2 are connected together, and the joint point is marked as point D. The purpose of using the device is to provide the base voltage and the base current for the first transistor Q1 and the second transistor Q2, and to clamp the voltage at point A at V A = V BE(Q1) + V GS(NM1) , and to reduce the influence of the power supply voltage VCC on the voltage at point A.

[0065] The gate of the second N-type MOS tube NM2 is connected at point A; the source and the collector of the second transistor Q2 are connected together, and the joint point is marked as point C; the drain is connected with the drain of the first N-type MOS tube NM1, the gate of the seventh P-type MOS tube PM7, the gate of the eighth P-type MOS tube PM8 and one end of the second resistor R2 at point D. The purpose of using the device is to clamp the voltage at point C at V c = V A -V GS(NM2) = V BE(Q1) + V GS(NM1) -V GS(NM2) , and to reduce the influence of the power supply voltage VCC on the voltage at point C.

[0066] One end of the first resistor R1 is connected to the ground, and the other end is connected with the bases of the first transistor Q1 and the second transistor Q2 and the source of the first N-type MOS tube NM1 at point B. The purpose is to utilize the characteristic that the base-emitter voltage of the bipolar junction transistor has a negative temperature coefficient, and then to obtain a current having a negative temperature coefficient, and to provide the basis for generating the current having a zero temperature coefficient.

[0067] The low-voltage cascode current mirror structure with self-bias function is composed of the fifth P-type MOS transistor PM5, the sixth P-type MOS transistor PM6, the seventh P-type MOS transistor PM7, the eighth P-type MOS transistor PM8 and the second resistor R2, wherein the gate of the fifth P-type MOS transistor PM5 and the gate of the sixth P-type MOS transistor PM6 are connected together with the drain of the seventh P-type MOS transistor PM7 and one end of the second resistor R2; the gate of the seventh P-type MOS transistor PM7 and the gate of the eighth P-type MOS transistor PM8 are connected with the other end of the second resistor R2, the drain of the first N-type MOS transistor NM1 and the drain of the second N-type MOS transistor NM2 at the point D. The purpose is to add the current with negative temperature coefficient flowing through the first N-type MOS transistor NM1 and the current with positive temperature coefficient flowing through the second N-type MOS transistor NM2 to the current flowing through the fifth P-type MOS transistor PM5 and the seventh P-type MOS transistor PM7, and mirror the current to the branch where the sixth P-type MOS transistor PM6 and the eighth P-type MOS transistor PM8 are located through the above low-voltage cascode current mirror structure.

[0068] When the PTAT current I1 generated by the bandgap reference circuit is adopted in the above design scheme, the current flowing through the second P-type MOS transistor PM2 and the first transistor Q1 is the PTAT current I1 through the current mirror structure composed of the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2. Then, since the bases and the emitters of the matched first transistor Q1 and the second transistor Q2 are connected together, i.e., V BE(Q1) = V BE(Q2) is established, and since the first N-type MOS transistor NM1 and the second N-type MOS transistor NM2 exist, the collector voltage of the first transistor Q1 is clamped to V A = V BE(Q1) + V GS(NM1) , and the collector voltage of the second transistor Q2 is clamped to V C = V BE(Q1) + V GS(NM1) -V GS(NM2) . Therefore, the PTAT current I1 can be accurately mirrored to the collector current of the second transistor Q2, i.e., the current flowing through the second N-type MOS transistor NM2 is basically consistent with the PTAT current I1 generated by the bandgap reference current.

[0069] Meanwhile, since the base-emitter voltage of the triode has a characteristic inversely proportional to temperature, and the resistor R1 is connected between the base of the first triode Q1 and the second triode Q2 and the ground, the current flowing through the first N-type MOS NM1 and the absolute value of the negative temperature coefficient of the current can be effectively adjusted by selecting a resistor with a proper positive or negative temperature coefficient and determining the number of resistors with a certain weight. When the sum of the negative temperature coefficient of the current flowing through the first N-type MOS NM1 and the positive temperature coefficient of the current flowing through the second N-type MOS NM2 is zero, a current with zero temperature coefficient is generated in the branch where the fifth P-type MOS PM5 and the sixth P-type MOS PM6 are located: I REF = I (NM1) + I (NM2) , wherein

[0070] Figure 3 is a circuit schematic diagram of the reference current temperature compensation circuit in an embodiment of the present application; please refer to Figure 3 In an embodiment of the present application, the fourth triode Q4 is composed of N NPN bipolar junction transistors matched with the third triode Q3 in parallel, and the third triode Q3 and the fourth triode Q4 are both diode-connected with the base and the collector connected together, so as to build the third triode Q3 and the fourth triode Q4 working at different current densities, and prepare for the following to obtain the difference V1 of the base-emitter voltage proportional to the absolute temperature.

[0071] One end of the third resistor R3 is connected with the base and the collector of the fourth triode Q4, and the other end is connected with the second P-type MOS PM2 and the input of the operational amplifier A1, so as to bear the voltage V1 with a positive temperature coefficient generated by the third triode Q3 and the fourth triode Q4.

[0072] One end of the input of the operational amplifier A1 is connected with the base and the collector of the third triode Q3 and the drain of the first P-type MOS PM1, and the point is recorded as point X; the other end is connected with the third resistor R3 and the drain of the second P-type MOS PM2, and the point is recorded as point Y; the output is connected with the gate of the first P-type MOS PM1 and the gate of the second P-type MOS PM2. The purpose is to keep the voltage values of points X and Y equal, and to provide appropriate gate voltages for the first P-type MOS PM1, the second P-type MOS PM2 and related devices.

[0073] The current mirror structure composed of the first P-type MOS PM1, the second P-type MOS PM2, the third P-type MOS PM3 and the fourth P-type MOS PM4 is to transmit the PTAT current flowing through the second P-type MOS PM2 to the branch where the related P-type MOS is located.

[0074] The fourth resistance R4 is connected between the ground and the drain of the third P-type MOS PM3, which is to convert the PTAT current flowing through the third P-type MOS PM3 into the reference voltage with zero temperature coefficient.

[0075] The current mirror structure is composed of the first transistor Q1 and the second transistor Q2, in which: the collector of the first transistor Q1 is connected with the drain of the fourth P-type MOS PM4 together, and the point is marked as A; the base of the first transistor Q1 and the base of the second transistor Q2 are connected together, and the point is marked as B; the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are connected together to the ground. The purpose of designing the structure is to mirror the current flowing through the first transistor Q1 to the second transistor Q2, to provide the second transistor Q2 with the current with positive temperature coefficient.

[0076] The gate of the first N-type MOS NM1 is connected at A, the source is connected at B, and the drain is connected with the drain of the second N-type MOS NM2 together, and the point is marked as D. The purpose of using the device is to provide the base voltage and the base current for the first transistor Q1 and the second transistor Q2, and to clamp the voltage at A to V A = V BE(Q3) + V GS(NM1) , to reduce the influence of the power supply voltage VCC on the voltage at A.

[0077] The gate of the second N-type MOS NM2 is connected at A, the source is connected with the collector of the second transistor Q2 together, and the point is marked as C; the drain of the second N-type MOS NM2 is connected with the drain of the first N-type MOS NM1, the gate of the seventh P-type MOS PM7, the gate of the eighth P-type MOS PM8 and one end of the second resistance R2 at D. The purpose of using the device is to clamp the voltage at C to V C = V A -V GS(NM2) = V BE(Q3) + V GS(NM1) -V GS(NM2) , to reduce the influence of the power supply voltage VCC on the voltage at C.

[0078] One end of the first resistor R1 is connected to ground, and the other end is connected to the base of the first transistor Q1 and the base of the second transistor Q2 at point B. The purpose is to utilize the negative temperature coefficient of the base-emitter voltage of the transistors to obtain a current with a negative temperature coefficient, thus providing a basis for generating a current with a zero temperature coefficient.

[0079] A low-voltage cascode current mirror structure with self-biasing function is formed by five P-type MOSFETs PM5, PM6, PM7, and PM8, and a second resistor R2. The gates of PM5, PM6, and PM7, and one end of the second resistor R2 are connected together. The gates of PM7 and PM8, the other end of the second resistor R2, the drain of N-type MOSFET NM1, and the drain of NM2 are connected at point D. The purpose is to add the current flowing through NM1 (which has a negative temperature characteristic) and NM2 (which has a positive temperature characteristic) to form the current flowing through PM5 and PM7, and then mirror this current to the branch containing PM6 and PM8 through the low-voltage cascode current mirror structure.

[0080] like Figure 3 As shown, in one embodiment of the present invention, it is assumed that the circuit has no startup-related problems, that is, the circuit can work normally, and none of the devices in the figure have zero current flowing through them. A current I2 = ΔV with a positive temperature coefficient is generated by a conventional bandgap reference circuit flowing through the second P-type MOSFET PM2. BE / R1 and the current mirror structure composed of the second P-type MOSFET PM2 and the third P-type MOSFET PM3 mirror the current I2 to the reference voltage V generated by the branch where the third P-type MOSFET PM3 is located and the fourth resistor R4. REF =ΔV BE ×R2 / R1, which will not be elaborated further.

[0081] Without affecting the reference voltage V REF Simultaneously, the current mirror formed by the second P-type MOSFET PM2 and the fourth P-type MOSFET PM4 mirrors the current I2 to the branch containing the fourth P-type MOSFET PM4. Therefore, the current flowing through the fourth P-type MOSFET PM4 and the first transistor Q1 is the current I2 with a positive temperature coefficient. Then, because the bases of the first transistor Q1 and the second transistor Q2 are connected together, and their emitters are also connected together, V... BE(Q3) =V BE(Q4)established, this part constitutes a current mirror structure, and the function is to mirror the current flowing through the first transistor Ql to the branch where the second transistor Q2 is located. Because of the existence of the first N-type MOS NMl and the second N-type MOS NM2, the collector voltage of the first transistor Ql is clamped to V A = V BE(Q3) + V GS(NM1) ; and the collector voltage of the second transistor Q2 is clamped to V C = V A - V GS(NM2) = V BE(Q3) + V Gs(NM1) - V GS(NM2) ; this can effectively suppress the base width modulation effect caused by the change of the collector voltage of the first transistor Ql and the second transistor Q2 due to the change of the power supply voltage, which leads to a large error in the mirror accuracy of the current mirror structure. Although the collector voltage V A of the first transistor Ql is not completely equal to the collector voltage V C of the second transistor Q2, the difference of the collector voltage has little effect on the current mirror accuracy, so it can be considered that the current flowing through the second transistor Q2 is basically consistent with the current I2, that is, the current I NM2 flowing through the second N-type MOS NM2 is basically consistent with the current I2.

[0082] Secondly, because the base-emitter voltage of the NPN bipolar junction transistor has an inverse temperature characteristic, and one end of the first resistor Rl is connected to the point B where the base of the first transistor Ql and the base of the second transistor Q2 are connected, and the other end is connected to the ground. That is, the voltage V B = V BE(Q3) = V BE(Q4) across the first resistor Rl, so the current flowing through the first resistor Rl is I3 = V B / R3, so the current flowing through the first resistor Rl has a negative temperature coefficient characteristic, and the current I NM1 flowing through the first N-type MOS is I B(Q3) + I B(Q4) + I3. In the circuit, by connecting the drains of the first N-type MOS NMl and the second N-type MOS NM2 together at point D, the current I NM1 with a negative temperature coefficient and the current I NM2The current flowing through the fifth P-type MOS transistor PM5 and the seventh P-type MOS transistor PM7 is the sum of the above two currents, and the current flowing through the fifth P-type MOS transistor PM5 and the seventh P-type MOS transistor PM7 is mirrored to the sixth P-type MOS transistor PM6 and the eighth P-type MOS transistor PM8 through the current mirror structure composed of the fifth P-type MOS transistor PM5, the sixth P-type MOS transistor PM6, the seventh P-type MOS transistor PM7 and the eighth P-type MOS transistor PM8, so the current obtained at the output end should be: I OUT = I NM1 + I NM2 = 2I B + V B / R3+ ΔV BE / R1, by adjusting the parameters of the related devices, so that there is that is, a zero-temperature-coefficient current I OUT is generated.

[0083] In summary, the reference current temperature compensation circuit and the reference current temperature compensation control method provided by the present application can complete the temperature compensation of the current to obtain a zero-temperature-coefficient reference current using a small number of devices without affecting the reference voltage in the bandgap reference circuit, or directly generate a zero-temperature-coefficient reference current using a PTAT current, thereby saving the chip area occupied and reducing the production cost to a certain extent. In addition, the current also has high stability and is less affected by the power supply voltage, and can well adapt to market needs.

[0084] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0085] The description and application of the present application are illustrative, and are not intended to limit the scope of the present application to the above-described embodiments. The effects or advantages involved in the embodiments can be disturbed by various factors and can not be embodied in the embodiments. The description of the effects or advantages is not used to limit the embodiments. Variations and changes of the disclosed embodiments are possible, and various components of the embodiments are known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present application can be realized in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential characteristics of the present application. Other variations and changes of the disclosed embodiments can be made without departing from the scope and spirit of the present application.

Claims

1. A reference current temperature compensation circuit, characterized in that, The reference current temperature compensation circuit includes: PTAT current generation circuit, used to generate PTAT current; A temperature compensation module, connected to the PTAT current generation circuit, is used to generate a temperature coefficient current based on the PTAT current generated by the PTAT current generation circuit; and The CTAT current output module is connected to the temperature compensation module and is used to output the temperature coefficient current generated by the temperature compensation module to the set output terminal through a current mirror. The temperature compensation module includes: A positive temperature coefficient current generating circuit is used to generate a positive temperature coefficient current; and Negative temperature coefficient current generating circuit, used to generate negative temperature coefficient current; The temperature compensation module includes: a first transistor Q1, a second transistor Q2, a first N-type MOSFET NM1, a second N-type MOSFET NM2, and a first resistor R1; The gate of the first N-type MOS transistor NM1 is connected to the PTAT current generation circuit, the collector of the first transistor Q1, and the gate of the second N-type MOS transistor NM2, respectively. The drain of the first N-type MOSFET NM1 is connected to the drain of the CTAT current output module and the drain of the second N-type MOSFET NM2, respectively. The source of the first N-type MOSFET NM1 is connected to the base of the first transistor Q1, the base of the second transistor Q2, and the first terminal of the first resistor R1, respectively. The source of the second N-type MOSFET NM2 is connected to the collector of the second transistor Q2; the emitter of the first transistor Q1, the second terminal of the first resistor R1, and the emitter of the second transistor Q2 are respectively grounded; The CTAT current output module includes a low-voltage common-source cascode current mirror, which is used to replicate and output a reference current. The low-voltage common-source cascode current mirror includes a fifth P-type MOSFET PM5, a sixth P-type MOSFET PM6, a seventh P-type MOSFET PM7, an eighth P-type MOSFET PM8, and a second resistor R2; The power supply voltage VCC is connected to the source of the fifth P-type MOSFET PM5 and the source of the sixth P-type MOSFET PM6, respectively. The drain of the fifth P-type MOSFET PM5 is connected to the source of the seventh P-type MOSFET PM7, and the drain of the sixth P-type MOSFET PM6 is connected to the source of the eighth P-type MOSFET PM8. The gate of the fifth P-type MOS transistor PM5 is connected to the gate of the sixth P-type MOS transistor PM6, the drain of the seventh P-type MOS transistor PM7, and the first end of the second resistor R2. The gate of the seventh P-type MOSFET PM7 is connected to the gate of the eighth P-type MOSFET PM8, the second terminal of the second resistor R2, and the temperature compensation module; the drain of the eighth P-type MOSFET PM8 is connected to the output port.

2. The reference current temperature compensation circuit according to claim 1, characterized in that: The PTAT current generation circuit includes a PTAT current source I1, a first P-type MOSFET PM1, and a second P-type MOSFET PM2. The PTAT current source I1 is used to generate PTAT current. The positive terminal of the PTAT current source I1 is connected to the drain of the first P-type MOS transistor PM1, the gate of the first P-type MOS transistor PM1, and the gate of the second P-type MOS transistor PM2, respectively, and the negative terminal of the PTAT current source I1 is grounded. The power supply voltage VCC is connected to the source of the first P-type MOSFET PM1 and the source of the second P-type MOSFET PM2, respectively; the drain of the second P-type MOSFET PM2 is connected to the temperature compensation module.

3. The reference current temperature compensation circuit according to claim 1, characterized in that: The PTAT current generation circuit is implemented through a bandgap reference circuit, which is used to generate a reference voltage and a PTAT current. The bandgap reference circuit includes a first operational amplifier A1, a first P-type MOSFET PM1, a second P-type MOSFET PM2, a third P-type MOSFET PM3, a fourth P-type MOSFET PM4, a third transistor Q3, a fourth transistor Q4, a third resistor R3, and a fourth resistor R4. The power supply voltage VCC is connected to the source of the first P-type MOSFET PM1, the source of the second P-type MOSFET PM2, the source of the third P-type MOSFET PM3, and the source of the fourth P-type MOSFET PM4, respectively. The gate of the first P-type MOS transistor PM1 is connected to the gate of the second P-type MOS transistor PM2, the gate of the third P-type MOS transistor PM3, the gate of the fourth P-type MOS transistor PM4, and the output terminal of the first operational amplifier A1, respectively. The drain of the first P-type MOS transistor PM1 is connected to the inverting input terminal of the first operational amplifier A1, the base of the third transistor Q3, and the collector of the third transistor Q3, respectively. The drain of the second P-type MOS transistor PM2 is connected to the non-inverting input terminal of the first operational amplifier A1 and the first terminal of the third resistor R3, respectively; the second terminal of the third resistor R3 is connected to the base and collector of the fourth transistor Q4, respectively. The drain of the third P-type MOS transistor PM3 is connected to the first terminal of the fourth resistor R4, and the drain of the fourth P-type MOS transistor PM4 is connected to the temperature compensation module. The emitter of the third transistor Q3 is grounded, the emitter of the fourth transistor Q4 is grounded, and the second terminal of the fourth resistor R4 is grounded.

4. The reference current temperature compensation circuit according to claim 1, characterized in that: The reference current temperature compensation circuit further includes a reference voltage generation circuit, which generates a reference voltage.

5. A reference current temperature compensation control method for the reference current temperature compensation circuit according to any one of claims 1 to 4, characterized in that, The reference current temperature compensation control method includes: Step S1: The PTAT current generation circuit generates PTAT current; Step S2: The temperature compensation module generates a temperature coefficient current based on the PTAT current generated by the PTAT current generation circuit. Step S3: The CTAT current output module outputs the temperature coefficient current generated by the temperature compensation module to the set output terminal through a current mirror.

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