Multi-die package

Abstract

A multi-chip package includes a host die, a memory die, a first set of pins, and a second set of pins. The host die includes a memory controller, a first set of contacts, a second set of contacts, and a third set of contacts. The memory die is coupled to the first set of contacts and the second set of contacts of the host die. The first set of pins is coupled to the third set of contacts of the host die. The second set of pins is coupled to the second set of contacts of the host die. The memory controller accesses the memory die through the first set of contacts and the second set of contacts, and accesses a memory chip outside the multi-chip package through the second set of contacts and the third set of contacts.

Description

TECHNICAL FIELD

[0001] The present application relates to a multi-die package architecture including a dynamic random access memory (DRAM). BACKGROUND

[0002] Current semiconductor packaging technology can integrate multiple dies in a single package to reduce the number of traces and area on a printed circuit board (PCB). For example, a conventional DRAM and a processor are in two separate chips / packages, so multiple traces and contacts on a PCB are needed to connect the two chips. If the processor and the DRAM are integrated in a single package so that the processor can access the DRAM through the traces and contacts inside the package, the number of traces and contacts on the PCB can be reduced.

[0003] However, if the processor and the DRAM are disposed in a single package, the capacity of the DRAM can only be maintained at the originally designed value because the dies inside the package cannot be increased, and the capacity of the DRAM lacks scalability. In other words, if a designer needs to design a processor and a DRAM for multiple different products, and the required DRAM capacities of the different products are not the same, the designer needs to design chips for multiple different DRAM capacities, which increases the design and manufacturing costs. SUMMARY

[0004] Therefore, one of the objectives of the present application is to provide a multi-die package architecture that allows the capacity of a DRAM to be expanded to solve the problems in the prior art.

[0005] In one embodiment of the present application, a multi-die package is disclosed, which includes a main die, a memory die, a first set of pins, and a second set of pins. The main die includes a memory controller, a first set of contacts, a second set of contacts, and a third set of contacts. The memory die is coupled to the first set of contacts and the second set of contacts of the main die. The first set of pins is coupled to the third set of contacts of the main die, and the second set of pins is coupled to the second set of contacts of the main die. In addition, the memory controller accesses the memory die through the first set of contacts and the second set of contacts, and accesses a memory chip outside the multi-die package through the second set of contacts and the third set of contacts.

[0006] The features, actual operations, and effects of the present application will be described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1FIG. 1 is a schematic diagram of a multi-chip package according to one embodiment of the present application.

[0008] Figure 2 FIG. 2 is a schematic diagram of a multi-chip package and memory chips according to one embodiment of the present application.

[0009] Symbol Explanation

[0010] 100: multi-chip package

[0011] 102: first set of pins of the multi-chip package

[0012] 104: second set of pins of the multi-chip package

[0013] 110: host chip

[0014] 112: core circuit

[0015] 114: memory controller

[0016] 116_1: first set of contacts of the host chip

[0017] 116_2: second set of contacts of the host chip

[0018] 116_3: third set of contacts of the host chip

[0019] 120: memory chip

[0020] 122: control circuit

[0021] 124: memory array

[0022] 126_1: first set of contacts of the memory chip

[0023] 126_2: second set of contacts of the memory chip

[0024] 200: memory chip

[0025] 202: first set of pins of the memory chip

[0026] 204: second set of pins of the memory chip

[0027] 210: control circuit

[0028] 220: memory array DETAILED DESCRIPTION

[0029] Embodiments of the present application are described below in more detail. It should be appreciated, however, that the present application provides many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments described below are merely illustrative of specific ways to make and use the application and do not delimit the scope of the application.

[0030] Figure 1This is a schematic diagram of a multi-die package 100 according to an embodiment of the present invention. Figure 1 As shown, the multi-die package 100 includes a main die 110, a memory die 120, and multiple sets of pins (only the first set of pins 102 and the second set of pins 104 are shown in this embodiment), wherein both the first set of pins 102 and the second set of pins 104 contain multiple pins. In this embodiment, the main die 110 may be a processor, such as a central processing unit (CPU), and the main die 110 includes a core circuit 112, a memory controller 114, and multiple sets of contacts (only the first set of contacts 116_1, the second set of contacts 116_2, and the third set of contacts 116_3 are shown in this embodiment), wherein each of the first set of contacts 116_1, the second set of contacts 116_2, and the third set of contacts 116_3 contains multiple contacts; in addition, the memory die 120 includes a control circuit 122, a memory array 124, and multiple sets of contacts (only the first set of contacts 126_1 and the second set of contacts 126_2 are shown in this embodiment). Furthermore, in this embodiment, the memory die 120 is a DRAM die, and the memory controller 114 in the main die 110 is a DRAM controller, but the present invention is not limited thereto.

[0031] In this embodiment, the first set of contacts 116_1 of the master die 110 are data contacts for transferring data to and / or receiving data from the memory die 120 through the first set of contacts 126_1 of the memory die 120, i.e. the first set of contacts 116_1 of the master die 110 and the first set of contacts 126_1 of the memory die 120 are connected through a plurality of connection lines, wherein the plurality of connection lines are used for sending at least a plurality of bi-directional data signals (DQ), one or more bi-directional data strobe signals (DQS), etc. The second set of contacts 116_2 of the master die 110 are control signal contacts for transferring frequency signals, control signals and address signals to the second set of contacts 126_2 of the memory die 120 for use by the memory die 120, and also transferring control signals and address signals to components outside the multi-die package 100 through the second set of pins 104, wherein the frequency signals, control signals and address signals include read / write commands, write enable, row address strobe, column address strobe, etc. The third set of contacts 116_3 of the master die 110 are data contacts for transferring data to and / or receiving data from components outside the multi-die package 100 through the first set of pins 102, i.e. the first set of contacts 116_1 of the master die 110 and the components outside the multi-die package 100 are connected through a plurality of connection lines, wherein the plurality of connection lines are used for sending at least a plurality of bi-directional data signals (DQ), one or more bi-directional data strobe signals (DQS), etc. In this embodiment, the path of the memory controller 110 to access components outside the multi-die package 100 through the third set of contacts 116_3 and the first set of pins 102 does not go through the memory die 120.

[0032] In the general operation of the multi-chip package 100, the memory controller 114 can receive a request from the core circuit 112 and send data signals, data strobe signals, a plurality of command signals, and a portion of the frequency signals through the first set of contacts 116_1 and the second set of contacts 116_2 to access the memory die 120. Specifically, the memory controller 114 can include associated circuitry, such as address decoders, processing circuitry, write / read buffers, control logic, and arbiters, to generate the data signals, data strobe signals, a plurality of command signals, and the frequency signals to the memory die 120. In addition, in the memory die 120, the control circuit 122 can include read / write controllers, row decoders, and column decoders, and the control circuit 124 receives the data signals, data strobe signals, a plurality of command signals, and the frequency signals from the memory controller through the first set of contacts 126_1 and the second set of contacts 126_2 to access the memory array 124.

[0033] In the above embodiment, since the capacity of the memory die 120 in the multi-chip package 100 is fixed, when the multi-chip package 100 needs to be applied to electronic products with higher memory capacity and performance requirements, the capacity of the memory die 120 is insufficient to meet the requirements. Therefore, the multi-chip package 100 of the present embodiment can be externally connected to another memory chip to improve the memory capacity and performance. Specifically, referring to Figure 2 which includes the multi-chip package 100 and the memory chip 200, wherein the memory chip 200 includes a control circuit 210, a memory array 220, and a plurality of pins (only the first set of pins 202 and the second set of pins 204 are drawn in the present embodiment). In addition, in the present embodiment, the memory chip 200 is a DRAM chip, the multi-chip package 100 and the memory chip 200 are disposed on a printed circuit board, and the first set of pins 102 and the second set of pins 104 of the multi-chip package 100 are connected to the first set of pins 202 and the second set of pins 204 of the memory chip 200 through the connection lines on the printed circuit board.

[0034] In Figure 2In operation of the illustrated multi-die package 100 and memory chip 200, the memory controller 114 can receive requests from the core circuit 112 and send a plurality of command signals to the memory die 120 and the memory chip 200 through the second set of contacts 116_2 to access at least one of the memory die 120 and the memory chip 200. Specifically, when an application executed by the core circuit 112 only requires lower memory access speed and performance (e.g., lower bandwidth), the memory controller 114 can receive requests from the core circuit 112 and send data signals, data strobe signals, a portion of the plurality of command signals, and frequency signals through the first set of contacts 116_1 and the second set of contacts 116_2 to access the memory die 120 to read data from or write data to the memory array 124; at this time, since the memory controller 114 does not need to access the memory chip 200, the control circuit 210 in the memory chip 200 can ignore the plurality of command signals received from the second set of pins 204, and / or the memory chip 200 can enter a power saving mode. In another embodiment, when an application executed by the core circuit 112 only requires lower memory access speed and performance, the memory controller 114 can receive requests from the core circuit 112 and send data signals, data strobe signals, a portion of the plurality of command signals, and frequency signals through the second set of contacts 116_2 and the third set of contacts 116_3 to access the memory chip 200 to read data from or write data to the memory array 220; at this time, since the memory controller 114 does not need to access the memory die 120, the control circuit 122 in the memory die 120 can ignore the plurality of command signals received from the second set of contacts 126, and / or the memory die 120 can enter a power saving mode.

[0035] When the application executed by the core circuit 112 needs to use higher memory access speed and performance (e.g., higher bandwidth), the memory controller 114 can receive the request from the core circuit 112 and send a plurality of command signals through the second set of contacts 116_2 to simultaneously access the memory die 120 and the memory chip 200. Specifically, the plurality of command signals sent by the memory controller 114 through the second set of contacts 116_2 can include a write command and the addresses of the memory array 124 and the memory array 220, and at this time the memory controller 114 transmits a first set of data through the first set of contacts 116_1 to the memory die 120 to write into the corresponding addresses of the memory array 124, and simultaneously the memory controller 114 transmits a second set of data through the third set of contacts 116_3 to the memory chip 200 to write into the corresponding addresses of the memory array 220. In addition, the plurality of command signals sent by the memory controller 114 through the second set of contacts 116_2 can include a read command and the addresses of the memory array 124 and the memory array 220, and at this time the control circuit 122 in the memory die 120 reads a first set of data from the memory array 124 according to the received addresses and transmits the first set of data through the first set of contacts 126_1 to the memory controller 114; simultaneously, the control circuit 210 in the memory chip 200 reads a second set of data from the memory array 220 according to the received addresses and transmits the second set of data through the first set of pins 202 to the memory controller 114.

[0036] In an embodiment, the bandwidth of the first set of contacts 116_1 in the master die 110 used to transmit or receive the first set of data can be the same as the bandwidth of the third set of contacts 116_3 used to transmit or receive the second set of data, for example, the bandwidth of the first set of data and the second set of data can be 16 bits; and the multi-die package 100 can decide to use the 16-bit bandwidth or the 32-bit bandwidth according to whether it is linked to the memory chip 200 or whether it needs to simultaneously access the memory die 120 and the memory array 220. In another example, the bandwidth of the first set of data and the second set of data can be 8 bits, and the multi-die package 100 can decide to use the 8-bit bandwidth or the 16-bit bandwidth according to whether it is linked to the memory chip 200 or whether it needs to simultaneously access the memory die 120 and the memory array 220.

[0037] Briefly summarized, in the multi-die package 100 of the present application, by the design of the relevant contacts / pins, the effect of expanding the memory capacity and speed can be easily achieved by externally connecting the memory chip 200, and the multi-die package 100 can also be applied to various electronic products with different memory bandwidth requirements to reduce the design cost.

[0038] The above merely describes preferred embodiments of the present application, and any equivalent changes and modifications made according to the above disclosure should fall within the protection scope of the present application.

Claims

1. A multi-die package, characterized in that, The multi-chip package comprises: a main die comprising a memory controller, a first set of contacts, a second set of contacts, and a third set of contacts, wherein the first set of contacts, the second set of contacts, and the third set of contacts each comprise a plurality of contacts; a memory die coupled to the first set of contacts and the second set of contacts of the main die; a first set of pins coupled to the third set of contacts of the main die; and a second set of pins coupled to the second set of contacts of the main die; wherein the memory controller accesses the memory die through the first set of contacts and the second set of contacts, and accesses a memory chip outside the multi-chip package through the second set of contacts and the third set of contacts. The memory controller transmits command signals and address signals to the memory die and the memory chip through the second set of contacts, and the memory controller writes data to or reads data from the memory die through the first set of contacts, or the memory controller writes data to or reads data from the memory chip through the third set of contacts.

2. The multi-die package of claim 1, wherein, The memory controller determines whether to access one of the memory die and the memory chip, or to access both the memory die and the memory chip, according to a bandwidth required by an application program executed by a core circuit in the main die.

3. The multiple die package of claim 2, wherein the first die is a memory die and the second die is a processor die. When the memory controller needs to access both the memory die and the memory chip, the address signals transmitted by the memory controller to the memory die and the memory chip comprise an address of a first memory array in the memory die and an address of a second memory array in the memory chip, and if the command signals transmitted by the memory controller to the memory die and the memory chip comprise a write command, the memory controller transmits a first set of data to the memory die through the first set of pins to write the first set of data into the first memory array, and transmits a second set of data to the memory die through the third set of pins to write the second set of data into the second memory array.

4. The multi-die package of claim 3, wherein the first die is a processor die and the second die is a graphics die. When the memory controller needs to access both the memory die and the memory chip, the address signals transmitted by the memory controller to the memory die and the memory chip comprise an address of a first memory array in the memory die and an address of a second memory array in the memory chip, and if the command signals transmitted by the memory controller to the memory die and the memory chip comprise a read command, the memory controller receives a first set of data from the memory die through the first set of pins and receives a second set of data from the memory chip through the third set of pins.

5. The multiple die package of claim 3, wherein the first die is a memory die and the second die is a processor die. The bandwidth of data transmitted / received by the first set of contacts is the same as the bandwidth of data transmitted / received by the third set of contacts.

6. The multiple die package of claim 2, wherein the first die is a memory die and the second die is a processor die. The bandwidth of data transmitted / received by the first set of contacts and the bandwidth of data transmitted / received by the third set of contacts are both 16 bits or 8 bits.

7. The multiple die package of claim 6, wherein the first die is a memory die and the second die is a processor die. ​ 8. The multiple die package of claim 2, wherein the first die is a memory die and the second die is a processor die. The memory controller writes data to or reads data from the memory chip through the third set of contacts and the first set of pins, and a path for the memory controller to access the memory chip through the third set of contacts and the first set of pins does not pass through the memory die.

9. The multiple die package of claim 2, wherein the first die is a memory die and the second die is a processor die. The memory controller transmits the command signal and the address signal to the memory die through the second set of contacts, and transmits the command signal and the address signal to the memory chip through the second set of contacts and the second set of pins.

10. The multiple die package of claim 1, wherein the first die is a memory die and the second die is a processor die. The memory die is a Dynamic Random Access Memory (DRAM) die, the memory chip is a DRAM chip, and the memory controller is a DRAM controller.

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