Semiconductor structure and method for manufacturing the same

Abstract

The disclosed embodiments relate to the field of semiconductors and provide a semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate, the substrate comprising a substrate and a first dielectric layer covering the substrate, the substrate comprising a source region, a drain region, and a channel region, the source region and the drain region being located on opposite sides of the channel region, the first dielectric layer having a hydrophilic surface; performing a surface modification treatment on the first dielectric layer overlying the source and drain regions to convert the hydrophilic surface of the first dielectric layer overlying the source and drain regions into a hydrophobic surface; and forming a second dielectric layer, the second dielectric layer covering only the surface of the first dielectric layer overlying the channel region, the dielectric constant of the second dielectric layer being greater than the dielectric constant of the first dielectric layer. This method can simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the development of Moore's Law, the feature size of semiconductors continues to shrink. In order to suppress the short channel effect and ensure that semiconductor devices have good device characteristics, the gate oxide layer is required to be thinner and thinner, which in turn causes many secondary effects. The direct tunneling effect of electrons is serious, and the gate electric field of the gate dielectric layer increases sharply. The leakage current caused by this makes the characteristics of semiconductor devices worse and worse, and even cannot work normally.

[0003] To this end, the use of high-k dielectric materials as the gate dielectric layer has been proposed to replace the traditional gate oxide layer. This allows the equivalent oxide thickness (EOT) of the gate dielectric layer to be maintained while reducing the physical thickness of the gate dielectric layer, thereby reducing the direct tunneling effect and the tunneling current. However, the physical properties of the interface between high-k dielectric materials and the substrate differ significantly. Factors such as lattice mismatch and interdiffusion at the interface result in a high interface state density, which seriously affects device characteristics and may even cause device failure. Furthermore, the preparation methods for high-k dielectric materials differ significantly from the existing gate oxide process, and the compatibility of their preparation process with conventional integrated circuit processes must be fully considered.

[0004] Therefore, the introduction of high dielectric constant materials increases the manufacturing process cost of semiconductor structures and complicates the process steps. Summary of the Invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, so as to simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a base, the base including a substrate and a first dielectric layer covering the substrate, the substrate including a source region, a drain region and a channel region, the source region and the drain region are located on opposite sides of the channel region, and the first dielectric layer has a hydrophilic surface; performing surface modification treatment on the first dielectric layer on the source region and the drain region to convert the hydrophilic surface of the first dielectric layer in the source region and the drain region into a hydrophobic surface; forming a second dielectric layer, the second dielectric layer only covering the surface of the first dielectric layer on the channel region, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.

[0007] In some embodiments, the surface modification treatment of the first dielectric layer on the source region and the drain region includes: using H + The surface of the first dielectric layer on the source region and the drain region is bombarded.

[0008] In some embodiments, H + The bombardment direction is perpendicular to the surface of the first dielectric layer on the source region and the drain region.

[0009] In some embodiments, the substrate has a groove exposing a surface of the channel region; forming the second dielectric layer includes: forming the second dielectric layer on the surface of the first dielectric layer on the bottom and sidewalls of the groove.

[0010] In some embodiments, before performing surface modification on the first dielectric layer on the source region and the drain region, the manufacturing method further includes: forming a mask layer, wherein the mask layer covers the first dielectric layer on the bottom and sidewalls of the groove and fills the groove; after performing surface modification on the first dielectric layer on the source region and the drain region, the manufacturing method further includes: removing the mask layer.

[0011] In some embodiments, forming the mask layer includes: forming an initial mask layer, the initial mask layer covering the first dielectric layer and filling the groove; removing the initial mask layer on the source region and the drain region, and retaining the initial mask layer in the groove as the mask layer.

[0012] In some embodiments, the process steps of forming a mask layer and performing surface treatment include: using a first gas to perform plasma etching on the initial mask layer to remove the initial mask layer located on the source region and the drain region; when a signal indicating that the first dielectric layer is exposed is detected, replacing the first gas with a second gas to perform surface modification treatment on the first dielectric layer on the source region and the drain region.

[0013] In some embodiments, the first gas includes CF4 and the second gas includes H2.

[0014] In some embodiments, the second dielectric layer is formed using an atomic layer deposition process.

[0015] In some embodiments, the process gas of the atomic layer deposition process includes water vapor and metal halide compound gas.

[0016] In some embodiments, the atomic layer deposition process includes multiple deposition steps, each deposition step is used to form a monomolecular layer of the second dielectric layer.

[0017] In some embodiments, process parameters of each deposition process include: a water vapor flow rate of 600-2000 sccm, a halogen compound gas flow rate of 600-2000 sccm, and a process temperature of 200° C. to 400° C.

[0018] In some embodiments, after performing a previous deposition process and before performing a next deposition process, the method further includes removing residual gas from the previous deposition process.

[0019] In some embodiments, the atomic layer deposition process includes n deposition steps, where n is greater than or equal to 1 and less than or equal to 25.

[0020] In some embodiments, the manufacturing method further includes: forming a gate, where the gate is located on a surface of the second dielectric layer.

[0021] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a semiconductor structure, which is formed using the manufacturing method of any one of the semiconductor structures in the above embodiments, including: a base, the base including a substrate and a first dielectric layer covering the substrate, the substrate including a source region, a drain region and a channel region, the source region and the drain region are located on opposite sides of the channel region, the surface of the first dielectric layer on the source region and the drain region is a hydrophobic surface, and the surface of the first dielectric layer on the channel region is a hydrophilic surface; a second dielectric layer, the second dielectric layer only covers the surface of the first dielectric layer on the channel region, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.

[0022] In some embodiments, the thickness of the second dielectric layer is less than 1.8 nm.

[0023] In some embodiments, the material of the first dielectric layer includes silicon oxide, silicon nitride, or silicon oxynitride, and the material of the second dielectric layer includes titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, or aluminum oxide.

[0024] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: providing a base including a substrate and a first dielectric layer covering the substrate, the substrate having a source region, a drain region, and a channel region for forming a transistor structure; the surface of the first dielectric layer is hydrophilic, and then the first dielectric layer on the source and drain regions is made hydrophobic through surface modification, while the first dielectric layer on the channel region remains hydrophilic. In the subsequent process of forming a second dielectric layer, the second dielectric layer grows only on the surface of the first dielectric layer on the channel region, and not on the surface of the first dielectric layer on the source and drain regions. Compared with the process steps of first depositing the second dielectric layer on the entire surface and then patterning the second dielectric layer, the etching process can be omitted, thereby improving the manufacturing efficiency of the semiconductor structure; further, the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The first dielectric layer can serve as an intermediate layer between the substrate and the second dielectric layer with a high dielectric constant, avoiding diffusion reaction between the second dielectric layer and the substrate, thereby improving the stability of the semiconductor structure. The first dielectric layer and the second dielectric layer can together constitute a gate dielectric layer, which can reduce the direct tunneling effect and tunneling current, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figures 1 to 7 A schematic structural diagram of each step corresponding to a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] As known from the background art, the introduction of high dielectric constant materials increases the manufacturing process cost of semiconductor structures and complicates the process steps.

[0028] Analysis reveals that the current gate oxide used is often silicon oxide, typically grown by direct thermal oxidation of the substrate. However, thermally grown silicon oxide layers inevitably exhibit numerous defects at the interface, significantly reducing channel mobility and significantly deviating from the theoretical electron mobility of the substrate. Furthermore, since silicon oxide has a dielectric constant of only 3.9, it increases the electric field at the gate oxide, posing significant reliability challenges. High-k dielectric materials, such as aluminum oxide, zirconium oxide, and hafnium oxide, have been extensively studied in recent years. However, these materials often have narrower band gaps than silicon oxide. This results in a smaller conduction band gap and a smaller valence band gap under gate voltage, resulting in high electron tunneling currents and significant energy losses at the gate. However, the physical properties of the interface between high-k dielectric materials and the substrate differ significantly. Lattice mismatch and interdiffusion at the interface contribute to a high density of interface states, which can severely impact device performance and even cause device failure. At the same time, the preparation method of high dielectric constant materials is very different from the original gate oxide layer process, and the compatibility of its preparation process with conventional integrated circuit processes must be fully considered.

[0029] According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure to simplify the manufacturing process of the semiconductor structure and improve the manufacturing efficiency of the semiconductor structure.

[0030] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0031] Figures 1 to 7 This is a schematic diagram of the structure of each step corresponding to the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. The method for manufacturing a semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings, as follows:

[0032] A method for manufacturing a semiconductor structure, comprising:

[0033] refer to Figure 1 , providing a substrate 200, the substrate 200 includes a substrate 100 and a first dielectric layer 101 covering the substrate 100, the substrate 100 includes a source region I, a drain region II and a channel region III, the source region I and the drain region II are located on opposite sides of the channel region III, and the first dielectric layer 101 has a hydrophilic surface 111.

[0034] The substrate 100 may be formed of an elemental semiconductor material or a compound semiconductor material. The elemental semiconductor material may be germanium or silicon, and the compound semiconductor material may be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide, or gallium arsenide silicon.

[0035] Continue to refer Figure 1 In this embodiment, the substrate 100 has a recess 121 that exposes the surface of the channel region III. The first dielectric layer 101 covers the bottom and sidewalls of the recess 121 to facilitate the subsequent formation of a buried gate structure, thereby increasing the contact area between the channel region and the word line and improving the gate control capability of the semiconductor structure. In other embodiments, the substrate may have a fin structure, with the source and drain regions located at either end of the fin structure to facilitate the subsequent formation of a fin transistor. Alternatively, the top surfaces of the source and drain regions may be flush with the top surface of the channel region to facilitate the subsequent formation of a planar gate structure.

[0036] As for the source region I and the drain region II, the source region I and the drain region II are used to form the source and drain of the transistor respectively. The source region I and the drain region II can have P-type doped ions or N-type doped ions. Specifically, the N-type ions can be phosphorus ions or arsenic ions, etc.; the P-type ions can be boron ions, indium ions or boron fluoride ions, etc.

[0037] The channel region III is used to form a gate of a transistor thereon.

[0038] The first dielectric layer 101 may be formed of a material including silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, or a material with a low dielectric constant. The first dielectric layer 101 may have a hydrophilic surface 111. A hydrophilic surface or hydrophilicity means that the contact angle of a water droplet on the surface is less than approximately 90 degrees.

[0039] In some embodiments, the first dielectric layer 101 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0040] refer to Figure 2 , the first dielectric layer 101 on the source region I and the drain region II is subjected to surface modification treatment to transform the hydrophilic surface 111 of the first dielectric layer 101 in the source region I and the drain region II into a hydrophobic surface 112. A hydrophobic surface or hydrophobicity means that the contact angle of a water droplet on the surface is equal to or greater than 90 degrees (and less than 180 degrees).

[0041] In some embodiments, the surface modification treatment of the first dielectric layer 101 on the source region I and the drain region II includes: using H + bombard the surface of the first dielectric layer 101 on the source region I and the drain region II. It can be understood that when the H on the surface of the first dielectric layer on the source region and the drain region + When the number increases, H + The greater the number, the greater the water repelling effect. The surface of the first dielectric layer on the corresponding source and drain regions is rich in H. + The repulsive force of the region to water increases, and the hydrophilic surface of the first dielectric layer on the source region and the drain region is converted into a hydrophobic surface after surface treatment.

[0042] Specifically, in some embodiments, the surface of the first dielectric layer 101 on the source region I and the drain region II is modified to generate H by ionizing H2. + To bombard the surface of the first dielectric layer 101 on the source region I and the drain region II. For example, the H2 gas flow rate can be 1000-2000 sccm, specifically, the H2 gas flow rate can be 1000 sccm, 1300 sccm, 1500 sccm, 1800 sccm or 2000 sccm, and the RF power used is 400-2000 W, specifically, the RF power can be 400 W, 800 W, 1000 W, 1500 W or 2000 W. The RF power needs to meet the appropriate size to ionize H2 to generate H + Bombard the surface of the first dielectric layer on the source and drain regions, but too high RF power will lead to increased power loss. Therefore, the setting of RF power needs to be adjusted according to the actual situation. Accordingly, the flow rate of H2 needs to meet the needs of ionization to generate enough H+ However, too much H2 can easily cause danger. Therefore, the flow rate of H2 should be appropriately adjusted while meeting the ionization requirements.

[0043] In some embodiments, H + The bombardment direction of H is perpendicular to the surface of the first dielectric layer 101 on the source region I and the drain region II. + When the bombardment direction of H is perpendicular to the surface of the first dielectric layer on the source and drain regions, + It can be uniformly injected into the surface of the first dielectric layer on the source region and the drain region, so that the hydrophilic surface of the first dielectric layer on the source region and the drain region is uniformly transformed into a hydrophobic surface. For example, in some embodiments, when the substrate surface has a fin structure, the source region and the drain region are located at both ends of the fin structure, and the first dielectric layer on the source region and the drain region has a top surface and two opposite side surfaces. + It can be uniformly injected into the surface of the first dielectric layer on the source and drain regions, and H + The bombardment direction is perpendicular to the surface of the first dielectric layer on the source and drain regions, so that the top surface and the two opposite side surfaces of the source and drain regions are uniformly injected with H + .

[0044] refer to Figure 3 In some embodiments, before performing surface modification on the first dielectric layer 101 on the source region I and the drain region II, the manufacturing method further includes: forming a mask layer 103, the mask layer 103 covering the first dielectric layer 101 on the bottom and sidewalls of the groove 121 and filling the groove 121; return to reference Figure 2 After performing surface modification on the first dielectric layer 101 over the source region I and the drain region II, the manufacturing method further includes removing the mask layer 103. It is understood that forming the mask layer to cover the first dielectric layer on the bottom and sidewalls of the recess and fill the recess can protect the surface of the first dielectric layer over the channel region from being affected by the surface modification process, thereby maintaining the hydrophilicity of the surface of the first dielectric layer over the channel region. The surface of the first dielectric layer over the channel region has different properties from the surface of the first dielectric layer over the source and drain regions. This allows the second dielectric layer to be formed only on the surface of the first dielectric layer over the channel region, and not on the surface of the first dielectric layer over the source and drain regions, during the subsequent formation of the second dielectric layer.

[0045] Regarding the mask layer 103 , the material forming the mask layer 103 includes photoresist, silicon oxide, silicon oxynitride, or silicon nitride, etc. Of course, the material of the mask layer 103 is usually different from the material of the first dielectric layer 101 .

[0046] In some embodiments, forming the mask layer 103 includes: referring to Figure 4, forming an initial mask layer 113, the initial mask layer 113 covers the first dielectric layer 101 and fills the groove 121; return to reference Figure 3 , the initial mask layer 113 located on the source region I and the drain region II is removed, and the initial mask layer 113 retained in the groove 121 is used as the mask layer 103.

[0047] In this embodiment, the material forming the initial mask layer 113 is photoresist, and the photoresist located on the source region I and the drain region II can be removed by light-defined areas to improve the manufacturing efficiency of the semiconductor structure; in other embodiments, the material forming the initial mask layer can be silicon oxide, silicon nitride or silicon oxynitride, etc., and the initial mask layer located on the source region and the drain region is subsequently removed by a graphical method.

[0048] In other embodiments, reference Figure 5 The process steps of forming the mask layer 103 and performing surface treatment include: using the first gas G1 to perform plasma etching on the initial mask layer 113 to remove the initial mask layer 113 located on the source region I and the drain region II; Figure 6 When a signal indicating that the first dielectric layer 101 is exposed is detected, the first gas G1 is replaced with the second gas G2 to perform surface modification on the first dielectric layer 101 on the source region I and the drain region II, with the remaining initial mask layer 113 serving as the mask layer 103. In other words, the first dielectric layer is detected simultaneously during the process step of removing the initial mask layer on the source and drain regions. When it is detected that the surface of the first dielectric layer on the source and drain regions is exposed, the process gas is replaced to perform surface modification on the first dielectric layer on the source and drain regions. This allows the removal of the initial mask layer on the source and drain regions and the surface modification of the first dielectric layer on the source and drain regions to be performed in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure.

[0049] As for the first gas G1 and the second gas G2, the first gas G1 can be CH4, and the second gas G2 can be H2. It is understood that when the material of the first dielectric layer is silicon oxide, the first gas cannot contain oxygen. Since silicon oxide contains oxygen, the oxygen in the oxygen will affect the detection of the first dielectric layer, resulting in deviations in the detection results.

[0050] In other embodiments, the first gas may also use other types of gases as etching gases, such as inert series, corrosive series, oxidizing series, and C, F series etching gases; the second gas may also use other types of gases as surface modification process gases to meet the requirement of converting the surface of the first dielectric layer on the source region and the drain region into a hydrophobic surface.

[0051] refer to Figure 7, the mask layer 103 is removed and a second dielectric layer 102 is formed. The second dielectric layer 102 only covers the surface of the first dielectric layer 101 on the channel region III, that is, the second dielectric layer 102 is formed on the surface of the first dielectric layer 101 on the bottom and sidewalls of the groove 121, wherein the dielectric constant of the second dielectric layer 102 is greater than the dielectric constant of the first dielectric layer 101.

[0052] The second dielectric layer 102 may be formed of a material having a high dielectric constant, such as titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, or aluminum oxide. The high dielectric constant material may be a metal oxide, metal nitride, metal oxynitride, metal silicate, transition metal oxide, transition metal nitride, or transition metal silicate. Examples of high dielectric constant materials include, but are not limited to, hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), zirconium oxide (HfZrO), silicon nitride, silicon oxide, zirconium oxide, titanium oxide, aluminum, aluminum oxide, and a hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy.

[0053] Because the physical properties of the interface between the high-k dielectric material and the substrate differ significantly, factors such as lattice mismatch and interdiffusion at the interface result in a high density of interface states, which can severely impact device characteristics and even cause device failure. The first dielectric layer can serve as an intermediate layer between the second dielectric layer and the substrate, preventing diffusion reactions between the second dielectric layer and the substrate, thereby improving the stability of the semiconductor structure. The second dielectric layer has a high k dielectric constant, which can reduce the physical thickness of the gate dielectric layer (composed of the first and second dielectric layers) while maintaining the equivalent oxide thickness (EOT) of the gate dielectric layer unchanged, thereby reducing direct tunneling and tunneling current.

[0054] In some embodiments, the second dielectric layer 102 can be formed using an atomic layer deposition process. The atomic layer deposition process has excellent properties such as uniform deposition over a large area, nanometer-scale controllable film thickness growth, low-temperature deposition, and suitability for various complex structures (such as structures with high aspect ratios), thus facilitating the formation of a second dielectric layer with uniform thickness and properties.

[0055] In some embodiments, the process gas of the atomic layer deposition process includes water vapor and metal halide compound gas.

[0056] Specifically, in some embodiments, the halogen compound may be zirconium chloride. When the process gases of the corresponding atomic layer deposition process are water vapor and zirconium chloride gas, the chemical reaction equation during the atomic layer deposition is as follows:

[0057] ZrCl4+2H2O=ZrO2+4HCl

[0058] It is understood that water vapor and zirconium chloride gas react to generate zirconium oxide and hydrogen chloride. When the reactants contain water vapor, the reaction easily proceeds on the surface of the first dielectric layer in the channel region when the surface of the first dielectric layer in the channel region is hydrophilic. However, when the surface of the first dielectric layer in the source and drain regions is hydrophobic, the reaction does not easily proceed on the surface of the first dielectric layer in the source and drain regions. As a result, a zirconium oxide layer can be formed on the first dielectric layer in the channel region, while no zirconium oxide layer is formed on the first dielectric layer in the source and drain regions.

[0059] It should be noted that the halogen compound gas provided in this embodiment takes zirconium chloride as an example. Referring to the chemical reaction equation provided in the above embodiment, in other embodiments, the halogen compound gas can also be a halogen compound gas such as aluminum chloride or titanium chloride, which can be applied to the above chemical reaction equation. The halogen element can be fluorine, bromine or iodine, etc., to form a corresponding high dielectric constant material. This embodiment does not constitute a limitation on the halogen compound gas.

[0060] In some embodiments, the atomic layer deposition process may include multiple deposition steps, each of which is used to form a monolayer of the second dielectric layer. Through multiple monolayer deposition steps, the second dielectric layer can be uniformly deposited on the surface of the first dielectric layer in the channel region, resulting in the second dielectric layer having a uniform thickness and excellent consistency.

[0061] Specifically, in some embodiments, the process parameters of each deposition process include: a water vapor flow rate of 600-2000 sccm, a halogen compound gas flow rate of 600-2000 sccm, and a process temperature of 200°C to 400°C. It can be understood that the volume ratio required for the complete reaction of water vapor and halogen compound can be calculated according to the above chemical reaction equation, and then in order to satisfy the chemical reaction more fully, the volume of water vapor or halogen compound can be appropriately increased so that the chemical reaction is more inclined to proceed in the direction of the positive reaction. Therefore, the flow rate of halogen compound gas and water vapor can be selected within a certain range to ensure that the chemical reaction can proceed fully. At the same time, the chemical reaction needs to proceed at a certain temperature. The increase in reaction temperature can appropriately increase the rate of the chemical reaction, but too high a temperature may cause side reactions or be detrimental to the reaction. Therefore, the process temperature needs to be adjusted within a range that is conducive to the chemical reaction.

[0062] In some embodiments, after the previous deposition process is performed and before the next deposition process is performed, the process further includes: removing residual gas from the previous deposition process. It is understood that during the previous deposition process, the chemical reaction will produce hydrogen halide gas. For the progress of the chemical reaction, the more hydrogen halide gas is produced, the less conducive it is for the chemical reaction to proceed in the direction of a positive reaction, thereby affecting subsequent deposition processes and causing incomplete reaction. Therefore, before the next deposition process is performed, purging and removing the residual gas from the previous deposition process can prevent the residual products of the previous reaction from causing the reaction to be incomplete, improve the chemical reaction efficiency of the next deposition process, and facilitate the uniformity of the performance of the second dielectric layer of each monolayer, thereby maintaining the uniformity of the second dielectric layer as a whole.

[0063] In some embodiments, the atomic layer deposition process includes n deposition steps, where n is greater than or equal to 1 and less than or equal to 25. As can be seen from the above reaction equation, water participates in the reaction process. During the deposition step, the chemical reaction facilitates growth on the hydrophilic surface of the first dielectric layer in the channel region. As the number of deposition steps increases, a monolayer of the second dielectric layer gradually nucleates and thickens. Meanwhile, the hydrophobic surfaces of the first dielectric layer in the source and drain regions may decrease in hydrophobicity due to the water in the deposition step. Consequently, when the number of deposition steps exceeds 25, the second dielectric layer may also begin to grow on the surface of the first dielectric layer in the source and drain regions. Therefore, the number of deposition steps needs to be within a certain range to ensure that a sufficiently thick second dielectric layer grows on the surface of the first dielectric layer in the channel region while preventing the second dielectric layer from growing on the surface of the first dielectric layer in the source and drain regions.

[0064] In some embodiments, the manufacturing method further includes: forming a gate, where the gate is located on a surface of the second dielectric layer.

[0065] For the gate, the material forming the gate includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, copper, aluminum, lanthanum, titanium or tungsten.

[0066] The present disclosure provides a method for manufacturing a semiconductor structure, which includes a substrate comprising a substrate and a first dielectric layer covering the substrate, wherein the substrate has a source region, a drain region, and a channel region for forming a transistor structure. The surface of the first dielectric layer is hydrophilic, and then surface modification treatment is performed to make the first dielectric layer on the source and drain regions hydrophobic, while maintaining the hydrophilicity of the first dielectric layer on the channel region. In the subsequent formation of the second dielectric layer, the second dielectric layer grows only on the surface of the first dielectric layer on the channel region, and not on the surface of the first dielectric layer on the source and drain regions. Compared with the process steps of first depositing the second dielectric layer on the entire surface and then patterning the second dielectric layer, the etching process can be omitted, thereby improving the manufacturing efficiency of the semiconductor structure. Furthermore, the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The first dielectric layer can serve as an intermediate layer between the substrate and the second dielectric layer with a high dielectric constant, thereby preventing diffusion reaction between the second dielectric layer and the substrate and improving the stability of the semiconductor structure. The first dielectric layer and the second dielectric layer can together constitute a gate dielectric layer, which can reduce the direct tunneling effect and tunneling current, thereby improving the performance of the semiconductor structure.

[0067] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a semiconductor structure formed using any of the semiconductor structure manufacturing methods described in the aforementioned embodiments to improve the performance of the formed semiconductor structure. It should be noted that for portions identical or corresponding to the aforementioned embodiments, reference may be made to the corresponding descriptions of the aforementioned embodiments and will not be repeated in detail below.

[0068] The semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings, as follows:

[0069] Continue to refer Figure 7 , a semiconductor structure includes: a base 200, the base 200 includes a substrate 100 and a first dielectric layer 101 covering the substrate 100, the substrate 100 includes a source region I, a drain region II and a channel region III, the source region I and the drain region II are located on opposite sides of the channel region III, the surface of the first dielectric layer 101 on the source region I and the drain region II is a hydrophobic surface 112, and the surface of the first dielectric layer 101 on the channel region III is a hydrophilic surface 111; a second dielectric layer 102, the second dielectric layer 102 only covers the surface of the first dielectric layer 101 on the channel region III, and the dielectric constant of the second dielectric layer 102 is greater than the dielectric constant of the first dielectric layer 101.

[0070] The substrate 100 may be formed of an elemental semiconductor material or a compound semiconductor material. The elemental semiconductor material may be germanium or silicon, and the compound semiconductor material may be gallium arsenide, indium phosphide, indium antimonide, silicon carbide, cadmium sulfide, or gallium arsenide silicon.

[0071] As for the source region I and the drain region II, the source region I and the drain region II are used to form the source and drain of the transistor respectively. The source region I and the drain region II can have P-type doped ions or N-type doped ions. Specifically, the N-type ions can be phosphorus ions or arsenic ions, etc.; the P-type ions can be boron ions, indium ions or boron fluoride ions, etc.

[0072] As for the channel region III, the channel region III is used to form a gate of the transistor.

[0073] As for the first dielectric layer 101 , the material of the first dielectric layer 101 includes silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, or a material with a low dielectric constant.

[0074] Regarding the second dielectric layer 102 , the material of the second dielectric layer 102 includes: titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide or other materials with high dielectric constant.

[0075] Here, a hydrophilic surface or hydrophilicity means that the contact angle of a water drop on the surface is less than about 90 degrees; a hydrophobic surface or hydrophobicity means that the contact angle of a water drop on the surface is equal to or greater than 90 degrees (and less than 180 degrees).

[0076] In some embodiments, the thickness of the second dielectric layer is less than 1.8 nm. It is understood that, based on the second dielectric layer formation process described in the above embodiments, when an atomic layer deposition process is used, as the number of deposition steps increases, a monolayer of the second dielectric layer gradually nucleates and thickens. Simultaneously, the hydrophobic surface of the first dielectric layer in the source and drain regions may decrease in hydrophobicity due to water in the deposition process. Consequently, when the number of deposition steps exceeds 25, the second dielectric layer also begins to grow on the surface of the first dielectric layer in the source and drain regions. Therefore, the thickness of the second dielectric layer needs to be less than 1.8 nm to prevent the formation of the second dielectric layer on the surface of the first dielectric layer in the source and drain regions, while maintaining a sufficiently thick second dielectric layer on the surface of the first dielectric layer in the channel region.

[0077] The semiconductor structure provided by the embodiment of the present disclosure includes a base including a substrate and a first dielectric layer covering the substrate, the substrate having a source region, a drain region and a channel region for forming a transistor structure; the surface of the first dielectric layer on the channel region is hydrophilic, and the first dielectric layer on the source region and the drain region is hydrophobic, so that the second dielectric layer can only cover the surface of the first dielectric layer on the channel region, but not cover the surface of the first dielectric layer on the source region and the drain region, thereby facilitating the selective growth of the second dielectric layer and improving the manufacturing efficiency of the semiconductor structure; further, the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer, and the first dielectric layer can serve as an intermediate layer between the substrate and the second dielectric layer with a high dielectric constant to avoid diffusion reaction between the second dielectric layer and the substrate, thereby improving the stability of the semiconductor structure, and the first dielectric layer and the second dielectric layer can jointly constitute a gate dielectric layer, which can reduce the direct tunneling effect and the tunneling current, thereby improving the performance of the semiconductor structure.

[0078] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a first dielectric layer covering the substrate, the substrate comprising a source region, a drain region and a channel region, the source region and the drain region being located on opposite sides of the channel region, and the first dielectric layer having a hydrophilic surface; performing surface modification treatment on the first dielectric layer on the source region and the drain region to convert the hydrophilic surface of the first dielectric layer on the source region and the drain region into a hydrophobic surface; A second dielectric layer is formed, where the second dielectric layer only covers a surface of the first dielectric layer on the channel region, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The surface modification treatment of the first dielectric layer on the source region and the drain region includes: using H + The surface of the first dielectric layer on the source region and the drain region is bombarded.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The H + The bombardment direction is perpendicular to the surface of the first dielectric layer on the source region and the drain region.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: The substrate has a groove exposing a surface of the channel region; The forming of the second dielectric layer includes: forming the second dielectric layer on the surface of the first dielectric layer on the bottom and sidewalls of the groove.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: Before performing the surface modification treatment on the first dielectric layer on the source region and the drain region, the manufacturing method further includes: forming a mask layer, wherein the mask layer covers the first dielectric layer on the bottom and sidewalls of the groove and fills the groove; After performing the surface modification treatment on the first dielectric layer on the source region and the drain region, the manufacturing method further includes: removing the mask layer.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: Forming the mask layer includes: forming an initial mask layer, wherein the initial mask layer covers the first dielectric layer and completely fills the groove; The initial mask layer located on the source region and the drain region is removed, and the initial mask layer remaining in the groove serves as the mask layer.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The process steps of forming the mask layer and performing the surface treatment include: using a first gas to perform plasma etching on the initial mask layer to remove the initial mask layer located on the source region and the drain region; when a signal indicating that the first dielectric layer is exposed is detected, replacing the first gas with a second gas to perform the surface modification treatment on the first dielectric layer on the source region and the drain region.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: The first gas includes CF 4 , and the second gas includes H 2 .

9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The second dielectric layer is formed by an atomic layer deposition process.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The process gas of the atomic layer deposition process includes water vapor and metal halogen compound gas.

11. The method for manufacturing a semiconductor structure according to claim 9, wherein: The atomic layer deposition process includes multiple deposition steps, and each deposition step is used to form a second dielectric layer of a monomolecular layer.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The process parameters of each deposition process include: a flow rate of water vapor of 600-2000 sccm, a flow rate of the halogen compound gas of 600-2000 sccm, and a process temperature of 200° C. to 400° C.

13. The method for manufacturing a semiconductor structure according to claim 11, wherein: After performing the previous deposition process and before performing the next deposition process, the method further includes removing residual gas from the previous deposition process.

14. The method for manufacturing a semiconductor structure according to claim 11, wherein: The atomic layer deposition process includes n deposition steps, wherein n is greater than or equal to 1 and less than or equal to 25.

15. The method for manufacturing a semiconductor structure according to claim 1, wherein: Also includes: A gate is formed, and the gate is located on the surface of the second dielectric layer.

16. A semiconductor structure, characterized in that The method for manufacturing a semiconductor structure according to any one of claims 1 to 15 comprises: a substrate comprising a substrate and a first dielectric layer covering the substrate, the substrate comprising a source region, a drain region, and a channel region, the source region and the drain region being located on opposite sides of the channel region, the surface of the first dielectric layer on the source region and the drain region being a hydrophobic surface, and the surface of the first dielectric layer on the channel region being a hydrophilic surface; A second dielectric layer, wherein the second dielectric layer only covers a surface of the first dielectric layer on the channel region, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.

17. The semiconductor structure according to claim 16, wherein: The thickness of the second dielectric layer is less than 1.8 nm.

18. The semiconductor structure according to claim 16, wherein: The material of the first dielectric layer includes silicon oxide, silicon nitride or silicon oxynitride, and the material of the second dielectric layer includes titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide or aluminum oxide.

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