Resistive structure and method of forming the same

Abstract

A method for forming a resistance structure includes: providing a substrate; forming a first resistance layer on a surface of the substrate; forming an initial second resistance layer on a surface of the first resistance layer, and a resistivity of the initial second resistance layer is higher than a resistivity of the first resistance layer; forming an mth dielectric layer on a surface of the initial second resistance layer, the mth dielectric layer has a via exposing the surface of the initial second resistance layer; performing a modification treatment on the initial second resistance layer exposed by the via to form a contact layer at a bottom of the via, the contact layer is located on the surface of the first resistance layer and is covered by the mth dielectric layer, the initial second resistance layer covered by the mth dielectric layer forms a second resistance layer, a sidewall of the contact layer is in contact with a sidewall of the second resistance layer, and a resistivity of the contact layer is less than a resistivity of the second resistance layer; and forming a conductive structure filling the via on the contact layer. The formed resistance structure has high reliability and good electrical performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a resistance structure in a semiconductor device and a forming method thereof. BACKGROUND

[0002] With the rapid development of semiconductor manufacturing technology, the size of semiconductor devices is continuously reduced, and higher requirements are put forward for semiconductor manufacturing technology and structure. Among them, resistance, as an important integrated circuit element, can cooperate with the adjustment of the electrical parameters of the devices in the circuit to make the integrated circuit achieve the expected function, so it has attracted widespread attention from researchers. Generally, the resistance device is located on the semiconductor substrate and is electrically connected to other devices through a conductive structure. Common resistance materials include metals, metal nitrides, metal carbides, etc.

[0003] In the prior art, the via located above the resistance device is filled with tungsten to form a conductive structure, so that the resistance device is conductive with other devices. A number of studies have shown that in the filling process of the via (V0) of 7nm (N7) and below, the application of selective tungsten deposition process can effectively improve the electrical performance of the semiconductor device.

[0004] Titanium nitride material is widely used as a constituent material of resistance devices due to its good thermal stability, high chemical stability, and wide adjustable range of resistivity. In the preparation process of the resistance device, in order to make the resistance of the device reach the target value, the thickness of the titanium nitride layer needs to be controlled within a certain range, and too thick titanium nitride will result in too low resistance.

[0005] In the process of manufacturing resistance devices and their electrical connections, the process steps of etching and filling the via often waste the resistance layer connected to the via, making the thinner resistance layer easy to be penetrated, resulting in resistance failure and poor device contact. If the thickness of the resistance layer is thickened, the resistance value of the resistance layer will be low, which cannot meet the resistance value requirement of the device. SUMMARY

[0006] The technical problem solved by the present application is to provide a forming method of a resistance structure, which can effectively improve the reliability of the semiconductor device and improve the electrical performance of the device.

[0007] To solve the above technical problems, the embodiment of the present application provides a forming method of a resistance structure, comprising: providing a substrate, the substrate comprising a substrate, a device structure on the substrate, a conductive layer connected to the device structure, and an interconnection layer connected to the conductive layer, the interconnection layer comprising n layers; forming a first resistance layer on the surface of the substrate; forming an initial second resistance layer on the surface of the first resistance layer, and the resistivity of the initial second resistance layer is higher than that of the first resistance layer; forming an mth dielectric layer on the surface of the initial second resistance layer, the mth dielectric layer having a via exposing the surface of the initial second resistance layer; performing modification treatment on the initial second resistance layer exposed by the via to form a contact layer at the bottom of the via, the contact layer being located on the surface of the first resistance layer, the initial second resistance layer covered by the mth dielectric layer forming a second resistance layer, the sidewall of the contact layer being in contact with the sidewall of the second resistance layer, and the resistivity of the contact layer being less than that of the second resistance layer; and forming a conductive structure filling the via on the contact layer.

[0008] Optionally, the method of the modification treatment comprises: performing reduction treatment on the initial second resistance layer exposed by the via to form the contact layer.

[0009] Optionally, the process of the reduction treatment is plasma treatment, and the process parameters of the reduction treatment comprise: the reaction gas comprises hydrogen.

[0010] Optionally, the method of the modification treatment comprises: before performing reduction treatment on the initial second resistance layer exposed by the via, performing oxidation treatment on the initial second resistance layer exposed by the via to process the initial second resistance layer exposed below the via into a metal oxide layer; and performing reduction treatment on the metal oxide layer to form the contact layer.

[0011] Optionally, the process of the reduction treatment is plasma treatment, the process parameters of the reduction treatment comprise: the reaction gas comprises hydrogen; the process of the oxidation treatment is plasma treatment, and the process parameters of the oxidation treatment comprise: the reaction gas comprises oxygen.

[0012] Optionally, the material of the conductive structure comprises tungsten, and the process of forming the conductive structure is a selective deposition process.

[0013] Optionally, the material of the first resistance layer is titanium nitride.

[0014] Optionally, the thickness of the first resistance layer is 30 angstroms to 100 angstroms, and the thickness of the initial second resistance layer is 30 angstroms to 100 angstroms.

[0015] Optionally, the material of the initial second resistance layer comprises one or more of metal oxides and metal nitrides in combination.

[0016] Optionally, the material of the mth dielectric layer is silicon oxide or silicon nitride.

[0017] Optionally, the forming method of the mth dielectric layer and the via hole comprises: forming an mth dielectric material layer on the surface of the initial second resistance layer; forming a photoresist pattern layer on the mth dielectric material layer; etching the mth dielectric material layer with the photoresist pattern layer as a mask to form the mth dielectric layer and the via hole.

[0018] Optionally, the value of the layer number n of the interconnection layer includes natural numbers 1-12.

[0019] Correspondingly, the application also provides a resistance structure formed by any of the above methods, comprising: a substrate, the substrate comprising a base, a device structure on the base, a conductive layer connecting the device structure, and an interconnection layer connected with the conductive layer, the interconnection layer comprising n layers; a first resistance layer on the surface of the substrate; a second resistance layer on the surface of the first resistance layer, and the resistivity of the second resistance layer is higher than that of the first resistance layer; an mth dielectric layer on the surface of the second resistance layer, the mth dielectric layer having a via hole exposing the surface of the second resistance layer; a contact layer at the bottom of the via hole, the contact layer being on the surface of the first resistance layer, the sidewall of the contact layer being in contact with the sidewall of the second resistance layer, and the resistivity of the contact layer being less than that of the second resistance layer; and a conductive structure on the contact layer, the conductive structure filling the via hole.

[0020] Optionally, the material of the conductive structure comprises tungsten.

[0021] Optionally, the material of the first resistance layer is titanium nitride.

[0022] Optionally, the thickness of the first resistance layer is 30-100 angstroms, and the thickness of the second resistance layer is 30-100 angstroms.

[0023] Optionally, the material of the second resistance layer comprises one or more of metal oxides and metal nitrides in combination.

[0024] Optionally, the material of the mth dielectric layer comprises silicon oxide or silicon nitride.

[0025] Optionally, the value of the layer number n of the interconnection layer includes natural numbers 1-12.

[0026] Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:

[0027] The forming method of the technical scheme of the present application forms a second resistance layer on the first resistance layer, which can serve as a buffer layer for the process of forming a via and a conductive structure, reducing the loss of the first resistance layer and weakening the problem of resistance layer failure. Since the resistance of the second resistance layer is much higher than that of the first resistance layer, the resistance after parallel connection is basically consistent with the single-layer resistance of the first resistance layer. Moreover, since the second resistance layer exists as a buffer layer, the thickness of the first resistance layer can be reduced until the requirement of high resistance of the device is met. In addition, the resistivity of the contact layer is less than that of the second resistance layer, which can effectively realize the electrical connection between the resistance layer and the conductive structure and promote the deposition of the conductive structure. Therefore, the formed resistance layer structure can effectively improve the reliability of the semiconductor device and improve the electrical performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figures 1 to 2 is a cross-sectional schematic diagram of an embodiment of a forming process of a resistance structure;

[0029] Figures 3 to 8 is a cross-sectional structure schematic diagram of a forming process of a resistance structure of an embodiment of the present application. DETAILED DESCRIPTION

[0030] As known from the background art, in the process of manufacturing a resistance device and its electrical connection, the process of etching and filling a via will damage the resistance layer connected to the via, causing the thin resistance layer to be easily penetrated, resulting in resistance failure. If the thickness of the resistance layer is thickened, the resistance value of the resistance layer will be reduced, which cannot meet the resistance value requirement of the device.

[0031] Figures 1 to 2 is a cross-sectional schematic diagram of an embodiment of a forming process of a resistance structure.

[0032] Referring to Figure 1 , a substrate 100 is provided, a resistance layer 101 is formed on the substrate 100, the material of the resistance layer 101 is titanium nitride, a dielectric layer 102 is formed on the resistance layer 101, and the material of the dielectric layer 102 is silicon nitride or silicon oxide.

[0033] Referring to Figure 2 , a via is formed in the dielectric layer 102, and a conductive structure 103 is formed to fill the via, the material of the conductive structure 103 includes tungsten, and the process of forming the conductive structure 103 is a selective deposition process.

[0034] In the via etching and filling process, the resistor layer 101 is consumed, and the thinner resistor layer 101 is easily penetrated, resulting in resistance failure and poor device contact. To solve the above problems, one method is to thicken the resistor layer 101, which makes the resistance of the resistor layer 101 lower, and cannot meet the high resistance requirement of the device. Therefore, it is necessary to optimize the existing resistor structure, and solve the consumption and penetration problems of the resistor layer without changing the thickness of the resistor layer.

[0035] To solve the above problems, the present application provides a resistor structure forming method, comprising:

[0036] forming a second resistor layer and a contact layer on the surface of the first resistor layer, wherein the resistivity of the second resistor layer is higher than that of the first resistor layer, and the resistivity of the contact layer is lower than that of the second resistor layer.

[0037] The second resistor layer on the first resistor layer can act as a buffer layer to reduce the loss of the first resistor layer in the via etching and filling process, and also allows the thickness of the first resistor layer to be reduced until the high resistance requirement of the device is met. In addition, the contact layer makes the first resistor layer and the second resistor layer form a parallel connection, and the resistance after parallel connection is basically consistent with the single-layer resistance of the first resistor layer. At the same time, the contact layer can realize circuit connection and promote the deposition of the conductive structure.

[0038] To make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0039] Figures 3 to 8 is a cross-sectional structure schematic diagram of the forming process of the resistor structure of the embodiment of the present application.

[0040] Referring to Figure 3 , a substrate 200 is provided.

[0041] In the embodiment, the substrate includes a substrate 300, a device structure 301 on the substrate 300, a conductive layer (not shown) connected to the device structure 301, and an interconnection layer (not shown) connected to the conductive layer, the interconnection layer including n layers.

[0042] The substrate 300 is used to provide a platform for subsequent processes, and the constituent materials of the substrate 300 include silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc.

[0043] In the embodiment, the value of the number n of layers of the interconnection layer includes natural numbers 1-12.

[0044] Referring to Figure 4 , a first resistor layer 302 is formed on the surface of the substrate 200.

[0045] In the embodiment, the material of the first resistance layer 302 is titanium nitride. Titanium nitride has good chemical stability, wear resistance and high hardness. By adjusting the thickness and microstructure of the titanium nitride layer, a wide range of resistance can be achieved. The first resistance layer 302 can be doped with carbon, and the higher the carbon concentration, the higher the resistance of the first resistance layer 302.

[0046] In the embodiment, the forming process of the first resistance layer 302 includes chemical vapor deposition, physical vapor deposition or atomic layer deposition process. The reaction gas of the chemical vapor deposition or atomic layer deposition process includes titanium tetrachloride (TiCl4) and ammonia (NH3).

[0047] The thickness of the first resistance layer 302 is 30 angstroms to 100 angstroms. The first resistance layer 302 serves as a resistance element in a circuit and is connected to other parts of the circuit. The thickness of the first resistance layer 302 can be adjusted to meet the resistance requirements of the resistance device in the circuit.

[0048] In other embodiments, the material of the first resistance layer includes titanium nitride, aluminum nitride, etc.

[0049] Please refer to Figure 5 An initial second resistance layer 303 is formed on the surface of the first resistance layer 302, and the resistivity of the initial second resistance layer 303 is higher than that of the first resistance layer 302.

[0050] The thickness of the initial second resistance layer 303 is 30 angstroms to 100 angstroms. The material of the initial second resistance layer 303 includes one or more of metal oxides and metal nitrides. The metal oxides include tungsten oxide, aluminum oxide, titanium oxide, etc. The metal nitrides include tungsten nitride, aluminum nitride, etc.

[0051] The initial second resistance layer 303 is doped with carbon. By increasing the concentration of carbon doping, the resistivity of the initial second resistance layer 303 can be increased until the device requirements are met.

[0052] The forming process of the initial second resistance layer 303 includes chemical vapor deposition, physical vapor deposition or atomic layer deposition process. The above process can accurately control the thickness of the initial second resistance layer 303. By changing the composition of the reaction gas source, a variety of combinations and changes of the chemical composition of the initial second resistance layer 303 can be achieved, so that the resistivity of the initial second resistance layer 303 meets the requirements. At the same time, the forming process has little effect on other devices, reducing the generation of reaction byproducts.

[0053] The initial second resistance layer 303 provides a buffer layer for the first resistance layer 302, avoiding the subsequent formation of a via and a conductive structure directly on the first resistance layer 302, thereby reducing the consumption of the first resistance layer 302 in the subsequent via etching process; at the same time, the consumption of the first resistance layer 302 due to the reaction with the conductive structure in the subsequent conductive structure forming process is also reduced; in addition, the first resistance layer 302 can be protected in the subsequent chemical mechanical polishing (CMP) process, reducing the penetration and corrosion of the polishing liquid, thereby ensuring that the electrical performance of the first resistance layer 302 is not affected. In addition, the initial second resistance layer 303 provides raw materials for the subsequent formation of a contact layer, which is used for circuit communication of the device, and is also conducive to the deposition of the subsequent conductive structure.

[0054] Reference is made to Figure 6 An mth dielectric layer 304 is formed on the surface of the initial second resistance layer 303, and the mth dielectric layer 304 has a via 305 exposing the surface of the initial second resistance layer 303.

[0055] The forming method of the mth dielectric layer 304 and the via 305 includes: forming an mth dielectric material layer (not shown) on the surface of the initial second resistance layer 303; forming a photoresist pattern layer on the mth dielectric material layer; etching the mth dielectric material layer to form the mth dielectric layer 304 and the via 305, taking the photoresist pattern layer as a mask.

[0056] In this embodiment, m-1 dielectric layers are formed on the substrate 300 before the mth dielectric layer 304 is formed, where m is a natural number.

[0057] The material of the mth dielectric layer 304 is silicon oxide or silicon nitride. The forming process of the mth dielectric material layer includes a chemical vapor deposition, a physical vapor deposition or an atomic layer deposition process.

[0058] The forming step of the photoresist pattern layer includes: forming a photoresist film on the surface of the mth dielectric material layer by a coating process and exposing and developing to form a photoresist pattern layer with a via pattern.

[0059] The etching process of the mth dielectric material layer is an anisotropic dry etching process, and the etching direction is perpendicular to the surface of the substrate 200 until the via 305 is formed. Due to the presence of the initial second resistance layer 303, the consumption of the first resistance layer 302 located below the initial second resistance layer 303 in the etching process of the via 305 is reduced.

[0060] In this embodiment, after the via 305 is formed, the photoresist pattern layer is removed by a gray ash process.

[0061] Reference is made to Figure 7The initial second resistance layer 303 exposed by the via hole 305 is modified to form a contact layer 310 at the bottom of the via hole 305, the contact layer 310 is on the surface of the first resistance layer 302 and is covered by the mth dielectric layer 304, the initial second resistance layer 303 covered by the mth dielectric layer 304 forms a second resistance layer 306, the sidewall of the contact layer 310 is in contact with the sidewall of the second resistance layer 306, and the resistivity of the contact layer 310 is less than the resistivity of the second resistance layer 306.

[0062] The material of the contact layer 310 is a conductive metal, which includes one or more combinations of tungsten, aluminum, titanium, etc., and the contact layer 310 is doped with carbon. The top surface of the contact layer 310 is exposed by the via hole 305 in the mth dielectric layer 304; the thickness of the contact layer 310 is 30 angstroms to 100 angstroms.

[0063] The contact layer 310 has good conductivity and a resistivity lower than that of the second resistance layer 306, and the contact layer 310 is used to connect the first resistance layer 302 and the second resistance layer 306 to form a parallel structure and play a role together. Since the resistance of the second resistance layer 306 is much greater than that of the first resistance layer 302, the resistance of the second resistance layer 306 in parallel with the first resistance layer 302 is basically consistent with the single-layer resistance of the first resistance layer 302, ensuring that the function of the resistance element is not affected. At the same time, the contact layer 310 also serves as an electrical connection to connect the first resistance layer 302, the second resistance layer 306, and the conductive structure formed in the via hole 305 subsequently. In addition, since the material of the contact layer 310 includes a metal element, it can participate in the formation reaction of the conductive structure during the subsequent filling process of the via hole 305, which is conducive to the formation and deposition of the conductive structure.

[0064] In this embodiment, the material of the initial second resistance layer 303 includes a metal oxide, and the initial second resistance layer 303 is doped with carbon. The method of the modification process includes reducing the initial second resistance layer 303 exposed by the via hole 305 to form the contact layer 310. The process of the reduction treatment includes plasma treatment; the process parameters of the reduction treatment include that the reaction gas includes hydrogen, the reaction temperature is 200-400 degrees Celsius, the reaction pressure is 100-1000 millitorr, and the radio frequency power is 300-2000 watts.

[0065] In another embodiment, the material of the initial second resistance layer includes a metal nitride, and the initial second resistance layer is doped with carbon. Since the metal nitride is difficult to be directly reduced to a metal element, it is necessary to process the metal nitride into a metal oxide before the reduction treatment, which is conducive to the subsequent reduction treatment.

[0066] In another embodiment, the method of the modification process comprises: before the reduction process of the initial second resistance layer exposed by the via, an oxidation process is performed on the initial second resistance layer exposed by the via, the initial second resistance layer exposed by the via is processed into a metal oxide layer; a reduction process is performed on the metal oxide layer to form the contact layer.

[0067] The oxidation process includes contact plasma processing, remote plasma processing and wet processing. When the oxidation process is contact plasma processing, the process parameters include: the reaction gas includes oxygen, the reaction temperature is 20-100 degrees Celsius, the reaction pressure is 100-1000 mTorr, and the radio frequency power is 300-1000 watts; when the oxidation process is remote plasma processing, the process parameters include: the reaction gas includes oxygen, the reaction temperature is 200-400 degrees Celsius, the reaction pressure is 800-2000 mTorr, and the radio frequency power is 2000-3000 watts; when the oxidation process is wet processing, the reaction reagent includes 1%-10% hydrogen peroxide or ozone.

[0068] The reduction process is plasma processing, and the process parameters of the reduction process include: the reaction gas includes hydrogen, the reaction temperature is 200-400 degrees Celsius, the reaction pressure is 100-1000 mTorr, and the radio frequency power is 300-2000 watts.

[0069] Please refer to Figure 8 A conductive structure 320 is formed on the contact layer 310 to fill the via 305. Figure 7 As shown in the figure.

[0070] The material of the conductive structure 320 includes tungsten. The process of forming the conductive structure 320 is a selective deposition process; the method of the selective deposition process includes: forming a nucleation layer (not shown) in the via; depositing a main body layer (not shown) on the nucleation layer, and the nucleation layer and the main body layer form the conductive structure 320 to fill the via. In addition, the forming step of the conductive structure 320 further includes, after the via is filled, removing the excess conductive structure 320 on the surface of the mth dielectric layer 304 by using a chemical mechanical polishing process until the surface of the mth dielectric layer 304 is exposed.

[0071] The forming process of the nucleation layer and the main body layer includes a chemical vapor deposition process, and the reaction gas of the process includes silane (SiH4), hydrogen (H2) and tungsten hexafluoride (WF6).

[0072] In the forming process of the conductive structure 320, since the material of the contact layer 310 includes a metal element, the contact layer 310 is in direct contact with the conductive structure 320, so that the contact layer 310 can participate in the reaction of forming the conductive structure 320, and promote the formation and deposition of the conductive structure 320. In addition, the contact layer 310 and the second resistance layer 306 act as a buffer layer of the first resistance layer 302, reducing the consumption of the first resistance layer 302 in the forming process of the conductive structure 320, and protecting the first resistance layer 302 from penetration corrosion by the polishing liquid in the subsequent chemical mechanical polishing (CMP) process, reducing the loss of the first resistance layer 302 and protecting the electrical performance of the resistance element.

[0073] Correspondingly, the application also provides a resistance structure formed by the above method, please continue to refer to Figure 8 , comprising:

[0074] a substrate 200, the substrate comprising a base 300, a device structure 301 on the base 300, a conductive layer (not shown) connected to the device structure 301, and an interconnection layer (not shown) connected to the conductive layer, the interconnection layer comprising n layers;

[0075] a first resistance layer 302 on the surface of the substrate 200;

[0076] a second resistance layer 306 on the surface of the first resistance layer 302, and the resistivity of the second resistance layer 306 is higher than that of the first resistance layer 302;

[0077] an mth dielectric layer 304 on the surface of the second resistance layer 306, the mth dielectric layer 304 having a via 305 exposing the surface of the second resistance layer 306;

[0078] a contact layer 310 at the bottom of the via 305, the contact layer 310 being on the surface of the first resistance layer 302, and the resistivity of the contact layer 310 being less than that of the second resistance layer 306;

[0079] a conductive structure 320 on the contact layer 310, the conductive structure 320 filling the via 305.

[0080] The above and other embodiments of the present application will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0081] In the present embodiment, the number n of layers of the interconnection layer includes natural numbers 1-12. The material of the first resistance layer 302 includes titanium nitride; the material of the second resistance layer 306 includes one or more of metal oxides and metal nitrides in combination. The thickness of the first resistance layer 302 is 30-100 angstroms; the thickness of the second resistance layer 306 is 30-100 angstroms. The material of the mth dielectric layer 304 includes silicon oxide or silicon nitride; and the material of the conductive structure 320 includes tungsten.

[0082] The second resistance layer 306 and the contact layer 310 are located on the surface of the first resistance layer 302, both of which serve as buffer layers, reducing the consumption of the first resistance layer 302 in the via 305 etching process, and also reducing the loss of the first resistance layer 302 caused by the reaction of the conductive structure 320 with the first resistance layer 302. In addition, it also weakens the penetration corrosion of the first resistance layer 302 by the grinding liquid in the process of chemical mechanical grinding (CMP) of the conductive structure 320. In addition, the contact layer 310 located on the surface of the first resistance layer 302 serves as an electrical connection, allowing the first resistance layer 302, the second resistance layer 306, and the conductive structure 320 to communicate with each other, so that the first resistance layer 302 and the second resistance layer 306 jointly play the role of a resistor.

[0083] Although the present application is disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the scope of protection of the present application should be limited by the scope defined in the claims.

Claims

1. A resistive structure, characterized by, The application relates to a substrate, which comprises a base, a device structure on the base, a conductive layer connected with the device structure, and an interconnection layer connected with the conductive layer, wherein the interconnection layer comprises n layers; a first resistance layer on the surface of the substrate; a second resistance layer on the surface of the first resistance layer, and the resistivity of the second resistance layer is higher than that of the first resistance layer; an mth dielectric layer on the surface of the second resistance layer, and the mth dielectric layer has a through hole exposing the surface of the second resistance layer; a contact layer on the bottom of the through hole, the contact layer is on the surface of the first resistance layer, the sidewall of the contact layer is in contact with the sidewall of the second resistance layer, and the resistivity of the contact layer is lower than that of the second resistance layer; and a conductive structure on the contact layer, which fills the through hole. The material of the conductive structure comprises tungsten. The material of the first resistance layer is titanium nitride. The thickness of the first resistance layer is 30-100 angstroms, and the thickness of the second resistance layer is 30-100 angstroms. The material of the second resistance layer comprises one or more of metal oxide, metal nitride in combination. The material of the mth dielectric layer comprises silicon oxide or silicon nitride. The value of the number n of the interconnection layer is a natural number of 1-12.

2. The resistance structure of claim 1, wherein, The application also discloses a method for manufacturing the substrate.

3. The resistance structure of claim 1, wherein, The method comprises the following steps: providing a substrate, which comprises a base, a device structure on the base, a conductive layer connected with the device structure, and an interconnection layer connected with the conductive layer, wherein the interconnection layer comprises n layers; forming a first resistance layer on the surface of the substrate; forming an initial second resistance layer on the surface of the first resistance layer, and the resistivity of the initial second resistance layer is higher than that of the first resistance layer; forming an mth dielectric layer on the surface of the initial second resistance layer, and the mth dielectric layer has a through hole exposing the surface of the initial second resistance layer; performing modification treatment on the initial second resistance layer exposed by the through hole to form a contact layer on the bottom of the through hole, the contact layer is on the surface of the first resistance layer, the initial second resistance layer covered by the mth dielectric layer forms a second resistance layer, the sidewall of the contact layer is in contact with the sidewall of the second resistance layer, and the resistivity of the contact layer is lower than that of the second resistance layer; and forming a conductive structure on the contact layer, which fills the through hole.

4. The resistive structure of claim 1, wherein, The method of the modification treatment comprises: performing reduction treatment on the initial second resistance layer exposed by the through hole to form the contact layer.

5. The resistive structure of claim 1, wherein, The process of the reduction treatment is plasma treatment.

6. The resistive structure of claim 1, wherein, The reaction gas of the reduction treatment comprises hydrogen.

7. The resistive structure of claim 1, wherein, The method of the modification treatment comprises: performing oxidation treatment on the initial second resistance layer exposed by the through hole before performing reduction treatment on the initial second resistance layer exposed by the through hole, and processing the initial second resistance layer exposed below the through hole into a metal oxide layer; and performing reduction treatment on the metal oxide layer to form the contact layer.

8. A method of forming a resistive structure, characterized by, The process of the reduction treatment is plasma treatment, the reaction gas of the reduction treatment comprises hydrogen, the process of the oxidation treatment is plasma treatment, and the reaction gas of the oxidation treatment comprises oxygen. ​ ​ ​ ​ ​ ​ 9. The method of forming a resistive structure of claim 8, wherein, ​ 10. The method of forming a resistive structure of claim 9, wherein, ​ ​ 11. The method of forming a resistive structure of claim 8, wherein, ​ 12. The method of forming a resistive structure of claim 11, wherein, ​ 13. The method of claim 8, wherein the resistive structure is formed by a process selected from the group consisting of: sputtering, evaporation, and chemical vapor deposition. The material of the conductive structure includes tungsten; and the process of forming the conductive structure is a selective deposition process.

14. The method of forming a resistive structure of claim 8, wherein, The material of the first resistance layer is titanium nitride.

15. The method of forming a resistive structure of claim 8, wherein, The thickness of the first resistance layer is 30 angstroms to 100 angstroms; and the thickness of the initial second resistance layer is 30 angstroms to 100 angstroms.

16. The method of forming a resistive structure of claim 8, wherein, The material of the initial second resistance layer includes one or more of a metal oxide, a metal nitride, or a combination thereof.

17. The method of forming a resistive structure of claim 8, wherein, The material of the mth dielectric layer includes silicon oxide or silicon nitride.

18. The method of forming a resistive structure of claim 8, wherein, The method for forming the mth dielectric layer and the via includes: forming an mth dielectric material layer on the surface of the initial second resistance layer; forming a photoresist pattern layer on the mth dielectric material layer; using the photoresist pattern layer as a mask, etching the mth dielectric material layer to form the mth dielectric layer and the via.

19. The method of forming a resistive structure of claim 8, wherein, The value of the number n of the interconnection layers includes natural numbers 1 to 12.

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