Electrostatic discharge protection device

Abstract

The application discloses an electrostatic discharge protection device, which comprises a P-type semiconductor substrate, first and second N-type deep well regions, first to fourth N-type doped regions, first to fourth P-type doped regions and first and second P-type well regions. The first and second N-type deep well regions are located in the P-type semiconductor substrate; the first N-type and P-type doped regions and the first P-type well region are located in the first N-type deep well region; the second N-type and P-type doped regions and the second P-type well region are located in the second N-type deep well region; the third N-type and P-type doped regions are located in the first P-type well region; the fourth N-type and P-type doped regions are located in the second P-type well region; the first P-type and fourth N-type doped regions are electrically connected to an input / output end; the first N-type and second P-type doped regions are electrically connected to a power supply end; and the third N-type and fourth P-type doped regions are electrically connected to a grounding end.

Description

Technical Field

[0001] This invention relates to electrostatic discharge protection devices, and more particularly to the structure and layout of electrostatic discharge protection devices. Background Technology

[0002] Integrated circuits, including semiconductor components, are highly susceptible to damage from electrical overstress (EOS). EOS includes electrostatic discharge (ESD), transient conditions, latch-up, and incorrect polarity connections. ESD conditions are classified as overvoltage or overcurrent events. Electrostatic discharge occurs when an object with accumulated charge comes into contact with an integrated circuit, generating current that can damage the semiconductor components and circuitry. Therefore, protecting semiconductor components from ESD and other electrical overstress conditions is a critical issue. Furthermore, for high-speed, high-end chips, diodes or transistors alone cannot completely eliminate the ESD problem. Summary of the Invention

[0003] Some embodiments of the present invention provide an electrostatic discharge (ESD) protection device. The ESD protection device includes a P-type semiconductor substrate, a first N-type deep well region, a second N-type deep well region, a first N-type doped region, a first P-type doped region, a second N-type doped region, a second P-type doped region, a third N-type doped region, a third P-type doped region, a fourth N-type doped region, a fourth P-type doped region, a first P-type well region, and a second P-type well region. The first N-type deep well region is located in the P-type semiconductor substrate; the first N-type doped region is located in the first N-type deep well region; the first P-type doped region is located in the first N-type deep well region and is arranged side-by-side with and spaced apart from the first N-type doped region; the second N-type deep well region is located in the P-type semiconductor substrate and is arranged side-by-side with and spaced apart from the first N-type deep well region; the second N-type doped region is located in the second N-type deep well region; the second P-type doped region is located in the second N-type deep well region and is arranged side-by-side with and spaced apart from the second N-type doped region; the first P-type well region is located in the first N-type deep well region; the third N-type doped region is located in the first N-type deep well region; the third P-type doped region is located in the first N-type deep well region; the fourth P-type doped region is located in the first N-type deep well region; the fifth P-type doped region is located in the first N-type deep well region; the sixth P-type doped region is located in the first N-type deep well region; the seventh P-type doped region is located in the first N-type deep well region; the eighth P-type doped region is located in the first N-type deep well region; the ninth P-type doped region is located in the first N-type deep well region; the eleventh P-type doped region In a P-type well region; a third P-type doped region is located in the first P-type well region and is arranged side-by-side with and spaced apart from the third N-type doped region; a second P-type well region is located in the second N-type deep well region; a fourth N-type doped region is located in the second P-type well region; and a fourth P-type doped region is located in the second P-type well region and is arranged side-by-side with and spaced apart from the fourth N-type doped region; wherein the first P-type doped region and the fourth N-type doped region are electrically connected to the input / output terminal, wherein the first N-type doped region and the second P-type doped region are electrically connected to the power supply terminal, and wherein the third N-type doped region and the fourth P-type doped region are electrically connected to the ground terminal. Attached Figure Description

[0004] Figure 1 This is a top view schematic diagram of an electrostatic discharge protection device according to some embodiments of the present invention;

[0005] Figure 2 For along Figure 1 The diagram shows a cross-sectional view of the electrostatic discharge protection device according to some embodiments of the present invention along line A-A'.

[0006] Figure 3 for Figure 2 A partially enlarged view shows the equivalent discharge circuit where an electrostatic discharge event occurs between the input / output terminal (IO) and the power supply terminal VCC, or between the ground terminal (VSS) and the input / output terminal (IO), and the parasitic elements of the aforementioned equivalent circuit. Figure 2 A schematic diagram of the corresponding location of the electrostatic discharge protection device;

[0007] Figure 4A This is the equivalent discharge circuit for an electrostatic discharge event occurring between the input / output terminal (IO) and the ground terminal (VSS);

[0008] Figure 4B for Figure 4A Parasitic elements in the equivalent circuit Figure 2 A schematic diagram of the corresponding location of the electrostatic discharge protection device;

[0009] Figure 5A This is the equivalent discharge circuit for an electrostatic discharge event occurring between the power supply terminal (VCC) and the input / output terminal (IO).

[0010] Figure 5B for Figure 5A Parasitic elements in the equivalent circuit Figure 2 A schematic diagram of the corresponding location of the electrostatic discharge protection device;

[0011] Figures 6-10 This is a partial cross-sectional schematic diagram of an electrostatic discharge protection device according to some embodiments of the present invention.

[0012] Symbol Explanation

[0013] 100, 110: Direction

[0014] 200: P-type semiconductor substrate

[0015] 210, 220, 230: Conductors

[0016] 300: Switching circuit

[0017] 300A: Detection circuit

[0018] 302: N-type metal-oxide-semiconductor transistor

[0019] 500, 500A, 500B, 500C, 500D, 500E, 500F: Electrostatic discharge protection devices

[0020] 510, 520: Area

[0021] A-A': Tangent line

[0022] B-B',C-C': Dashed lines

[0023] B1: First parasitic bipolar junction transistor (junction type)

[0024] B2: Second parasitic bipolar junction transistor

[0025] B3: Third parasitic bipolar junction transistor

[0026] B4: Fourth parasitic bipolar junction transistor

[0027] BT: Base

[0028] C1: First capacitor

[0029] C2: Second capacitor

[0030] D1: First parasitic diode

[0031] D2: Second parasitic diode

[0032] D3: Third parasitic diode

[0033] D4: Fourth diode

[0034] DNW1: First type N deep well region

[0035] DNW2: Second type N deep well region

[0036] G1: First gate structure

[0037] G2: Second gate structure

[0038] G3: Third gate structure

[0039] G4: Fourth gate structure

[0040] GR1: First protection ring

[0041] GR2: Second protection ring

[0042] GT: Gate

[0043] IO: Input / Output Terminal

[0044] NW1: First N-type well region

[0045] NM1: First N-type metal-oxide-semiconductor transistor

[0046] NM2: Second type N-type metal-oxide-semiconductor transistor

[0047] N1: First N-type doped region

[0048] N2, N2-1, N2-2: Second N-type doped region

[0049] N3, N3-1, N3-2: Third N-type doped region

[0050] N4, N4-1, N4-2: Fourth N-type doped region

[0051] N5: Fifth N-type doped region

[0052] N6: Sixth N-type doped region

[0053] N7: Seventh N-type doped region

[0054] P1, P1-1, P1-2: First P-type doped region

[0055] P2, P2-1, P2-2: Second P-type doped region

[0056] P3, P3-1, P3-2: Third P-type doped region

[0057] P4: Fourth P-type doped region

[0058] P5: Fifth P-type doped region

[0059] P6: Sixth P-type doped region

[0060] P7: Seventh P-type doped region

[0061] PW1: First P-type well region

[0062] PW2: Second P-type well region

[0063] PW3: Third P-type well region

[0064] PM1: First P-type metal-oxide-semiconductor transistor

[0065] PH1, PH2: Current paths

[0066] SCR-1: First Parasitic Semiconductor Controlled Rectifier

[0067] SCR-2: Second Parasitic Semiconductor Controlled Rectifier

[0068] SDT1: First Source / Drain

[0069] SDT2: Second Source / Drain

[0070] VCC: Power Supply

[0071] VSS: Grounding terminal Detailed Implementation

[0072] The invention is described more fully below with reference to the accompanying drawings of embodiments thereof. However, the invention may be implemented in various different ways and should not be limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numerals denote the same or similar elements in the drawings.

[0073] Figure 1 This is a top view schematic diagram of an electrostatic discharge protection device 500 (including electrostatic discharge protection devices 500A, 500B, 500C, 500D, 500E, and 500F) according to some embodiments of the present invention. Figure 2 For along Figure 1 The diagram shows a cross-sectional view of the electrostatic discharge protection device 500A according to some embodiments of the present invention along line A-A'. The electrostatic discharge protection device 500 is electrically connected between the input / output terminal (IO) and the ground terminal (VSS) of the system to prevent an electrostatic discharge current from flowing through the protected circuit. The electrostatic discharge protection device 500A includes a P-type semiconductor substrate 200, and a first guard ring GR1, a second guard ring GR2, a first N-type deep well region DNW1, a second N-type deep well region DNW2, a first P-type well region PW1, and a second P-type well region PW2 located within the P-type semiconductor substrate 200. The first N-type deep well region DNW1, the second N-type deep well region DNW2, the first P-type well region PW1, and the second P-type well region PW2 each include at least one pair of heavily doped regions with opposite conductivity types. For illustration, Figure 1 Only the above components are shown; the remaining components can be found in [the following locations]. Figure 2 A cross-sectional schematic diagram, which along Figure 1 The tangent AA is taken, and the tangent AA is essentially parallel to the direction 100. For example, the first N-type deep well region DNW1 includes the first N-type doped region N1 and the first P-type doped region P1 (including the first P-type doped regions P1-1 and P1-2), the second N-type deep well region DNW2 includes the second N-type doped region N2 (including the second N-type doped regions N2-1 and N2-2) and the second P-type doped region P2 (including the second P-type doped regions P2-1 and P2-2), the first P-type well region PW1 includes the third N-type doped region N3 (the third N-type doped regions N3-1 and N3-2) and the third P-type doped region P3 (including the third P-type doped regions P3-1 and P3-2), and the second P-type well region PW2 includes the fourth N-type doped region N4 (including the fourth N-type doped regions N4-1 and N4-2) and the fourth P-type doped region P4.

[0074] like Figure 1 , Figure 2 As shown, the first N-type deep well region DNW1 and the second N-type deep well region DNW2 are both located in the P-type semiconductor substrate 200, and are arranged side by side and spaced apart from each other along direction 100. The electrostatic discharge protection device 500A also includes a first N-type doped region N1 and first P-type doped regions P1-1 and P1-2 located in the first N-type deep well region DNW1. The first N-type doped region N1 and the first P-type doped regions P1-1 and P1-2 extend along direction 110 and are disposed in the middle region of the first N-type deep well region DNW1. Furthermore, the first P-type doped regions P1-1 and P1-2 are located on opposite sides of the first N-type doped region N1 that are substantially parallel to direction 110, and are spaced apart from the first N-type doped region N1 along direction 100. In this embodiment, the first N-type doped region N1 is electrically connected to the power supply terminal VCC, and the first P-type doped regions P1-1 and P1-2 are electrically connected to the input / output terminal IO.

[0075] like Figure 1 , Figure 2 As shown, the electrostatic discharge protection device 500A further includes second N-type doped regions N2-1 and N2-2 and second P-type doped regions P2-1 and P2-2 located in the second N-type deep well region DNW2. The second N-type doped regions N2-1 and N2-2 and the second P-type doped regions P2-1 and P2-2 extend along direction 110. Furthermore, the second N-type doped region N2-1 and the second P-type doped region P2-1 are located in the peripheral region of the second N-type deep well region DNW2, close to the first N-type deep well region DNW1, and are arranged side-by-side and spaced apart along direction 100. The second N-type doped region N2-2 and the second P-type doped region P2-2 are located in the peripheral region of the second N-type deep well region DNW2, away from the first N-type deep well region DNW1, and are arranged side-by-side and spaced apart along direction 100. In this embodiment, the second N-type doped regions N2-1 and N2-2 are electrically connected to one output terminal of the switching circuit 300 (the structure of the switching circuit 300 can be found in [reference needed]). Figure 4A The second P-type doped regions P2-1 and P2-2 are electrically connected to the power supply terminal VCC.

[0076] like Figure 1 , Figure 2 As shown, the first P-type well region PW1 of the electrostatic discharge protection device 500A is located in the first N-type deep well region DNW1. In... Figure 1 In the top view, the first P-type well region PW1 is annular and covers the surrounding area of ​​the first N-type deep well region DNW1. In such a way... Figure 2In the cross-sectional view, the first P-type well region PW1 is located on the opposite side of the first N-type doped region N1 along direction 110. The electrostatic discharge protection device 500A also includes third N-type doped regions N3-1 and N3-2, and third P-type doped regions P3-1 and P3-2 located within the first P-type well region PW1. The third N-type doped regions N3-1 and N3-2, and the third P-type doped regions P3-1 and P3-2 extend along direction 110. Furthermore, the third N-type doped region N3-1 and the third P-type doped region P3-1 are located in the peripheral region of the first N-type deep well region DNW1, close to the second N-type deep well region DNW2, and are arranged side-by-side and spaced apart along direction 100. The third N-type doped region N3-2 and the third P-type doped region P3-2 are located in the peripheral region of the first N-type deep well region DNW1, away from the second N-type deep well region DNW2, and are arranged side-by-side and spaced apart along direction 100. In this embodiment, the third N-type doped regions N3-1 and N3-2 are electrically connected to the ground terminal VSS, and the third P-type doped regions P3-1 and P3-2 are electrically connected to another output terminal of the switching circuit 300 (relative to the second N-type doped regions N2-1 and N2-2).

[0077] like Figure 1 , Figure 2 As shown, the second P-type well region PW2 of the electrostatic discharge protection device 500A is located in the second N-type deep well region DNW2, and is disposed in the middle region of the second N-type deep well region DNW2, so that the second N-type deep well region DNW2, which is not covered by the second P-type well region PW2, is in... Figure 1 The top view shows a ring shape. The electrostatic discharge protection device 500A also includes fourth N-type doped regions N4-1 and N4-2, and a fourth P-type doped region P4 located in the second P-type well region PW2. The fourth N-type doped regions N4-1, N4-2, and the fourth P-type doped region P4 extend along direction 110. Furthermore, the fourth N-type doped regions N4-1 and N4-2 are located on opposite sides of the fourth P-type doped region P4, substantially parallel to direction 110, and are spaced apart from the fourth P-type doped region P4 along direction 100. In this embodiment, the fourth N-type doped regions N4-1 and N4-2 are electrically connected to the input / output terminal IO, and the fourth P-type doped region P4 is electrically connected to the ground terminal VSS.

[0078] like Figure 1 , Figure 2As shown, the first protection ring GR1 of the electrostatic discharge protection device 500A is located outside the first N-type deep well region DNW1 and the second N-type deep well region DNW2, respectively surrounding the first N-type deep well region DNW1 and the second N-type deep well region DNW2, and is located between the first P-type well region PW1 and the second P-type well region PW2 along direction 100. The first protection ring GR1 includes a third P-type well region PW3 and a fifth P-type doped region P5 located in the third P-type well region PW3. In this embodiment, the P-type semiconductor substrate 200 can be electrically connected to the ground terminal VSS through the fifth P-type doped region P5.

[0079] like Figure 1 , Figure 2 As shown, the second protection ring GR2 of the electrostatic discharge protection device 500A is located outside the first N-type deep well region DNW1 and the second N-type deep well region DNW2, and surrounds the first protection ring GR1. The second protection ring GR2 includes the first N-type well region NW1 and a fifth N-type doped region N5 located in the first N-type well region NW1. In some embodiments, the fifth N-type doped region N5 is electrically connected to the power supply terminal VCC. Generally, the N-type protection ring (second protection ring GR2) is electrically connected to a higher voltage level, while the P-type protection ring (first protection ring GR1) is electrically connected to a lower voltage level.

[0080] like Figure 1 , Figure 2 As shown, the first P-type well region PW1 and the heavily doped region (including the first N-type doped region N1 and the first P-type doped regions P1-1 and P1-2) disposed in the first N-type deep well region DNW1, and the heavily doped region (including the third N-type doped regions N3-1 and N3-2 and the third P-type doped regions P3-1 and P3-2) disposed in the first P-type well region PW1 are symmetrically arranged along an axis (as shown by the dashed line B-B') passing through the center of the first N-type doped region N1 in the direction 110. Similarly, the second P-type well region PW2 and the heavily doped regions (including the second N-type doped regions N2-1, N2-2 and the second P-type doped regions P2-1, P2-2) disposed in the second N-type deep well region DNW2, and the heavily doped regions (including the fourth N-type doped regions N4-1, N4-2 and the fourth P-type doped region P4) disposed in the second P-type well region PW2 are symmetrically arranged along an axis (as shown by the dashed line C-C') passing through the center of the fourth P-type doped region P4 in direction 110. Therefore, the following figures will capture... Figure 2 Regions 510 and 520 illustrate the equivalent circuits triggered by various electrostatic discharge events occurring at the input / output terminal IO, the power supply terminal VCC, or the ground terminal VSS, as well as the electrostatic discharge protection devices of other embodiments. Furthermore, in the following figures, the second, third, and fourth N-type doped regions are labeled N2, N3, and N4, respectively, and the first, second, and third P-type doped regions are labeled P1, P2, and P3, respectively.

[0081] In the embodiments described below, the switching circuit 300 switches the second N-type doped region N2 and the third P-type doped region P3 to different potentials depending on the circumstances. For example, when the protected circuit is operating normally (no electrostatic discharge event occurs), the second N-type doped region N2, which is electrically connected to the switching circuit 300, is electrically connected to the power supply terminal VCC (its voltage level is equal to the high level), and the third P-type doped region P3, which is electrically connected to the switching circuit 300, is electrically connected to the ground terminal VSS (its voltage level is equal to the ground level). When an electrostatic discharge event occurs at the input / output terminal IO, the power supply terminal VCC, or the ground terminal VSS, the second N-type doped region N2, which is electrically connected to the switching circuit 300, is electrically connected to the ground terminal VSS (its voltage level is equal to the ground level), and the third P-type doped region P3, which is electrically connected to the switching circuit 300, is electrically connected to the power supply terminal VCC (its voltage level is equal to the high level).

[0082] Figure 3 for Figure 2 Enlarged views of regions 510 and 520 show the equivalent discharge circuits where an electrostatic discharge (ESD) event occurs between the input / output terminal IO and the power supply terminal VCC, or the equivalent discharge circuits where an ESD event occurs between the ground terminal VSS and the input / output terminal (IO), and the parasitic elements of the aforementioned equivalent discharge circuits. Figure 2 A schematic diagram of the corresponding location of the 500A electrostatic discharge protection device. (See diagram below.) Figure 3 As shown, the first P-type doped region P1, the first N-type deep well region DNW1, and the first N-type doped region N1 constitute the first parasitic diode D1. When an electrostatic discharge event occurs between the input / output terminal IO and the power supply terminal VCC, the first parasitic diode D1 is triggered to conduct, forming a current path PH1 from the input / output terminal IO to the power supply terminal VCC, thus discharging the static charge away from the protected circuit.

[0083] like Figure 3 As shown, the fourth P-type doped region P4, the second P-type well region PW2, and the fourth N-type doped region N4 constitute the second parasitic diode D2. When an electrostatic discharge event occurs between the ground terminal VSS and the input / output terminal IO, the second parasitic diode D2 is triggered to conduct, forming a current path PH2 from the ground terminal VSS to the input / output terminal IO, thus discharging the static charge away from the protected circuit.

[0084] Figure 4A This displays an alternative equivalent discharge circuit for an electrostatic discharge (ESD) event occurring between the input / output terminal IO and the ground terminal VSS, as well as a switching circuit 300 electrically connected thereto. Figure 4B show Figure 4A Parasitic elements in the equivalent discharge circuit Figure 2A schematic diagram of the corresponding location of the 500A electrostatic discharge protection device. (See diagram below.) Figure 4A , Figure 4B As shown, in addition to the first parasitic diode D1, the equivalent discharge circuit where an electrostatic discharge event occurs between the input / output terminal IO and the ground terminal VSS also includes a first parasitic bipolar junction transistor (BJT) B1 (e.g., a parasitic PNP BJT) composed of a first P-type doped region P1, a first N-type deep well region DNW1, and a first P-type well region PW1. The emitter, base, and collector of the first parasitic bipolar junction transistor B1 are respectively composed of the first P-type doped region P1, the first N-type deep well region DNW1, and the first P-type well region PW1. The equivalent circuit also includes a second parasitic bipolar junction transistor B2 (e.g., a parasitic NPN BJT) composed of a third N-type doped region N3, a first P-type well region PW1, and a first N-type deep well region DNW1. The emitter, base, and collector of the second parasitic bipolar junction transistor B2 are respectively composed of a third N-type doped region N3, a first P-type well region PW1, and a first N-type deep well region DNW1. Furthermore, the base (first N-type deep well region DNW1) of the first parasitic bipolar junction transistor B1 is electrically connected to the collector (first N-type deep well region DNW1) of the second parasitic bipolar junction transistor B2, and the base (first P-type well region PW1) of the second parasitic bipolar junction transistor B2 is electrically connected to the collector (first P-type well region PW1) of the first parasitic bipolar junction transistor B1, thereby forming the first parasitic semiconductor controlled rectifier SCR-1. Furthermore, the emitter (first P-type doped region P1) of the first parasitic bipolar junction transistor B1 is electrically connected to the input / output terminal IO and the positive terminal of the first parasitic diode D1, and the base (first N-type deep well region DNW1) of the first parasitic bipolar junction transistor B1 is electrically connected to the negative terminal of the first parasitic diode D1. The emitter (third N-type doped region N3) of the second parasitic bipolar junction transistor B2 is electrically connected to the ground terminal VSS.

[0085] Figure 4A The equivalent circuit of switching circuit 300 is also shown. Switching circuit 300 is composed of a resistor-capacitor sensor (RC detector), which includes a resistor, a capacitor, an inverter, and an N-type metal-oxide-semiconductor transistor.

[0086] like Figure 4A , Figure 4BAs shown, when an electrostatic discharge (ESD) event occurs between the input / output terminal IO and the ground terminal VSS, a forward bias voltage is applied to the emitter (first P-type doped region P1)-base (first N-type deep well region DNW1) junction of the first parasitic diode D1 and the first parasitic bipolar junction transistor B1, triggering them to conduct. This forms a current path from the input / output terminal IO through the emitter (first P-type doped region P1)-base (first N-type deep well region DNW1) junction of the first parasitic bipolar junction transistor B1 and to the switching circuit 300, triggering the first parasitic bipolar junction transistor B1 to conduct. This causes the switching circuit 300 to output a high level to the third P-type doped region P3 (which is switched to the power supply terminal VCC), and this high level is higher than the ground terminal VSS ground level. Furthermore, the switching circuit 300 is electrically connected to the base (first P-type well region PW1) of the second parasitic bipolar junction transistor B2 via wire 210. Therefore, when the high level output by the switching circuit 300 is higher than the ground level of the ground terminal VSS, a current path is formed through wire 210, applying a forward bias voltage to the base (first P-type well region PW1)-emitter (third N-type doped region N3) junction of the second parasitic bipolar junction transistor B2, triggering the second parasitic bipolar junction transistor B2 to conduct. Since the first parasitic bipolar junction transistor B1 and the second parasitic bipolar junction transistor B2 are triggered to conduct together, the first parasitic semiconductor controlled rectifier SCR-1 is triggered to conduct, forming a current path. The aforementioned current path provides a trigger current (start-up current), which in turn triggers the first parasitic bipolar junction transistor B1 (PNP) and the second parasitic bipolar junction transistor B2 (NPN) to form a first parasitic semiconductor controlled rectifier SCR-1. This first parasitic semiconductor controlled rectifier SCR-1, with its low holding voltage (VHold) and low resistance (R), can provide a current path from the input / output terminal IO to the ground terminal VSS, discharging static charge away from the protected circuit.

[0087] When the protected components in the system are operating normally (without an electrostatic discharge event), the third P-type doped region P3 is switched to the ground terminal VSS. The base (first P-type well region PW1)-emitter (third N-type doped region N3) junction of the second parasitic bipolar junction transistor B2 has no forward bias, therefore, the second parasitic bipolar junction transistor B2 will not be triggered to conduct. Furthermore, the first N-type deep well region DNW1 is connected to the power supply terminal VCC, which is the highest potential in the entire system. Therefore, the emitter (first P-type doped region P1)-base (first N-type deep well region DNW1) junction of the first parasitic bipolar junction transistor B1 has no forward bias, therefore, the first parasitic bipolar junction transistor B1 will not be triggered to conduct. Since neither the first parasitic bipolar junction transistor B1 nor the second parasitic bipolar junction transistor B2 is triggered to conduct, the first parasitic semiconductor control rectifier SCR-1 will also not be triggered to conduct, and no leakage / latch-up phenomenon will occur.

[0088] Figure 5A This indicates that an electrostatic discharge (ESD) event occurs in the equivalent discharge circuit between the power supply terminal VCC and the input / output (IO) terminals. Figure 5B show Figure 5A Parasitic elements in the equivalent circuit Figure 2 A schematic diagram of the corresponding location of the 500A electrostatic discharge protection device. (See diagram below.) Figure 5A , Figure 5BAs shown, in addition to the first parasitic diode D1 and the second parasitic diode D2, the equivalent circuit also includes a third parasitic diode D3 composed of a second P-type doped region P2 and a second N-type deep well region DNW2, and a third parasitic bipolar junction transistor B3 (e.g., a parasitic PNP BJT) composed of a second P-type doped region P2, a second N-type deep well region DNW2, and a second P-type well region PW2. The emitter, base, and collector of the third parasitic bipolar junction transistor B3 are respectively composed of a second P-type doped region P2, a second N-type deep well region DNW2, and a second P-type well region PW2. The equivalent circuit also includes a fourth parasitic bipolar junction transistor B4 (e.g., a parasitic NPN BJT) composed of a fourth N-type doped region N4, a second P-type well region PW2, and a second N-type deep well region DNW2. The emitter, base, and collector of the fourth parasitic bipolar junction transistor B4 are respectively composed of a fourth N-type doped region N4, a second P-type well region PW2, and a second N-type deep well region DNW2. Furthermore, the base (second N-type deep well region DNW2) of the third parasitic bipolar junction transistor B3 is electrically connected to the collector (second N-type deep well region DNW2) of the fourth parasitic bipolar junction transistor B4, and the base (second P-type well region PW2) of the fourth parasitic bipolar junction transistor B4 is electrically connected to the collector (second P-type well region PW2) of the third parasitic bipolar junction transistor B3, thus forming the second parasitic semiconductor controlled rectifier SCR-2. Furthermore, the emitter (second P-type doped region P2) of the third parasitic bipolar junction transistor B3 is electrically connected to the power supply terminal VCC and the positive terminal of the third parasitic diode D3, and the base (second N-type deep well region DNW2) of the third parasitic bipolar junction transistor B3 is electrically connected to the negative terminal of the third parasitic diode D3. The emitter (fourth N-type doped region N4) of the fourth parasitic bipolar junction transistor B4 is electrically connected to the input / output terminal IO and the negative terminal of the second parasitic diode D2, and the base (second P-type well region PW2) of the fourth parasitic bipolar junction transistor B4 is electrically connected to the positive terminal of the second parasitic diode D2.

[0089] like Figure 5A , Figure 5BAs shown, when an electrostatic discharge (ESD) event occurs between the power supply terminal VCC and the input / output terminal IO, the ESD current flows through the switching circuit 300 and forms a current path through the resistor-capacitor sensor (RC detector) to output a low level for the second N-type doped region N2 (which is now switched to be electrically connected to the ground terminal VSS). This low level is lower than the voltage level of the power supply terminal VCC. Furthermore, the switching circuit 300 forms a current path by electrically connecting the base (second N-type deep well region DNW2) of the third parasitic bipolar junction transistor B3 via wire 220. Therefore, when the low level output by the switching circuit 300 is lower than the level of the power supply terminal VCC, a forward bias voltage is applied to the emitter (second P-type doped region P2)-base (second N-type deep well region DNW2) junction of the third parasitic bipolar junction transistor B3, triggering the third parasitic bipolar junction transistor B3 to conduct. Additionally, the electrostatic discharge current flows through the switching circuit 300 and forms a current path through the resistor-capacitor sensor (RC detector), outputting a high level at the gate of the N-type metal-oxide-semiconductor transistor (NMOS) 302. This high level is higher than the ground level of the ground terminal VSS, causing the NMOS 302 to conduct and forming a current path to the ground terminal VSS. It also applies a forward bias voltage to the base (second P-type well region PW2)-emitter (fourth N-type doped region N4) junction of the second parasitic diode D2 and the fourth parasitic bipolar junction transistor B4, triggering the fourth parasitic bipolar junction transistor B4 to conduct. Since the third parasitic bipolar junction transistor B3 and the fourth parasitic bipolar junction transistor B4 are both triggered to conduct, the second parasitic semiconductor control rectifier SCR-2 is triggered to conduct, forming a current path to the input / output terminal IO. The aforementioned current path provides a trigger current (start-up current), which in turn triggers the third parasitic bipolar junction transistor B3 (PNP) and the fourth parasitic bipolar junction transistor B4 (NPN) to form a second parasitic semiconductor controlled rectifier SCR-2. This second parasitic semiconductor controlled rectifier SCR-2, with its low holding voltage (VHold) and low resistance (R), can provide a current path from the power supply terminal VCC to the input / output terminal IO, discharging static charge away from the protected circuit.

[0090] When the protected components in the system are operating normally (without an electrostatic discharge event), the second N-type doped region N2 is switched to the power supply terminal VCC. The emitter (second P-type doped region P2)-base (second N-type deep well region DNW2) junction of the third parasitic bipolar junction transistor B3 has no forward bias, therefore, the third parasitic bipolar junction transistor B3 will not be triggered to conduct. Furthermore, the second P-type well region PW2 is connected to the ground terminal VSS, which is the lowest potential in the entire system. Therefore, the base (second P-type well region PW2)-emitter (fourth N-type doped region N4) junction of the fourth parasitic bipolar junction transistor B4 has no forward bias, therefore, the fourth parasitic bipolar junction transistor B4 will not be triggered to conduct. Since neither the third parasitic bipolar junction transistor B3 nor the fourth parasitic bipolar junction transistor B4 is triggered to conduct, the second parasitic semiconductor control rectifier SCR-2 will also not be triggered to conduct, and no leakage / latch-up phenomenon will occur.

[0091] Figures 6-10 Show corresponding Figure 2 Partial cross-sectional schematic diagrams of electrostatic discharge protection devices 500B to 500F according to some embodiments of the present invention, in regions 510 and 520. Figure 6 As shown, compared to the electrostatic discharge protection device 500A, the electrostatic discharge protection device 500B further includes a first gate structure G1 and / or a second gate structure G2, and a sixth P-type doped region P6 and / or a sixth N-type doped region N6. The first gate structure G1 is disposed on the P-type semiconductor substrate 200 within the first N-type deep well region DNW1, and partially overlaps with the first P-type doped region P1 and the sixth P-type doped region P6 disposed within the first N-type deep well region DNW1. In some embodiments, the sixth P-type doped region P6 is electrically connected to the power supply terminal VCC. Therefore, the first gate structure G1, the first P-type doped region P1 in the first N-type deep well region DNW1, and the sixth P-type doped region P6 can constitute a first P-type metal-oxide-semiconductor transistor PM1. In some embodiments, the first P-type doped region P1 of the first P-type metal-oxide-semiconductor transistor PM1 can form a parasitic diode with the first N-type doped region N1, which is equivalent to a first parasitic diode D1. Figure 6 The left half (including the parasitic first parasitic diode D1, the first parasitic bipolar junction transistor B1, and the second parasitic bipolar junction transistor B2) will produce the following: Figures 4A-4B Its effects.

[0092] like Figure 6As shown, the second gate structure G2 is disposed on the P-type semiconductor substrate 200 within the second P-type well region PW2, and partially overlaps with the fourth N-type doped region N4 and the sixth N-type doped region N6 disposed within the second P-type deep well region PW2. In some embodiments, the sixth N-type doped region N6 is electrically connected to the ground terminal VSS. Therefore, the second gate structure G2, the fourth N-type doped region N4, and the sixth N-type doped region N6 in the second P-type well region PW2 can constitute a first N-type metal-oxide-semiconductor transistor NM1. In some embodiments, the fourth N-type doped region N4 of the first N-type metal-oxide-semiconductor transistor NM1 can form a parasitic diode with the second P-type well region PW2, which is equivalent to the second parasitic diode D2. Figure 6 The right half (containing the parasitic second parasitic diode D2, the third parasitic bipolar junction transistor B3, and the fourth parasitic bipolar junction transistor B4) will produce the following: Figures 5A-5B Its effects.

[0093] like Figure 7 As shown, compared to the electrostatic discharge protection device 500A, the electrostatic discharge protection device 500C further includes a third gate structure G3 and / or a fourth gate structure G4, and a seventh P-type doped region P7 and / or a seventh N-type doped region N7. The third gate structure G3 is disposed on the P-type semiconductor substrate 200 within the first P-type well region PW1, and partially overlaps with the third P-type doped region P3 and the seventh N-type doped region N7 disposed in the first P-type well region PW1. In some embodiments, the third gate structure G3 is electrically connected to the power supply terminal VCC, and the seventh N-type doped region N7 is electrically connected to the ground terminal VSS. Therefore, the first capacitor C1 of the electrostatic discharge protection device 500C has the function of stabilizing the voltage between the power supply terminal VCC and the ground terminal VSS. Under normal conditions, the switching circuit 300 outputs a low-level voltage (VSS) to the third P-type doped region P3, so in this case, the first capacitor C1 still has the voltage regulation function of a general capacitor. However, when an electrostatic discharge event occurs, the switching circuit 300 outputs a high-level voltage (VCC) to the third P-type doped region P3, triggering the second parasitic bipolar junction transistor B2 (NPN), and forming the first parasitic semiconductor controlled rectifier SCR-1 with the corresponding first parasitic bipolar junction transistor B1 (PNP). Figure 4A ).

[0094] like Figure 7As shown, the fourth gate structure G4 is disposed on the P-type semiconductor substrate 200 within the second N-type deep well region DNW2, and partially overlaps with the second N-type doped region N2 and the seventh P-type doped region P7 disposed within the second N-type deep well region DNW2. In some embodiments, the fourth gate structure G4 is electrically connected to the ground terminal VSS, and the seventh P-type doped region P7 is electrically connected to the power supply terminal VCC. Therefore, the second capacitor C2 of the electrostatic discharge protection device 500C has the function of stabilizing the voltage between the power supply terminal VCC and the ground terminal VSS. Under normal conditions, the switching circuit 300 outputs a high-level voltage (VCC) to N2, so in this case, the second capacitor C2 still has the voltage regulation function of a general capacitor. However, when an electrostatic discharge event occurs, the switching circuit 300 outputs a low-level voltage (VSS) to N2, triggering the third parasitic bipolar junction transistor B3 (PNP), and forming a second parasitic semiconductor controlled rectifier SCR-2 with the corresponding fourth parasitic bipolar junction transistor B4 (NPN). Figure 5A ).

[0095] In some embodiments, when the operating voltage of the input / output terminal IO is lower than 1V, the third P-type doped region P3 and the second N-type doped region N2 can be directly interconnected by a wire without being electrically connected to the switching circuit 300. Figure 2 ).like Figure 8 As shown, compared to the electrostatic discharge protection device 500A, the electrostatic discharge protection device 500D also includes a wire 230. The wire 230 is disposed above the P-type semiconductor substrate 200. Furthermore, the two ends of the wire 230 are directly electrically connected to the third P-type doped region P3 and the second N-type doped region N2, respectively. When the current pulse of an electrostatic discharge event causes the voltage difference between the power supply terminal VCC and the ground terminal VSS to be greater than 1.2V, the second N-type doped region N2 will send out current and trigger the emitter (second P-type doped region P2)-base (second N-type deep well region DNW2) junction of the third parasitic bipolar junction transistor B3 to conduct. The third P-type doped region P3 receives current through wire 230, triggering the base (first P-type well region PW1)-emitter (third N-type doped region N3) junction of the second parasitic bipolar junction transistor B2 to conduct, thereby triggering the first parasitic semiconductor controlled rectifier SCR-1 and the second parasitic semiconductor controlled rectifier SCR-2 to conduct, and discharging static charge away from the protected circuit.

[0096] In some embodiments, when the operating voltage of the input / output terminal IO is between 1.0V and 1.2V, the third P-type doped region P3 and the second N-type doped region N2 can be directly interconnected by diodes without being electrically connected to the switching circuit 300. Figure 2 ).like Figure 9As shown, compared to the electrostatic discharge protection device 500A, the electrostatic discharge protection device 500E further includes a fourth diode D4. The fourth diode D4 is disposed above the P-type semiconductor substrate 200. Furthermore, the positive and negative terminals of the fourth diode D4 are electrically connected to the second N-type doped region N2 and the third P-type doped region P3, respectively. In some embodiments, when the current pulse of an electrostatic discharge event causes the voltage difference between the power supply terminal VCC and the ground terminal VSS to exceed 1.8V, the second N-type doped region N2 will send out current, triggering the emitter (second P-type doped region P2)-base (second N-type deep well region DNW2) junction of the third parasitic bipolar junction transistor B3 to conduct. The third P-type doped region P3 receives current through the fourth diode D4, triggering the base (first P-type well region PW1)-emitter (third N-type doped region N3) junction of the second parasitic bipolar junction transistor B2 to conduct. This, in turn, triggers the first parasitic semiconductor controlled rectifier SCR-1 and the second parasitic semiconductor controlled rectifier SCR-2 to conduct, discharging static charge away from the protected circuit. In some other embodiments, if the normal operating voltage of the input / output terminal IO is higher than 1.2V, the third P-type doped region P3 and the second N-type doped region N2 can be interconnected by multiple diodes connected in series.

[0097] In some embodiments, if the normal operating voltage of the input / output terminal IO is higher than 1.2V, the third P-type doped region P3 and the second N-type doped region N2 can be electrically interconnected with the detection circuit through the N-type metal-oxide-semiconductor transistor NM2 without being electrically connected to the switching circuit 300. Figure 2 ).like Figure 10 As shown, compared to the electrostatic discharge protection device 500A, the electrostatic discharge protection device 500F further includes a second N-type metal-oxide-semiconductor transistor NM2 and a detection circuit 300A composed of a resistance-capacitance sensor. The second N-type metal-oxide-semiconductor transistor NM2 has a base BT, a gate GT, a first source / drain SDT1, and a second source / drain SDT2. In some embodiments, the base BT is electrically connected to the ground terminal VSS, the gate GT is electrically connected to the detection circuit 300A, the first source / drain SDT1 is electrically connected to the third P-type doped region P3, and the second source / drain SDT2 is electrically connected to the second N-type doped region N2. In some embodiments, the detection circuit 300A is composed of a resistance-capacitance sensor (RC detector), which includes a resistor, a capacitor, an inverter, and an N-type metal-oxide-semiconductor transistor.

[0098] When an electrostatic discharge (ESD) event occurs at the input / output (IO) terminal and the ground terminal (VSS) receives a ground level, the inverter in the detection circuit 300A outputs a high level, turning on the N-channel of the second N-type metal-oxide-semiconductor transistor (NM2), thus forming a path between the second N-type doped region N2 and the third P-type doped region P3. The second N-type doped region N2 sends out current, triggering the emitter (second P-type doped region P2)-base (second N-type deep well region DNW2) junction of the third parasitic bipolar junction transistor (B3) to conduct. The third P-type doped region P3 receives current from the second N-type metal-oxide-semiconductor transistor NM2, triggering the base (first P-type well region PW1)-emitter (third N-type doped region N3) junction of the second parasitic bipolar junction transistor B2 to conduct, thereby triggering the first parasitic semiconductor controlled rectifier (SCR-1) and the second parasitic semiconductor controlled rectifier (SCR-2) to conduct, discharging the electrostatic charge away from the protected circuit.

[0099] This invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes functional guard ring structures respectively disposed in two N-type deep well regions. These two functional guard ring structures are electrically connected to a functional circuit composed of a resistance-capacitance sensor (RC detector). For ESD events occurring at any two terminals (input / output terminal IO, power supply terminal VCC, or ground terminal VSS), the device can guide static charge away from the protected circuit. When the protected circuit is operating normally or during an ESD event, the two functional guard ring structures switch to different potentials (levels) via the functional circuit as needed. During an ESD event, the parasitic semiconductor controlled rectifier in the functional guard ring structure is triggered to conduct, providing an additional discharge path. Furthermore, when the protected component is operating normally, the parasitic semiconductor controlled rectifier in the functional guard ring structure is less likely to be triggered to conduct, thus preventing latch-up. In some embodiments, the functional circuitry can be replaced by wires, diodes, N-type metal-oxide-semiconductor transistors, and detection circuitry composed of resistor-capacitor sensors, depending on the normal operating voltage conditions of different input / output terminals (IO).

[0100] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art to which this invention pertains can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of this invention should be defined by the appended claims.

Claims

1. An electrostatic discharge protection device, comprising: a P-type semiconductor substrate; a first N-type deep well region in the P-type semiconductor substrate; a first N-type doped region in the first N-type deep well region; a first P-type doped region in the first N-type deep well region and disposed side by side and spaced apart from the first N-type doped region; a second N-type deep well region in the P-type semiconductor substrate and disposed side by side and spaced apart from the first N-type deep well region; a second N-type doped region in the second N-type deep well region; a second P-type doped region in the second N-type deep well region and disposed side by side and spaced apart from the second N-type doped region; a first P-type well region in the first N-type deep well region; a third N-type doped region in the first P-type well region; a third P-type doped region in the first P-type well region and disposed side by side and spaced apart from the third N-type doped region; a second P-type well region in the second N-type deep well region; a fourth N-type doped region in the second P-type well region; and a fourth P-type doped region in the second P-type well region and disposed side by side and spaced apart from the fourth N-type doped region; wherein the first P-type doped region and the fourth N-type doped region are electrically connected to an input / output terminal, wherein the first N-type doped region and the second P-type doped region are electrically connected to a power supply terminal, wherein the third N-type doped region and the fourth P-type doped region are electrically connected to a ground terminal.

2. The electrostatic discharge protection device of claim 1, further comprising: a first guard ring in the P-type semiconductor substrate and surrounding the first N-type deep well region and the second N-type deep well region, respectively, wherein the first guard ring comprises: a third P-type well region; and a fifth P-type doped region in the third P-type well region; and a second guard ring in the P-type semiconductor substrate and surrounding the first guard ring, wherein the second guard ring comprises: a first N-type well region; and a fifth N-type doped region in the first N-type well region.

3. The electrostatic discharge protection device of claim 2, wherein the fifth P-type doped region is electrically connected to the ground terminal.

4. The electrostatic discharge protection device of claim 2, wherein the fifth N-type doped region is electrically connected to the power supply terminal.

5. The electrostatic discharge protection device of claim 1, wherein the third P-type doped region and the second N-type doped region are electrically connected to a switching circuit.

6. The electrostatic discharge protection device of claim 5, wherein when an electrostatic discharge event occurs between the input / output terminal, the power supply terminal, or the ground terminal, the third P-type doped region is electrically connected to the power supply terminal and the second N-type doped region is electrically connected to the ground terminal.

7. The electrostatic discharge protection device of claim 6, wherein the first P-type doped region, the first N-type deep well region, and the first N-type doped region form a first parasitic diode, wherein the fourth P-type doped region, the second P-type well region, and the fourth N-type doped region form a second parasitic diode.

8. The electrostatic discharge protection device of claim 7, wherein when an electrostatic discharge event occurs between the input / output terminal and the power supply terminal, the first parasitic diode is triggered on. ​ 9. The ESD protection device of claim 7, wherein the second parasitic diode is triggered on when an ESD event occurs between the ground terminal and the input / output terminal.

10. The ESD protection device of claim 7, wherein: the first P-type doped region, the first N-type deep well region, and the first P-type well region form a first parasitic bipolar junction transistor, the third N-type doped region, the first P-type well region, and the first N-type deep well region form a second parasitic bipolar junction transistor, a base of the first parasitic bipolar junction transistor is electrically connected to a collector of the second parasitic bipolar junction transistor, a base of the second parasitic bipolar junction transistor is electrically connected to a collector of the first parasitic bipolar junction transistor to form a first parasitic semiconductor controlled rectifier, an emitter of the first parasitic bipolar junction transistor is electrically connected to the input / output terminal and a positive terminal of the first parasitic diode, the base of the first parasitic bipolar junction transistor is electrically connected to a negative terminal of the first parasitic diode, and an emitter of the second parasitic bipolar junction transistor is electrically connected to the ground terminal.

11. The ESD protection device of claim 10, wherein when an ESD event occurs between the input / output terminal and the ground terminal, the first parasitic diode and the first parasitic bipolar junction transistor are triggered on, and the switching circuit outputs a high level to the third P-type doped region, the high level being higher than a ground level of the ground terminal, to trigger on the second parasitic bipolar junction transistor, thereby triggering on the first parasitic semiconductor controlled rectifier.

12. The ESD protection device of claim 7, wherein: the second P-type doped region and the second N-type deep well region form a third parasitic diode, the second P-type doped region, the second N-type deep well region, and the second P-type well region form a third parasitic bipolar junction transistor, the fourth N-type doped region, the second P-type well region, and the second N-type deep well region form a fourth parasitic bipolar junction transistor, a base of the third parasitic bipolar junction transistor is electrically connected to a collector of the fourth parasitic bipolar junction transistor, a base of the fourth parasitic bipolar junction transistor is electrically connected to a collector of the third parasitic bipolar junction transistor to form a second parasitic semiconductor controlled rectifier, an emitter of the third parasitic bipolar junction transistor is electrically connected to the power supply terminal and a positive terminal of the third parasitic diode, the base of the third parasitic bipolar junction transistor is electrically connected to a negative terminal of the third parasitic diode, an emitter of the fourth parasitic bipolar junction transistor is electrically connected to the input / output terminal and a negative terminal of the second parasitic diode, and the base of the fourth parasitic bipolar junction transistor is electrically connected to a positive terminal of the second parasitic diode.

11. The ESD protection device of claim 10, wherein when an ESD event occurs between the input / output terminal and the ground terminal, the first parasitic diode and the first parasitic bipolar junction transistor are triggered on, and the switching circuit outputs a high level to the third P-type doped region, the high level being higher than a ground level of the ground terminal, to trigger on the second parasitic bipolar junction transistor, thereby triggering on the first parasitic semiconductor controlled rectifier.

12. The ESD protection device of claim 7, wherein: the second P-type doped region and the second N-type deep well region form a third parasitic diode, the second P-type doped region, the second N-type deep well region, and the second P-type well region form a third parasitic bipolar junction transistor, the fourth N-type doped region, the second P-type well region, and the second N-type deep well region form a fourth parasitic bipolar junction transistor, a base of the third parasitic bipolar junction transistor is electrically connected to a collector of the fourth parasitic bipolar junction transistor, a base of the fourth parasitic bipolar junction transistor is electrically connected to a collector of the third parasitic bipolar junction transistor to form a second parasitic semiconductor controlled rectifier, an emitter of the third parasitic bipolar junction transistor is electrically connected to the power supply terminal and a positive terminal of the third parasitic diode, the base of the third parasitic bipolar junction transistor is electrically connected to a negative terminal of the third parasitic diode, an emitter of the fourth parasitic bipolar junction transistor is electrically connected to the input / output terminal and a negative terminal of the second parasitic diode, and the base of the fourth parasitic bipolar junction transistor is electrically connected to a positive terminal of the second parasitic diode. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 13. The ESD protection device of claim 12, wherein when an ESD event occurs between the power supply terminal and the input / output terminal, the switching circuit outputs a high level to the third P-type doped region and a low level to the second N-type doped region, the low level being lower than the high level, so that the third parasitic diode and the third parasitic bipolar junction transistor are triggered on, and the second parasitic diode and the fourth parasitic bipolar junction transistor are triggered on, thereby triggering the second parasitic semiconductor-controlled rectifier to be on.

14. The ESD protection device of claim 1, further comprising: a first gate structure disposed on the P-type semiconductor substrate within the first N-type deep well region and partially overlapping the first P-type doped region and a sixth P-type doped region disposed in the first N-type deep well region, wherein the sixth P-type doped region is electrically connected to a power supply terminal, wherein the first gate structure, the first P-type doped region and the sixth P-type doped region form a first P-type metal oxide semiconductor transistor.

15. The ESD protection device of claim 1, further comprising: a second gate structure disposed on the P-type semiconductor substrate within the second P-type well region and partially overlapping the fourth N-type doped region and a sixth N-type doped region disposed in the second P-type well region, wherein the sixth N-type doped region is electrically connected to a ground terminal, wherein the second gate structure, the fourth N-type doped region and the sixth N-type doped region form a first N-type metal oxide semiconductor transistor.

16. The ESD protection device of claim 1, further comprising: a third gate structure disposed on the P-type semiconductor substrate within the first P-type well region and partially overlapping the third P-type doped region and a seventh N-type doped region disposed in the first P-type well region, wherein the third gate structure is electrically connected to the power supply terminal and the seventh N-type doped region is electrically connected to the ground terminal, wherein the third gate structure, the third P-type doped region and the seventh N-type doped region form a first capacitor.

17. The ESD protection device of claim 1, further comprising: a fourth gate structure disposed on the P-type semiconductor substrate within the second N-type deep well region and partially overlapping the second N-type doped region and a seventh P-type doped region disposed in the second N-type deep well region, wherein the fourth gate structure is electrically connected to the ground terminal and the seventh P-type doped region is electrically connected to the power supply terminal, wherein the fourth gate structure, the second N-type doped region and the seventh P-type doped region form a second capacitor.

18. The ESD protection device of claim 1, further comprising: a wire disposed above the P-type semiconductor substrate, wherein two ends of the wire are directly electrically connected to the third P-type doped region and the second N-type doped region, respectively.

19. The ESD protection device of claim 1, further comprising: a fourth diode disposed above the P-type semiconductor substrate, wherein an anode and a cathode of the fourth diode are electrically connected to the second N-type doped region and the third P-type doped region, respectively.

20. The ESD protection device of claim 1, further comprising: A second N-type metal oxide semiconductor transistor has a base, a gate, a first source / drain, and a second source / drain; and a detection circuit, wherein the base is electrically connected to the ground terminal, wherein the gate is electrically connected to the detection circuit, the first source / drain is electrically connected to the third P-type doped region, and the second source / drain is electrically connected to the second N-type doped region.

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