Filtering circuit and polyphase filter

Abstract

The present invention provides a filter circuit and a polyphase filter that can greatly improve the noise, power loss, and mismatch of the polyphase filter. In one embodiment, a filter circuit provided by the present invention can include a polyphase filter and a quadrature phase detector, wherein the polyphase filter includes a first path configured to receive a first input signal to generate a first clock signal, a second path including a first adjustable delay circuit configured to receive the first input signal to generate a second clock signal, a third path including a second adjustable delay circuit configured to receive the second input signal to generate a third clock signal, and a fourth path configured to receive the second input signal to generate a fourth clock signal, and wherein the quadrature phase detector is configured to detect phases of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to generate a control signal to control the first adjustable delay circuit and the second adjustable delay circuit.

Claims

1. A filter circuit, characterized in that, It includes a polyphase filter and a quadrature phase detector, wherein the polyphase filter includes: The first path is configured to receive a first input signal to generate a first clock signal; The second path includes a first adjustable delay circuit configured to receive the first input signal to generate a second clock signal, wherein the first adjustable delay circuit is coupled to the first input signal and a second input signal, and the first input signal and the second input signal are differential signals. The third path includes a second adjustable delay circuit configured to receive the second input signal to generate a third clock signal, wherein the second adjustable delay circuit is coupled to the first input signal and the second input signal; The fourth path is configured to receive the second input signal to generate a fourth clock signal; The quadrature phase detector is configured to detect the phases of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit. The quadrature phase detector detects the phases of the first clock signal, the second clock signal, and the fourth clock signal to generate a first control signal to control the first adjustable delay circuit.

2. The filter circuit as described in claim 1, characterized in that, The first path does not have any adjustable delay circuit, and the fourth path does not have any adjustable delay circuit.

3. The filter circuit as described in claim 1, characterized in that, The first adjustable delay circuit includes a first pole and a second pole. The first adjustable delay circuit receives the first input signal at the first pole and outputs the second clock signal at the second pole. The second pole of the first adjustable delay circuit is coupled to the second input signal through a first capacitor.

4. The filter circuit as described in claim 3, characterized in that, The second pole of the first adjustable delay circuit outputs the second clock signal through a buffer.

5. The filter circuit as described in claim 1, characterized in that, The second adjustable delay circuit includes a first pole and a second pole. The second adjustable delay circuit receives the second input signal at the first pole and outputs the third clock signal at the second pole. The second pole of the second adjustable delay circuit is coupled to the first input signal through a second capacitor.

6. The filter circuit as described in claim 5, characterized in that, The second pole of the second adjustable delay circuit outputs the third clock signal through a buffer.

7. The filter circuit as described in claim 1, characterized in that, The quadrature phase detector detects the phases of the first clock signal, the third clock signal, and the fourth clock signal to generate a second control signal to control the second adjustable delay circuit.

8. The filter circuit as described in claim 1, characterized in that, The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal correspond to phases of 0 degrees, 90 degrees, 270 degrees, and 180 degrees, respectively.

9. The filter circuit as described in claim 7, characterized in that, The orthogonal phase detector includes: The first detection circuit is configured to detect the phase difference between the first clock signal and the second clock signal to generate a first detection result; The second detection circuit is configured to detect the phase difference between the second clock signal and the fourth clock signal to generate a second detection result; The third detection circuit is configured to detect the phase difference between the third clock signal and the fourth clock signal to generate a third detection result; The fourth detection circuit is configured to detect the phase difference between the third clock signal and the first clock signal to generate a fourth detection result; A first comparator is configured to compare the first detection result and the second detection result to generate the first control signal; and The second comparator is configured to compare the third detection result and the fourth detection result to generate the second control signal.

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