A switch connection method for ADC sampling circuit and its circuit and chip

Abstract

The present invention relates to a switch connection method for an ADC sampling circuit, as well as its circuit and chip. The method samples first and then compares. In the sampling phase, the output end of the DAC circuit is connected to a reference voltage VCM via a switch A1 controlled by a sampling control signal, and is connected to the positive end of a comparator. The negative end of the comparator is connected to the output end of the DAC circuit via a switch A2 controlled by a sampling control signal. At this time, the voltage value of the positive end of the comparator is equal to the voltage value of the output end of the DAC circuit and equal to the voltage value of the negative end, ensuring that the voltage values ​​input to the positive and negative ends of the comparator during the sampling phase are equal. In the comparison phase, the negative end of the comparator is connected to the reference voltage VCM via a switch B1 controlled by a comparison control signal, and is compared with the input signal VIN collected at the positive end. The present invention ensures that the voltage values ​​at the positive and negative ends of the comparator are always equal during sampling, reduces the offset error in the sampling circuit, and prevents erroneous flipping, thereby improving the performance of the sampling circuit.

Description

Technical Field

[0001] The present invention relates to a switch connection method for an ADC sampling circuit in the field of integrated circuit design, as well as a circuit and chip thereof. Specifically, it relates to a circuit switch connection method suitable for reducing offset error in an ADC sampling circuit, an ADC sampling circuit sampling the method, and an ADC sampling circuit chip encapsulated by sampling the ADC sampling circuit. Background Art

[0002] ADC, short for analog-to-digital converter, is widely used in consumer electronics, automotive, wireless and wired communications, military and aerospace industries, and other fields, making it an indispensable part of high-tech modern life. ADC circuit offset error affects ADC performance, and reducing it is an effective way to improve ADC performance.

[0003] Offset error in ADC circuits often occurs during the sampling phase, causing the voltage values ​​at the positive and negative terminals of the comparator to be unequal, affecting the accuracy of the comparator and resulting in inaccurate comparator output results, thereby reducing the performance of the ADC circuit. Therefore, a circuit needs to be designed to offset or reduce the offset error.

[0004] The input offset voltage of the comparator is an important factor affecting the accuracy of the comparator. The comparator precision affects the accuracy of the comparator, thus affecting the performance of the high-speed and high-precision ADC circuit. The accuracy of the comparator in the ADC circuit is affected by the input offset voltage. The method to eliminate the input offset voltage is: during the sampling phase, the voltage values ​​of the positive and negative terminals of the comparator are equal. The offset voltage is amplified by the pre-amplifier stage in the comparator structure and stored on the output coupling capacitor. It is then superimposed with the input of the comparison phase to eliminate the influence of the offset voltage, such as Figure 1 shown.

[0005] Figure 2 The figure shows the switch connection mode of the sampling and holding circuit in the traditional single-ended ADC circuit. Figure 2 The ADC sampling circuit includes a DAC circuit (such as a DAC circuit array), a bias circuit, a comparator, and an electronically controlled switch A1 controlled by a sampling control signal.

[0006] When a traditional single-ended ADC circuit samples, the DAC circuit output of the DAC array circuit is connected to the reference voltage VCM through switch A1 controlled by the sampling signal, and is also connected to the positive terminal of the comparator. The negative terminal of the comparator is directly connected to the reference voltage VCM. Since the reference VCM voltage is not a fixed voltage source, but is generated by the reference current IREF flowing through the bias circuit, the output terminal VCM of the bias circuit carries a weak current and the voltage of VCM also has certain small fluctuations, and is not completely fixed. During sampling, the current carried by the reference voltage VCM flows through the switch. Since the switch resistance is about a few hundred ohms, a small voltage is generated on the switch, resulting in unequal voltage values ​​at the positive and negative terminals of the comparator. The size of the switch resistance is inversely proportional to its area, so reducing the switch resistance will increase the switch area, resulting in an increase in the area of ​​the ADC circuit. At the end of sampling, the voltage values ​​at the positive and negative terminals of the comparator are unequal, and the small voltage difference affects the comparison stage. During comparison, switch A1 controlled by the sampling signal is disconnected, and the positive terminal of the comparator is connected to the output terminal of the DAC circuit. The collected input signal VIN is input, and the comparator The negative terminal remains connected to the reference voltage VCM, which will also introduce a fluctuating voltage error, which is superimposed on the voltage error introduced by the positive terminal of the comparator during sampling. Since the positive and negative terminal voltage values ​​of the comparator are different during the sampling phase, the offset voltages stored in the comparator for the positive and negative terminals are different. The offset cannot be eliminated during the comparison phase, which will have a certain impact on the accuracy of the comparator. For comparators with low precision, offset errors will be generated, reducing the performance of the ADC circuit. Comparators with very high precision requirements will output erroneous codes, affecting the actual results and failing to meet the performance requirements of high-speed and high-precision ADC circuits. Summary of the Invention

[0007] Based on this, the offset error caused by the sampling stage in the traditional single-ended ADC circuit is solved. The present invention provides a circuit switch connection method suitable for reducing the offset error in the ADC sampling circuit, an ADC sampling circuit sampling the method, and an ADC sampling circuit chip formed by encapsulating the ADC sampling circuit. The present invention ensures that the voltage values ​​of the positive and negative terminals of the comparator are always equal during sampling, reduces the offset error in the ADC circuit, and prevents the occurrence of erroneous flipping, thereby improving the performance of the ADC circuit.

[0008] The objective of the present invention is achieved through the following technical solution: a circuit switch connection method suitable for reducing offset error in an ADC sampling circuit, wherein the ADC sampling circuit includes a DAC circuit, a bias circuit, a comparator, and an electronically controlled switch A1 controlled by a sampling control signal; the circuit switch connection method includes the following steps:

[0009] Step 1: Provide electronically controlled switch A2 and electronically controlled switch B1, and add a comparison control signal;

[0010] Step 2: Design the ADC sampling circuit to meet the following operating conditions:

[0011] (1) In each sampling cycle of the ADC sampling circuit, the sampling phase is preceded by the comparison phase, and the sampling phase is also the reset phase of the comparison phase;

[0012] (2) During the sampling phase, the sampling control signal controls the electronically controlled switches A1 and A2 to be closed, and the comparison control signal controls the electronically controlled switch B1 to be open; the output end of the DAC circuit is connected to the positive end of the comparator, and receives the reference voltage VCM from the bias circuit through the switch A1 controlled by the sampling control signal, and is connected to the negative end of the comparator through the switch A2 controlled by the sampling control signal;

[0013] (3) In the comparison stage, the sampling control signal controls the electronically controlled switches A1 and A2 to be disconnected, and the comparison control signal controls the electronically controlled switch B1 to be closed; the negative terminal of the comparator receives the reference voltage VCM through the switch B1 controlled by the comparison control signal, and the positive terminal of the comparator is electrically connected to the output terminal of the DAC circuit.

[0014] The present invention also provides an ADC sampling circuit, which includes a DAC circuit, a bias circuit, a comparator, an electrically controlled switch A1, an electrically controlled switch A2, and an electrically controlled switch B1; one end of the DAC circuit serves as a signal input end of the entire ADC sampling circuit, and the other end of the DAC circuit is electrically connected to the positive end of the comparator circuit in a first aspect; the other end of the DAC circuit is electrically connected to one end of the electrically controlled switch A1 in a second aspect, and the other end of the electrically controlled switch A1 is electrically connected to one end of the bias circuit and one end of the electrically controlled switch B1; the other end of the bias circuit receives a reference current IREF, and the other end of the electrically controlled switch B1 is electrically connected to the negative end of the comparator; the other end of the DAC circuit is electrically connected to one end of the electrically controlled switch A2 in a third aspect, and the other end of the electrically controlled switch A2 is electrically connected to the negative end of the comparator; the electrically controlled switches A1 and A2 are both controlled to be turned on and off using a sampling control signal, and the electrically controlled switch B1 is controlled to be turned on and off using a comparison control signal;

[0015] When the ADC sampling circuit is running, the sampling phase is preceded by the comparison phase in the same processing cycle, and the sampling phase is also the reset phase of the comparison phase;

[0016] In the sampling phase, the sampling control signal controls the electronically controlled switches A1 and A2 to be closed, and the comparison control signal controls the electronically controlled switch B1 to be open;

[0017] In the comparison stage, the sampling control signal controls the electronically controlled switch A1 and the electronically controlled switch A2 to be opened, and the comparison control signal controls the electronically controlled switch B1 to be closed.

[0018] As a further improvement of the above solution, each electronically controlled switch is a bootstrap switch.

[0019] As a further improvement of the above solution, each electronically controlled switch adopts a transistor, and the gate of the transistor is used to receive a corresponding control signal.

[0020] As a further improvement of the above solution, the design type of the DAC circuit is charge type, voltage type or resistance-capacitance type.

[0021] As a further improvement of the above solution, the design type of the DAC circuit is a charge type of full capacitor array.

[0022] As a further improvement of the above solution, the DAC circuit includes multiple capacitors in parallel, one end of the multiple capacitors is converged and connected to the signal input end, and the other end of the multiple capacitors is converged and electrically connected to the positive end of the comparator.

[0023] As a further improvement of the above solution, the comparison circuit includes at least one level of comparator, and each level of comparator includes NMOS transistors M1 to M3 and PMOS transistors P1 to P2;

[0024] The gate of the NMOS transistor M1 serves as the positive terminal of the comparator; the source of the NMOS transistor M1 is electrically connected to the drain of the PMOS transistor P1 and serves as an output terminal OUTN1 of the comparator; the gate of the NMOS transistor M2 serves as the negative terminal of the comparator; the source of the NMOS transistor M2 is electrically connected to the drain of the PMOS transistor P2 and serves as another output terminal OUTP1 of the comparator; the drains of the NMOS transistors M1 and M2 are both electrically connected to the source of the NMOS transistor M3, the drain of the NMOS transistor M3 is electrically grounded, and the gate of the NMOS transistor M3 receives an enable signal Vb1; the sources of the PMOS transistors P1 and P2 both receive the voltage signal VDD, and the gates of the PMOS transistors P1 and P2 both receive the enable signal Vb2.

[0025] Preferably, the comparator includes a two-stage capacitor-coupled preamplifier and a subsequent latch. The preamplifier has two positive and negative input terminals, the positive input terminal is the positive terminal, and the negative input terminal is the negative terminal. When the positive terminal voltage value is greater than the negative terminal voltage value, the output terminal of the comparison circuit outputs 1, and when the positive terminal voltage value is less than the negative terminal voltage value, the output terminal of the comparison circuit outputs 0.

[0026] The present invention further provides an ADC sampling circuit chip, which is packaged using any of the above-mentioned ADC sampling circuits, and the chip includes the following pins:

[0027] Pin 1 is used to receive the input signal VIN;

[0028] Pin 2 is used to receive the reference current IREF;

[0029] Pin three is used to receive sampling control signal;

[0030] Pin 4 is used to receive the comparison control signal;

[0031] Pin 5 is used for output signal OUT;

[0032] Pin six is ​​used for electrical grounding;

[0033] Pin seven, used to receive voltage signal VDD;

[0034] Pin 8, used to receive the enable signal Vb1;

[0035] Pin nine is used to receive an enable signal Vb2.

[0036] Compared with the traditional single-ended ADC circuit, the advantages of the present invention are:

[0037] During the sampling phase, the present invention adds a path connecting the output of the DAC circuit and the negative terminal of the comparator via a switch. This path ensures that the voltage values ​​at the positive and negative terminals of the comparator remain equal during sampling. During sampling in a traditional single-ended ADC circuit, the switch has an impedance of several hundred ohms, and the reference voltage VCM is generated by the reference current IREF flowing through the bias circuit, so the reference voltage VCM carries current. When the output of the DAC circuit is connected to the reference voltage VCM via the switch, a current path is formed from the input signal VIN, the DAC array circuit, the DAC output, the switch A1, and the reference voltage VCM. At this time, a small voltage is generated on the switch, resulting in the voltage value at the output of the DAC circuit being unequal to the voltage value of the reference voltage VCM. However, the negative terminal of the comparator is directly connected to the reference voltage VCM, resulting in the voltage values ​​at the positive and negative terminals of the comparator being unequal, with a small voltage difference. The present invention adds two switches, A2 and B1. During the sampling phase, switch A2, controlled by a sampling signal, connects the output of the DAC circuit to the negative terminal of the comparator. At this point, both the positive and negative terminals of the comparator are connected to the output of the DAC circuit, ensuring that the voltage values ​​of the positive and negative terminals of the comparator are always equal. Because the input signals to the positive and negative terminals of the comparator are connected via the transistor gates, which essentially generate no current, no current flows through the circuits connected to the positive and negative terminals of the comparator. Even if a small current flows, the input impedance of the transistor gates is infinite, and the impedance of switch A2 added to the gates will appear negligible. This ensures that the voltage values ​​of the positive and negative terminals of the comparator are equal. Furthermore, voltage fluctuations generated by the reference voltage VCM have a consistent effect on the positive and negative terminals of the comparator, further ensuring that the voltage values ​​of the positive and negative terminals of the comparator are equal. During the comparison phase, switches A1 and A2, controlled by the sampling signals, are opened, and switch B1, controlled by the comparison signal, is closed. The negative terminal of the comparator is connected to the reference voltage VCM via switch B1, controlled by the comparison signal, for comparison with the DAC output signal input to the positive terminal of the comparator.

[0038] The typical application scenario of this invention is for high-speed and high-precision ADC circuits, ensuring that the voltage values ​​at the positive and negative ends of the comparator are equal during the sampling phase, reducing or eliminating the impact of the input offset voltage on the accuracy of the comparator, thereby reducing the offset error in the ADC circuit and improving the accuracy of the ADC circuit.

[0039] In addition, the advantage of the circuit of the present invention is that the added "two-way switch" does not introduce additional errors and power consumption, which not only improves the accuracy of the circuit but also ensures the low power consumption requirement of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is the schematic diagram of the internal circuit of the comparator;

[0041] Figure 2 This is the schematic diagram of the switch connection method of the traditional ADC sampling circuit;

[0042] Figure 3 A circuit schematic diagram of a circuit switch connection method for reducing offset error in an ADC sampling circuit, provided in Example 1 of the present invention;

[0043] Figure 4 A circuit diagram of an ADC sampling circuit provided in Example 2 of the present invention;

[0044] Figure 5 2 is a comparison diagram of signal waveforms of a conventional switch connection method and the switch connection method of the present invention. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0046] Example 1

[0047] The present invention provides a circuit switch connection method suitable for reducing offset error in an ADC sampling circuit. In this embodiment, the ADC sampling circuit includes a DAC circuit, a bias circuit, a comparator, electronically controlled switches A1 and A2 controlled by a sampling control signal, and an electronically controlled switch B1 controlled by a comparison control signal. Figure 3 shown.

[0048] The circuit switch connection method comprises the following steps:

[0049] Step 1: Provide electronically controlled switch A2 and electronically controlled switch B1, and add a comparison control signal;

[0050] Step 2: Design the ADC sampling circuit to meet the following operating conditions:

[0051] (1) In each sampling cycle of the ADC sampling circuit, the sampling phase is preceded by the comparison phase, and the sampling phase is also the reset phase of the comparison phase;

[0052] (2) During the sampling phase, the sampling control signal controls the electronically controlled switches A1 and A2 to be closed, and the comparison control signal controls the electronically controlled switch B1 to be open; the output end of the DAC circuit is connected to the positive end of the comparator, and receives the reference voltage VCM from the bias circuit through the switch A1 controlled by the sampling control signal, and is connected to the negative end of the comparator through the switch A2 controlled by the sampling control signal;

[0053] (3) In the comparison stage, the sampling control signal controls the electronically controlled switches A1 and A2 to be disconnected, and the comparison control signal controls the electronically controlled switch B1 to be closed; the negative terminal of the comparator receives the reference voltage VCM through the switch B1 controlled by the comparison control signal, and the positive terminal of the comparator is electrically connected to the output terminal of the DAC circuit.

[0054] Please refer again Figure 3 The feature of the present invention is to add "two switches A2 and B1", which solves the problem of Figure 2 The offset error caused by the sampling phase in the traditional single-ended ADC circuit shown in the figure ensures that the voltage values ​​at the positive and negative terminals of the comparator are always equal during sampling, reducing the offset error in the ADC circuit and preventing false flipping, thereby improving the performance of the ADC circuit.

[0055] One end of the DAC circuit serves as the signal input end of the entire ADC sampling circuit, and the other end of the DAC circuit is electrically connected to the positive end of the comparator circuit. The other end of the DAC circuit is electrically connected to one end of an electronically controlled switch A1, and the other end of the electronically controlled switch A1 is electrically connected to one end of the bias circuit and one end of an electronically controlled switch B1. The other end of the bias circuit receives a reference current IREF, and the other end of the electronically controlled switch B1 is electrically connected to the negative end of the comparator. The other end of the DAC circuit is electrically connected to one end of an electronically controlled switch A2, and the other end of the electronically controlled switch A2 is electrically connected to the negative end of the comparator.

[0056] The output of the comparator serves as the signal output of the entire ADC sampling circuit. The output of the bias circuit serves as the reference voltage input of the entire ADC sampling circuit. The output of the bias circuit is electrically connected between the electronically controlled switch A1 and the electronically controlled switch B1. Both the electronically controlled switches A1 and A2 are turned on and off using a sampling control signal, while the electronically controlled switch B1 is turned on and off using a comparison control signal.

[0057] The ADC sampling circuit samples first, then compares. During sampling, electronically controlled switches A1 and A2, controlled by the sampling control signal, close, while electronically controlled switch B1, controlled by the comparison control signal, opens. The DAC circuit output is connected to the positive terminal of the comparator, electronically controlled switch A1, controlled by the sampling control signal, connects to the reference voltage VCM, and electronically controlled switch A2, controlled by the sampling control signal, connects to the negative terminal of the comparator. During comparison, electronically controlled switches A1 and A2, controlled by the sampling control signal, open, while electronically controlled switch B1, controlled by the comparison control signal, closes. The negative terminal of the comparator is connected to the reference voltage VCM via electronically controlled switch B1, controlled by the comparison control signal, for comparison with the DAC output signal input to the positive terminal of the comparator.

[0058] In summary, the present invention discloses a circuit switch connection method design suitable for reducing offset error in an ADC. The structure comprises a DAC array circuit, switches A1 and A2 controlled by sampling signals, switch B1 controlled by a comparison signal, a comparator, and a bias circuit for generating a reference voltage VCM. The implementation method is as follows: the circuit samples first and then compares. During the sampling phase, switches A1 and A2 controlled by the sampling signals are closed, and switch B1 controlled by the comparison signal is opened. The DAC circuit output of the DAC array circuit is connected to the reference voltage VCM via switch A1 controlled by the sampling signal and connected to the positive terminal of the comparator. The negative terminal of the comparator is connected to the DAC circuit output via switch A2 controlled by the sampling signal. At this time, the voltage value of the comparator's positive terminal is equal to the voltage value of the DAC circuit output and equal to the voltage value of the comparator's negative terminal, ensuring that the voltage values ​​input to the positive and negative terminals of the comparator are equal during the sampling phase. During the comparison phase, switches A1 and A2 controlled by the sampling signals are opened, and switch B1 controlled by the comparison signal is closed. The negative terminal of the comparator is connected to the reference voltage VCM via switch B1 controlled by the comparison signal and compared with the input signal VIN collected at the positive terminal.

[0059] When the positive terminal voltage value of the comparator is greater than the negative terminal voltage value, the comparator output terminal OUT outputs 1; when the positive terminal voltage value is less than the negative terminal voltage value, the comparator output terminal OUT outputs 0. The present invention provides a circuit switch connection method design suitable for reducing offset error in an ADC. This design not only improves the accuracy of the ADC circuit, but also meets the requirements of a small ADC circuit area and low power consumption, meeting the needs of the Internet of Things era.

[0060] Example 2

[0061] A specific embodiment of the present invention is Figure 4 As shown, the waveform diagram of the embodiment is as follows Figure 5 As shown, Figure 4 This is only one embodiment of the present invention, and is intended to facilitate understanding of the principles of the present invention, and does not represent the full scope of the present invention. Figure 4 The schematic diagram of the ADC circuit switch connection method shown consists of a charge DAC array circuit composed of four parallel capacitors, a comparator with vanishing modulation, a switch, and a bias circuit that generates the reference voltage VCM.

[0062] The design type of the DAC circuit can be a charge type, a voltage type, or a resistance-capacitance type, such as a charge type of a full capacitor array. In this embodiment, the DAC array circuit adopts a parallel form of four capacitors, the lower plate of the capacitor array is connected to the input signal VIN, the upper plate of the capacitor array is connected to the output end of the DAC circuit, and is directly connected to the positive end of the comparator. The electronically controlled switch A1 controlled by the sampling control signal is connected to the reference voltage VCM and the electronically controlled switch A2 controlled by the sampling control signal is connected to the negative end of the comparator. The negative end of the comparator is connected to the reference voltage VCM by the electronically controlled switch B1 controlled by the comparison control signal. Each electronically controlled switch can be a transistor, and the gate of the transistor is used to receive the corresponding control signal.

[0063] Each level of comparator includes NMOS transistors M1 to M3 and PMOS transistors P1 to P2. The gate of the NMOS transistor M1 serves as the positive terminal of the comparator. The source of the NMOS transistor M1 is electrically connected to the drain of the PMOS transistor P1 and serves as an output terminal OUTN1 of the comparator; the gate of the NMOS transistor M2 serves as the negative terminal of the comparator. The source of the NMOS transistor M2 is electrically connected to the drain of the PMOS transistor P2 and serves as another output terminal OUTP1 of the comparator. The drains of the NMOS transistors M1 and M2 are both electrically connected to the drain of the NMOS transistor M3, the source of the NMOS transistor M3 is electrically grounded, and the gate of the NMOS transistor M3 receives an enable signal Vb1. The sources of the PMOS transistors P1 and P2 both receive the voltage signal VDD, and the gates of the PMOS transistors P1 and P2 both receive the enable signal Vb2.

[0064] The comparator with vanishing modulation is mainly composed of a two-stage capacitor-coupled preamplifier followed by a latch. It has two input terminals, positive and negative. The positive input terminal is the positive terminal, and the negative input terminal is the negative terminal. When the positive terminal voltage value is greater than the negative terminal voltage value, the output terminal OUTP outputs 1. When the positive terminal voltage value is less than the negative terminal voltage value, the output terminal OUTN outputs 0.

[0065] The electronically controlled switch is selectively connected to the circuit. Compared with the traditional one, it is divided into an electronically controlled switch controlled by a sampling control signal and an electronically controlled switch controlled by a comparison control signal.

[0066] The bias circuit generates the reference voltage VCM. In the actual circuit, the reference voltage is not provided by a fixed voltage source, but is generated by the reference current IREF flowing through the bias circuit.

[0067] The present invention works as follows to reduce the offset error in the ADC circuit:

[0068] (1) The ADC sampling circuit samples first and then compares. During the sampling phase, the switch circuit is connected as follows: the electronically controlled switches A1 and A2 controlled by the sampling control signal are closed, and the electronically controlled switch B1 controlled by the comparison control signal is open. The lower plate of the capacitor array in the DAC array circuit is connected to the input signal VIN, and the upper plate is connected to the output of the DAC circuit. The output of the DAC circuit is connected to the positive terminal of the comparator, that is, the gate of the M1 transistor; the electronically controlled switch A1 controlled by the sampling control signal is connected to the reference voltage VCM; and the electronically controlled switch A2 controlled by the sampling control signal is connected to the negative terminal of the comparator, that is, the gate of the M2 transistor.

[0069] (2) Since the reference voltage VCM is generated by the reference current IREF flowing through the bias circuit, the reference voltage VCM will carry a small current, and the switch impedance is about several hundred ohms. When the DAC circuit output terminal is connected to the reference voltage VCM through the switch, a current path is formed from the input signal VIN, the DAC array circuit, the DAC output terminal, the electronically controlled switch A1 to the reference voltage VCM. At this time, a small voltage is generated on the switch, resulting in the voltage value of the DAC circuit output terminal being unequal to the voltage value of the reference voltage VCM; the input signals of the positive and negative terminals of the comparator are connected by the transistor gate, which basically does not generate current, ensuring that no current flows through the circuit connected to the positive and negative terminals of the comparator; even if there is a weak current flowing, the input impedance of the transistor gate is infinite, and the impedance value of the electronically controlled switch A2 added to the gate will appear insignificant, ensuring that the voltage values ​​of the positive and negative terminals of the comparator are equal, and the voltage fluctuation generated by the reference voltage VCM has the same effect on the positive and negative terminals of the comparator, further ensuring that the voltage values ​​of the positive and negative terminals of the comparator are equal. Moreover, the sampling phase of the DAC circuit is also the comparator reset phase. Therefore, the voltage values ​​of the positive and negative terminals of the comparator must be the same to effectively reduce the offset error of the ADC sampling circuit.

[0070] (3) After the above sampling phase is completed, the ADC sampling circuit enters the comparison phase. The switching circuit connection in the comparison phase is as follows: the electronically controlled switches A1 and A2 controlled by the sampling control signal are disconnected, and the electronically controlled switch B1 controlled by the comparison control signal is closed. The upper plate of the DAC circuit continues to be connected to the output of the DAC circuit and connected to the positive terminal of the comparator. The negative terminal of the comparator is connected to the reference voltage VCM through the electronically controlled switch B1 controlled by the comparison control signal. At this time, there is basically no current flowing through the path between the negative terminal of the comparator, i.e., the gate of the M2 transistor, the switch B1 controlled by the comparison control signal, and the reference voltage VCM. The voltage value of the negative terminal of the comparator is equal to the reference voltage VCM. The positive terminal of the comparator inputs the signal value of the DAC output terminal. The positive terminal voltage value and the negative terminal voltage value of the comparator are compared. When the positive terminal voltage value is greater than the negative terminal voltage value, the output terminal OUTP outputs 1. When the positive terminal voltage value is less than the negative terminal voltage value, the output terminal OUTP outputs 0. During the comparison, the lower plate of the capacitor in the DAC array circuit is disconnected by the switches S1, S2, S3, and S4 controlled by the sampling signal, and the input signal is no longer input.

[0071] Figure 4 This is just a simple embodiment of the present invention. Figure 4 The purpose of the present invention can be better understood. Figure 4 This is a charge-type DAC array circuit. While the figure depicts only an array of four parallel capacitors, the present invention is not limited to the type of DAC array circuit or the size of the array; the array can be reduced to a single device or increased to an infinite number of devices. The comparator can be a static, dynamic, or pre-amplified comparator circuit. The present invention employs a circuit switch connection method for reducing offset error in an ADC, ensuring that the voltages at the positive and negative terminals of the comparator are equal during the sampling phase. This reduces offset error and prevents erroneous coding, thereby ensuring the performance of the overall ADC circuit.

[0072] Example 3

[0073] This embodiment provides an ADC sampling circuit chip, which is a packaged version of the ADC sampling circuit described in Example 1. The ADC sampling circuit chip includes 10 pins: Pin 1 for receiving an input signal VIN; Pin 2 for receiving a reference current IREF; Pin 3 for receiving a sampling control signal; Pin 4 for receiving a comparison control signal; Pin 5 for receiving an output signal OUT; Pin 6 for electrical ground; Pin 7 for receiving a voltage signal VDD; Pin 8 for receiving an enable signal Vb1; and Pin 9 for receiving an enable signal Vb2. This embodiment, through its packaging as a chip, facilitates the promotion and application of the ADC sampling circuit.

[0074] It should be noted that the description of the above embodiment is only one possibility of the present invention. The purpose of the description is to facilitate a better understanding, and the above description should not be regarded as a limitation of the present invention. Those skilled in the art can create other embodiments without departing from the scope of the claims, which should also be within the scope of protection of the present invention. The terms involved in the above-mentioned embodiments are only set for the convenience of understanding and cannot be used as a limitation of the scope of the present invention. The terms can be defined according to actual needs without affecting the normal operation of the embodiment circuit. For example, the circuit of the above embodiment adopts a "charge-type" DAC array circuit, but it is equally applicable if it is changed to a voltage-type or a resistance-capacitance type.

[0075] The above is merely one specific embodiment of the present invention, and the scope of protection of the present invention is not limited thereto. Any person skilled in the art will appreciate that any substitution or variation that can be deduced within the scope of the claims presented herein is encompassed within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A circuit switch connection method for reducing offset error in an ADC sampling circuit, wherein the ADC sampling circuit includes a DAC circuit, a bias circuit, a comparator, and an electronically controlled switch A1 controlled by a sampling control signal; characterized in that: The circuit switch connection method comprises the following steps: Step 1: Provide electronically controlled switch A2 and electronically controlled switch B1, and add a comparison control signal; Step 2: Design the ADC sampling circuit to meet the following operating conditions: (1) In each sampling cycle of the ADC sampling circuit, the sampling phase is preceded by the comparison phase, and the sampling phase is also the reset phase of the comparison phase; (2) During the sampling phase, the sampling control signal controls the electronically controlled switches A1 and A2 to be closed, and the comparison control signal controls the electronically controlled switch B1 to be open; the output end of the DAC circuit is connected to the positive end of the comparator, and receives the reference voltage VCM from the bias circuit through the switch A1 controlled by the sampling control signal, and is connected to the negative end of the comparator through the switch A2 controlled by the sampling control signal; (3) In the comparison stage, the sampling control signal controls the electronically controlled switches A1 and A2 to be disconnected, and the comparison control signal controls the electronically controlled switch B1 to be closed; the negative terminal of the comparator receives the reference voltage VCM through the switch B1 controlled by the comparison control signal, and the positive terminal of the comparator is electrically connected to the output terminal of the DAC circuit.

2. An ADC sampling circuit, comprising a DAC circuit, a bias circuit, a comparator, and an electronically controlled switch A1; characterized in that: The ADC sampling circuit further includes an electronically controlled switch A2 and an electronically controlled switch B1; one end of the DAC circuit serves as a signal input end of the entire ADC sampling circuit, and the other end of the DAC circuit is electrically connected to the positive end of the comparator in a first aspect; the other end of the DAC circuit is electrically connected to one end of the electronically controlled switch A1 in a second aspect, and the other end of the electronically controlled switch A1 is electrically connected to one end of the bias circuit and one end of the electronically controlled switch B1, the other end of the bias circuit receives a reference current IREF, and the other end of the electronically controlled switch B1 is electrically connected to the negative end of the comparator; the other end of the DAC circuit is electrically connected to one end of the electronically controlled switch A2 in a third aspect, and the other end of the electronically controlled switch A2 is electrically connected to the negative end of the comparator; both the electronically controlled switches A1 and A2 are controlled to be turned on and off using a sampling control signal, and the electronically controlled switch B1 is controlled to be turned on and off using a comparison control signal; When the ADC sampling circuit is running, the sampling phase is preceded by the comparison phase in the same processing cycle, and the sampling phase is also the reset phase of the comparison phase; In the sampling phase, the sampling control signal controls the electronically controlled switch A1 and the electronically controlled switch A2 to be closed, and the comparison control signal controls the electronically controlled switch B1 to be open; In the comparison stage, the sampling control signal controls the electronically controlled switch A1 and the electronically controlled switch A2 to be opened, and the comparison control signal controls the electronically controlled switch B1 to be closed.

3. The ADC sampling circuit according to claim 2, wherein: Each electronically controlled switch is a bootstrap switch.

4. The ADC sampling circuit according to claim 2, wherein: Each electronically controlled switch uses a transistor, and a gate of the transistor is used to receive a corresponding control signal.

5. The ADC sampling circuit according to claim 2, wherein: The design type of the DAC circuit is charge type, voltage type or resistance-capacitance type.

6. The ADC sampling circuit according to claim 2, wherein: The design type of the DAC circuit is a charge type full capacitor array.

7. The ADC sampling circuit according to claim 6, wherein: The DAC circuit includes a plurality of capacitors connected in parallel, one end of the plurality of capacitors is converged and connected to the signal input end, and the other ends of the plurality of capacitors are converged and electrically connected to the positive end of the comparator.

8. The ADC sampling circuit according to claim 2, wherein: The comparator includes at least one level of comparator, and each level of comparator includes NMOS transistors M1-M3 and PMOS transistors P1-P2; The gate of the NMOS transistor M1 serves as the positive terminal of the comparator; the source of the NMOS transistor M1 is electrically connected to the drain of the PMOS transistor P1 and serves as an output terminal OUTN1 of the comparator; the gate of the NMOS transistor M2 serves as the negative terminal of the comparator; the source of the NMOS transistor M2 is electrically connected to the drain of the PMOS transistor P2 and serves as another output terminal OUTP1 of the comparator; the drains of the NMOS transistors M1 and M2 are both electrically connected to the source of the NMOS transistor M3, the drain of the NMOS transistor M3 is electrically grounded, and the gate of the NMOS transistor M3 receives an enable signal Vb1; the sources of the PMOS transistors P1 and P2 both receive the voltage signal VDD, and the gates of the PMOS transistors P1 and P2 both receive the enable signal Vb2.

9. The ADC sampling circuit according to claim 8, characterized in that: The comparator includes a two-stage capacitor-coupled preamplifier and a subsequent latch. The preamplifier has two input terminals, positive and negative, where the positive input terminal is the positive terminal and the negative input terminal is the negative terminal. When the positive terminal voltage value is greater than the negative terminal voltage value, the output terminal of the comparator outputs 1; when the positive terminal voltage value is less than the negative terminal voltage value, the output terminal of the comparator outputs 0.

10. An ADC sampling circuit chip, characterized in that: It is packaged using the ADC sampling circuit according to any one of claims 2 to 9, and the chip includes the following pins: Pin 1 is used to receive input signal VIN; Pin 2 is used to receive the reference current IREF; Pin three is used to receive sampling control signal; Pin 4 is used to receive the comparison control signal; Pin 5 is used for output signal OUT; Pin six is ​​used for electrical grounding; Pin seven, used to receive voltage signal VDD; Pin 8, used to receive the enable signal Vb1; Pin nine is used to receive an enable signal Vb2.

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