Semiconductor structure and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure and a forming method thereof. The method comprises: providing a semiconductor substrate, the semiconductor substrate comprising a storage region and a peripheral region; a surface of the storage region is formed with an insulating layer, and a surface of the peripheral region is formed with a first metal layer; etching the insulating layer and the storage region of the semiconductor substrate to form a plurality of bit line grooves arranged at intervals along a first direction and an etched insulating layer, wherein the bit line grooves are partially located in the storage region of the semiconductor substrate, and the other part of the bit line grooves is located in the etched insulating layer; forming a second metal layer on surfaces of the bit line grooves, the storage region and the first metal layer; etching the first metal layer and the second metal layer to form a semi-buried bit line structure and a peripheral gate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and relates to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] The development of dynamic memory pursues the requirements of high speed, high integration density, low power consumption, etc. With the miniaturization of semiconductor devices, especially in the manufacturing process of dynamic random access memory (DRAM) with a critical dimension less than 20 nanometers (nm), the structural stability of the bit line directly determines the electrical performance of the dynamic random access memory.

[0003] In the related art, the bit line of the dynamic random memory is located on the surface of the active region, and the bit line and the peripheral gate (PG) of the peripheral region are prepared separately, which is complex in preparation process and high in cost. In addition, the structure of the bit line formed in the related art is unstable, which leads to poor electrical performance of the dynamic random access memory. SUMMARY

[0004] Therefore, the embodiments of the present application provide a semiconductor structure and a forming method thereof.

[0005] In a first aspect, the embodiments of the present application provide a forming method of a semiconductor structure, which comprises the following steps:

[0006] providing a semiconductor substrate, wherein the semiconductor substrate comprises a storage region and a peripheral region; an insulating layer is formed on the surface of the storage region, and a first metal layer is formed on the surface of the peripheral region;

[0007] etching the insulating layer and the storage region of the semiconductor substrate to form a plurality of bit line grooves arranged at intervals along a first direction and an etched insulating layer, wherein a part of the bit line grooves is located in the storage region of the semiconductor substrate, and another part of the bit line grooves is located in the etched insulating layer;

[0008] forming a second metal layer on the surface of the bit line grooves, the storage region and the first metal layer;

[0009] etching the first metal layer and the second metal layer to form a semi-buried bit line structure and a peripheral gate.

[0010] In some embodiments, the insulating layer comprises a first word line insulating layer and a bit line insulating layer located between adjacent first word line insulating layers and covering the first word line insulating layers; and the method further comprises the following steps:

[0011] forming a buried word line structure in the memory region; wherein the buried word line structure comprises at least the first word line insulating layer, and the first word line insulating layer protrudes out of the top surface of the peripheral region.

[0012] In some embodiments, the top surface of the first word line insulating layer protrudes 70-90 nanometers out of the top surface of the peripheral region.

[0013] In some embodiments, the forming a buried word line structure in the memory region comprises:

[0014] forming a first isolation layer on the surface of the memory region and the peripheral region;

[0015] etching the first isolation layer on the surface of the memory region and the memory region to form a plurality of word line trenches arranged along a second direction; the second direction is perpendicular to the first direction;

[0016] forming the buried word line structure in the word line trenches.

[0017] In some embodiments, the forming the buried word line structure in the word line trenches comprises:

[0018] forming a gate oxide layer on the inner wall of the word line trenches;

[0019] forming a word line metal layer in the word line trenches with the gate oxide layer;

[0020] forming a word line insulating layer on the surface of the word line metal layer, wherein the word line insulating layer comprises a second word line insulating layer and the first word line insulating layer on the surface of the second word line insulating layer; the first word line insulating layer is located in the first isolation layer.

[0021] In some embodiments, the method further comprises:

[0022] after forming the buried word line structure, removing part of the first isolation layer of the peripheral region and the memory region to expose the first word line insulating layer.

[0023] In some embodiments, the method further comprises:

[0024] after exposing the first word line insulating layer, removing the remaining first isolation layer on the surface of the peripheral region to expose the surface of the peripheral region.

[0025] In some embodiments, the first metal layer is formed by:

[0026] forming a first initial metal layer, a first mask layer and a first photoresist layer on the surface of the peripheral region, the storage region and the first word line insulation layer in sequence; wherein the first photoresist layer has a first preset pattern, and the first preset pattern exposes the storage region;

[0027] etching the first mask layer through the first photoresist layer to realize transferring the first preset pattern to the first mask layer, and obtaining a patterned first mask layer;

[0028] etching the first initial metal layer through the patterned first mask layer to form the first metal layer.

[0029] In some embodiments, the method further comprises:

[0030] After forming the first metal layer, removing the first photoresist layer and the patterned first mask layer.

[0031] In some embodiments, the etching the insulation layer and the storage region to form a plurality of bit line trenches arranged along a first direction comprises:

[0032] forming the bit line insulation layer, a bit line mask layer and a second photoresist layer on the surface of the first metal layer, the storage region and the first word line insulation layer in sequence; the second photoresist layer has a second preset pattern, and the second preset pattern comprises a plurality of sub-patterns arranged in parallel along the first direction; each of the sub-patterns is used for forming one of the bit line trenches;

[0033] etching the bit line mask layer through the second photoresist layer to realize transferring the sub-patterns to the bit line mask layer, and obtaining a patterned bit line mask layer;

[0034] etching the bit line insulation layer, the first word line insulation layer and the storage region through the patterned bit line mask layer to form the bit line trenches.

[0035] In some embodiments, the method further comprises:

[0036] After forming the bit line trenches, removing the second photoresist layer, the patterned bit line mask layer, and the bit line insulation layer on the surface of the peripheral region.

[0037] In some embodiments, the etching the first metal layer and the second metal layer to form a semi-buried bit line structure and a peripheral gate comprises:

[0038] forming a second mask layer on the surface of the second metal layer in the peripheral region;

[0039] etching the second metal layer through the second mask layer to form an etched second metal layer; wherein the etched second metal layer in the bit line trench forms the semi-buried bit line structure;

[0040] etching the first metal layer through the etched second metal layer to form an etched first metal layer; wherein the etched first metal layer and the etched second metal layer in the peripheral region jointly form the peripheral gate.

[0041] In some embodiments, the method further comprises:

[0042] After forming the semi-buried bit line structure and the peripheral gate, a second isolation layer is formed on the surface of the peripheral region, the storage region and the peripheral gate.

[0043] In a second aspect, the embodiments of the present application provide a semiconductor structure, which is formed by the method for forming a semiconductor structure described above, and the semiconductor structure at least comprises:

[0044] a semiconductor substrate comprising a storage region and a peripheral region;

[0045] an etched insulating layer on the surface of the storage region;

[0046] a semi-buried bit line structure, a part of the semi-buried bit line structure is in the storage region, and another part of the semi-buried bit line structure is in the etched insulating layer;

[0047] a peripheral gate on the surface of the peripheral region.

[0048] In some embodiments, the etched insulating layer at least comprises an etched first word line insulating layer; the semiconductor structure further comprises a buried word line structure;

[0049] the buried word line structure is in the storage region; the buried word line structure at least comprises the etched first word line insulating layer, and the etched first word line insulating layer exceeds the top surface of the peripheral region.

[0050] The semiconductor structure and the forming method thereof provided by the embodiments of the present application, wherein the forming method of the semiconductor structure comprises: providing a semiconductor substrate comprising a storage region and a peripheral region, a surface of the storage region is formed with an insulating layer, and a surface of the peripheral region is formed with a first metal layer; etching the insulating layer and the storage region of the semiconductor substrate to form a plurality of bit line grooves arranged at intervals along a first direction and an etched insulating layer, and forming a second metal layer on surfaces of the bit line grooves, the storage region and the first metal layer; etching the first metal layer and the second metal layer to form a semi-embedded bit line structure and a peripheral gate. The semiconductor structure formed by the forming method of the semiconductor structure provided by the embodiments of the present application, the semi-embedded bit line and the peripheral gate can be simultaneously prepared and formed, and the structure of the semi-embedded bit line is stable, so that not only the preparation process of the semiconductor structure is greatly simplified, the preparation cost of the semiconductor structure is reduced, but also the electrical performance of the semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0051] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of the components. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0052] Figure 1 A flowchart of the forming method of the semiconductor structure provided by the embodiments of the present application;

[0053] Figures 2a to 2u A structural diagram of the forming process of the semiconductor structure provided by the embodiments of the present application;

[0054] Figure 3 A sectional view of the semiconductor structure provided by the embodiments of the present application along the X-axis direction;

[0055] BRIEF DESCRIPTION OF DRAWINGS:

[0056] 100 - semiconductor substrate; 101 - first isolation layer; 102 - word line trench; 103 - buried word line structure; 103a - gate oxide wall; 103b - word line metal layer; 103c - second word line insulation layer; 103d - first word line insulation layer; 101a - remaining first isolation layer; 104a - first initial metal layer; 104 - first metal layer; 104b - etched first metal layer; 105 - first mask layer; 106 - first photoresist layer; 107 - bit line insulation layer; 108 - bit line mask layer; 108a - amorphous carbon layer; 108b - first silicon oxynitride layer; 108c - spin-on hard mask layer; 108d - second silicon oxynitride layer; 109 - second photoresist layer; 110 - bit line trench; 111 - etched insulation layer; 112 - second metal layer; 112a - etched second metal layer; 113 - second mask layer; 114 - semi-buried bit line structure; 115 - peripheral gate; 116 - second isolation layer; 30 - semiconductor structure; A - memory area; C - peripheral area; B - sub-pattern. DETAILED DESCRIPTION

[0057] Example embodiments of the present application will now be described in detail with reference to the accompanying drawings. Although example embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited to specific embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0058] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one of ordinary skill in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily obscure the present application.

[0059] In the drawings, the size of layers, regions, elements and the like can be exaggerated for clarity. Like reference numerals can represent like elements throughout the several figures.

[0060] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application, and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] Based on the problems in the related art, the embodiments of the present application provide a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises: providing a semiconductor substrate comprising a storage region and a peripheral region, a surface of the storage region is formed with an insulating layer, and a surface of the peripheral region is formed with a first metal layer; etching the insulating layer and the storage region of the semiconductor substrate to form a plurality of bit line grooves arranged at intervals along a first direction and an etched insulating layer, and forming a second metal layer on surfaces of the bit line grooves, the storage region and the first metal layer; etching the first metal layer and the second metal layer to form a semi-embedded bit line structure and a peripheral gate. The semiconductor structure formed by the forming method of the semiconductor structure provided by the embodiments of the present application can simultaneously form the semi-embedded bit line and the peripheral gate, and the structure of the semi-embedded bit line is stable. Therefore, the preparation process of the semiconductor structure is greatly simplified, the preparation cost of the semiconductor structure is reduced, and the electrical performance of the semiconductor structure is improved.

[0063] The embodiments of the present application provide a forming method of a semiconductor structure, Figure 1A flowchart of a method for forming a semiconductor structure is shown in FIG. 1. The method for forming a semiconductor structure includes the following steps: Figure 1

[0064] In step S101, a semiconductor substrate is provided, which includes a storage region and a peripheral region. A surface of the storage region is formed with an insulating layer, and a surface of the peripheral region is formed with a first metal layer.

[0065] The semiconductor substrate can be a silicon substrate, and can also include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or combinations thereof.

[0066] In the embodiments of the present application, the storage region of the semiconductor substrate is used to form a memory device of a semiconductor device, such as a storage capacitor, and the peripheral region of the semiconductor substrate is used to form a peripheral control circuit of the semiconductor device. The insulating layer can be a material layer formed of any insulating material, such as a silicon nitride layer or a silicon oxynitride layer. The first metal layer can be a polysilicon layer, a doped silicon layer, or a silicide layer.

[0067] In step S102, the insulating layer and the storage region of the semiconductor substrate are etched to form a plurality of bit line trenches arranged at intervals along a first direction, and an etched insulating layer. The bit line trenches are partially located in the storage region of the semiconductor substrate, and the other part of the bit line trenches is located in the etched insulating layer.

[0068] In the embodiments of the present application, the semiconductor substrate can include a top surface at a front surface and a bottom surface at a back surface opposite to the front surface. A third direction is defined as a direction perpendicular to the top surface and the bottom surface of the semiconductor substrate, in the case of neglecting the flatness of the top surface and the bottom surface. In the direction of the top surface and the bottom surface of the semiconductor substrate (i.e., the plane direction of the semiconductor substrate), two first and second directions intersecting with each other (e.g., perpendicular to each other) are defined, for example, the arrangement direction of the plurality of bit line trenches can be defined as the first direction, and the plane direction of the semiconductor substrate can be determined based on the first and second directions. Here, the first, second, and third directions are perpendicular to each other. In the embodiments of the present application, the first direction is defined as an X-axis direction, the second direction is defined as a Y-axis direction, and the third direction is defined as a Z-axis direction.

[0069] ​In the embodiment of the present application, the part of the bit line trench is located in the storage region of the semiconductor substrate, and the other part of the bit line trench is located in the etched insulating layer, that is, the bit line trench in the embodiment of the present application is semi-buried in the semiconductor substrate.

[0070] In step S103, a second metal layer is formed on the surface of the bit line trench, the storage region and the first metal layer.

[0071] The second metal layer can be composed of any conductive material, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide or any combination thereof.

[0072] In step S104, the first metal layer and the second metal layer are etched to form a semi-buried bit line structure and a peripheral gate.

[0073] In the embodiment of the present application, the part of the semi-buried bit line structure is located in the storage region of the semiconductor substrate, and the other part of the semi-buried bit line structure is located in the etched insulating layer. The peripheral gate is a structural device located in the peripheral region.

[0074] Figures 2a to 2u The structural schematic diagram of the semiconductor structure formation process provided in the embodiment of the present application is shown in the following Figures 2a to 2u The forming method of the semiconductor structure provided in the embodiment of the present application is further described in detail.

[0075] Firstly, the following Figures 2a to 2j can be referred to. In step S101, a semiconductor substrate is provided, which includes a storage region and a peripheral region; an insulating layer is formed on the surface of the storage region, and a first metal layer is formed on the surface of the peripheral region.

[0076] Figure 2a The three-dimensional structural view of the semiconductor substrate provided in the embodiment of the present application is shown in the following Figure 2b The sectional view of the semiconductor substrate along the Y-axis direction is shown in the following Figure 2a and 2b As shown in the following

[0077] In some embodiments, the insulating layer located on the surface of the storage region includes a first word line insulating layer, and a bit line insulating layer located between and covering the adjacent first word line insulating layers. The forming method of the semiconductor structure further includes: forming a buried word line structure in the storage region; wherein the buried word line structure at least includes the first word line insulating layer, and the first word line insulating layer exceeds the top surface of the peripheral region.

[0078] In some embodiments, the process of forming the buried word line structure in the storage region includes the following steps:

[0079] Step S11: Form a first isolation layer on the surface of the storage area and the peripheral area.

[0080] The first isolation layer is a material layer formed of any insulating material. For example, the first isolation layer may be a silicon oxide layer or a silicon oxynitride layer. In the embodiments of this application, the first isolation layer can be formed by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or coating process.

[0081] Figure 2c To form a cross-sectional view of the first isolation layer along the Y-axis, as shown... Figure 2c As shown, a first isolation layer 101 is formed on the surfaces of storage region A and peripheral region C.

[0082] Step S12: Etch the first isolation layer and the storage area on the surface of the storage area to form multiple word line trenches spaced apart along the second direction.

[0083] In this embodiment, a dry etching process can be used to etch the first isolation layer and the storage region on the surface of the storage region to form word line trenches. For example, plasma etching, reactive ion etching, or ion milling processes can be used.

[0084] Figure 2d To form a cross-sectional view of the character line groove along the Y-axis, as shown... Figure 2d As shown, the first isolation layer 101 located on the surface of memory region A and the corresponding semiconductor substrate of the memory region are etched along the Z-axis direction to form a plurality of word line trenches 102 spaced apart along the Y-axis direction. From Figure 2d As can be seen, part of the word line trench 102 is located in the semiconductor substrate of the storage region, and another part of the word line trench 102 is located in the first isolation layer 101.

[0085] Step S13: Form an embedded character line structure in the character line groove.

[0086] In some embodiments, step S13 may include the following steps:

[0087] Step S131: Form a gate oxide layer on the inner wall of the word line trench.

[0088] Step S132: Form a word line metal layer in the word line trench where the gate oxide layer is formed.

[0089] Step S133, forming a word line insulating layer on the surface of the word line metal layer, wherein the word line insulating layer comprises a second word line insulating layer and a first word line insulating layer on the surface of the second word line insulating layer.

[0090] In the embodiment of the present application, the gate oxide layer can be a silicon oxide layer; the metal material constituting the word line metal layer can be tungsten, titanium nitride or a combination thereof; and the word line insulating layer can be a silicon nitride layer or a silicon oxynitride layer.

[0091] Figure 2e A cross-sectional view of the semiconductor structure along the Y-axis direction is shown in FIG. 1. As shown in FIG. 1, the semiconductor structure comprises a semiconductor substrate 100, a first isolation layer 101, a word line trench 102, a gate oxide layer 103a, a word line metal layer 103b, a second word line insulating layer 103c and a first word line insulating layer 103d. Figure 2e As shown in FIG. 1, the semiconductor structure comprises a semiconductor substrate 100, a first isolation layer 101, a word line trench 102, a gate oxide layer 103a, a word line metal layer 103b, a second word line insulating layer 103c and a first word line insulating layer 103d. The formation process of the buried word line structure 103 in each word line trench 102 comprises: first, forming the gate oxide layer 103a on the inner wall of the word line trench 102; second, depositing a metal material in the word line trench 102 on which the gate oxide layer 103a is formed to form the word line metal layer 103b; and third, forming the word line insulating layer on the surface of the word line metal layer 103b. In the embodiment of the present application, the word line insulating layer comprises the second word line insulating layer 103c and the first word line insulating layer 103d on the surface of the second word line insulating layer 103c. The second word line insulating layer 103c is located inside the semiconductor substrate, and the first word line insulating layer 103d is located in the first isolation layer 101, that is, the first word line insulating layer 103d exceeds the surface of the semiconductor substrate in the embodiment of the present application.

[0092] In some embodiments, the top surface of the first word line insulating layer 103d exceeds the top surface of the peripheral region by 70-90 nanometers (nm). In the embodiment of the present application, the top surface of the first word line insulating layer exceeding the top surface of the peripheral region can provide sufficient space for the subsequent buried bit line.

[0093] In some embodiments, after the formation of the buried word line, the method for forming the semiconductor structure further comprises:

[0094] Step S14, removing part of the first isolation layer in the peripheral region and the storage region to expose the first word line insulating layer.

[0095] Step S15, after the first word line insulating layer is exposed, removing the remaining first isolation layer on the surface of the peripheral region to expose the surface of the peripheral region.

[0096] Figure 2f And 2g A cross-sectional view of the semiconductor structure along the Y-axis direction is shown in FIG. 1. As shown in FIG. 1, the semiconductor structure comprises a semiconductor substrate 100, a first isolation layer 101, a word line trench 102, a gate oxide layer 103a, a word line metal layer 103b, a second word line insulating layer 103c and a first word line insulating layer 103d. Figure 2fAs shown, the first isolation layer with partial thickness on the peripheral region C and the storage region A is removed to expose the first word line insulation layer 103d, and the remaining first isolation layer 101a is retained on the peripheral region C and the partial storage region A; secondly, as shown, Figure 2g As shown, the remaining first isolation layer 101a on the peripheral region C is removed to expose the surface of the semiconductor substrate of the peripheral region C, and the remaining first isolation layer 101a is retained on the partial storage region A.

[0097] In some embodiments, the first metal layer on the surface of the peripheral region can be formed by the following steps:

[0098] Step S16, sequentially forming a first initial metal layer, a first mask layer and a first photoresist layer on the surface of the peripheral region, the storage region and the first word line insulation layer.

[0099] Figure 2h For the three-dimensional structure view of the first initial metal layer, the first mask layer and the first photoresist layer, Figure 2i For the sectional view along the Y-axis direction of the first initial metal layer, the first mask layer and the first photoresist layer, as shown, Figure 2h and 2i As shown, the first initial metal layer 104a, the first mask layer 105 and the first photoresist layer 106 are sequentially formed on the surface of the peripheral region C and the storage region A, and the first photoresist layer 106 has a first preset pattern in the embodiment of the application, and the first preset pattern exposes the storage region A.

[0100] Step S17, etching the first mask layer through the first photoresist layer to realize the transfer of the first preset pattern to the first mask layer, and obtaining a patterned first mask layer.

[0101] Step S18, etching the first initial metal layer through the patterned first mask layer to form a first metal layer.

[0102] Figure 2j For the sectional view along the Y-axis direction of the first metal layer, as shown, Figure 2j As shown, the first metal layer 104 is formed by sequentially etching the first mask layer 105 and the first initial metal layer 104a through the first photoresist layer 106, and the first metal layer 104 is located on the surface of the semiconductor substrate of the peripheral region C.

[0103] Please continue to see Figure 2j After the first metal layer 104 is formed, the method for forming the semiconductor structure further includes: removing the first photoresist layer and the patterned first mask layer.

[0104] In the embodiment of the application, the wet etching or dry etching technology can be used to remove the first photoresist layer and the patterned first mask layer.

[0105] In some embodiments, the process of forming the bit line insulation layer between and covering the adjacent first word line insulation layers can be understood by referring to step S102.

[0106] Next, step S102 can be performed by referring to Figures 2k to 2o etching the insulation layer and the storage region of the semiconductor substrate to form a plurality of bit line trenches arranged along the first direction and the etched insulation layer.

[0107] Part of the bit line trenches is located in the storage region of the semiconductor substrate, and another part of the bit line trenches is located in the etched insulation layer.

[0108] In some embodiments, step S102 can be formed by the following steps:

[0109] Step S1021, sequentially forming a bit line insulation layer, a bit line mask layer and a second photoresist layer on the surface of the first metal layer, the storage region and the first word line insulation layer; the second photoresist layer has a second preset pattern, and the second preset pattern includes a plurality of sub-patterns arranged in parallel along the first direction; each sub-pattern is used to form a bit line trench.

[0110] In the embodiments of the present application, the bit line insulation layer can be a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer, and the bit line mask layer can be composed of one hard mask layer or multiple hard mask layers.

[0111] Figure 2k To form a three-dimensional structure view of the bit line insulation layer, the bit line mask layer and the second photoresist layer, FIG. 21 is a cross-sectional view of the bit line insulation layer, the bit line mask layer and the second photoresist layer along the Y-axis direction, as shown in Figure 2k and 21, the bit line insulation layer 107, the bit line mask layer 108 and the second photoresist layer 109 are sequentially formed on the surface of the first metal layer 104, the storage region A and the first word line insulation layer 103d. In the embodiments of the present application, the bit line mask layer 108 includes an amorphous carbon layer (ACL) 108a, a first silicon oxynitride layer 108b, a spin-on hard mask layer (SOH) 108c and a second silicon oxynitride layer 108d stacked from bottom to top.

[0112] In the embodiments of the present application, the second photoresist layer 109 has a second preset pattern, and the second preset pattern includes a plurality of sub-patterns B arranged in parallel along the X-axis direction, and each sub-pattern B is used to form a bit line trench.

[0113] It should be noted that in this embodiment, the window for forming the bit line trench is relatively large and extends to the peripheral area. This is because the bit line needs to be led out from the storage area to the peripheral area to facilitate the access and lead-out of the bit line electrical signal.

[0114] Step S1022: Etch the bit line mask layer through the second photoresist layer to transfer the sub-pattern to the bit line mask layer and obtain a patterned bit line mask layer.

[0115] Step S1023: Using a patterned bit line mask layer, etch the bit line insulating layer, the first word line insulating layer, and the storage area to form a bit line trench.

[0116] Figure 2m To form a three-dimensional structural view of the bitline trench, Figure 2n To form a cross-sectional view of the bit line groove along the Y-axis, Figure 2o To form a cross-sectional view of the bitline trench along the X-axis, as shown... Figures 2m to 2o As shown, through the second photoresist layer 109, the second silicon oxynitride layer 108d, the spin-coated hard mask layer 108c, the first silicon oxynitride layer 108b, the amorphous carbon layer 108a, and the bit line insulating layer 107 are sequentially etched along the Z-axis, forming a plurality of bit line trenches 110 spaced apart along the X-axis. It can be seen that part of the formed bit line trenches 110 is located in the semiconductor substrate of the storage region A, and another part of the bit line trenches 110 is located in the etched insulating layer 111 (including the etched bit line insulating layer and the etched first word line insulating layer).

[0117] It should be noted that, in the embodiments of this application, a first word line insulation layer of a certain height is etched during the formation of the bit line trench.

[0118] Please continue reading Figures 2m to 2o After forming the bit line trench, the second photoresist layer, the patterned bit line mask layer, and the bit line insulating layer on the surface of the peripheral region are removed.

[0119] Next, you can refer to Figure 2p and 2q Step S103 is executed to form a second metal layer on the surface of the bit line trench, the storage region and the first metal layer.

[0120] The second metal layer can also be made of any conductive material, such as tungsten, cobalt, copper, aluminum, titanium nitride, polycrystalline silicon, doped silicon, silicide, or any combination thereof.

[0121] In some embodiments, the first metal layer and the second metal layer may be the same or different. In the embodiments of this application, the first metal layer and the second metal layer are different; for example, the first metal layer may be a polycrystalline silicon layer, and the second metal layer may be a tungsten metal layer.

[0122] Figure 2p A cross-sectional view along the X-axis direction for forming the second metal layer is shown in FIG. 4B. Figure 2q A cross-sectional view along the X-axis direction for forming the second metal layer is shown in FIG. 4B. Figure 2p A cross-sectional view along the X-axis direction for forming the second metal layer is shown in FIG. 4B. 2q A cross-sectional view along the X-axis direction for forming the second metal layer is shown in FIG. 4B.

[0123] Next, referring to FIG. 4C, step S104, etching the first metal layer and the second metal layer, is performed to form the semi-buried bit line structure and the peripheral gate. Figures 2r to 2t Next, referring to FIG. 4C, step S104, etching the first metal layer and the second metal layer, is performed to form the semi-buried bit line structure and the peripheral gate.

[0124] In some embodiments, step S104 can include the following steps:

[0125] Step S1041, forming a second mask layer on the surface of the second metal layer in the peripheral region.

[0126] In the embodiments of the present application, the second mask layer is used to form the peripheral gate, and the second mask layer can be a silicon nitride layer.

[0127] Figure 2r A cross-sectional view along the X-axis direction for forming the second mask layer is shown in FIG. 4D. Figure 2r A cross-sectional view along the X-axis direction for forming the second mask layer is shown in FIG. 4D.

[0128] Step S1042, etching the second metal layer through the second mask layer to form an etched second metal layer; wherein the etched second metal layer located in the bit line trench constitutes the semi-buried bit line structure.

[0129] Figure 2s A cross-sectional view along the X-axis direction for forming the semi-buried bit line structure is shown in FIG. 4E. Figure 2s A cross-sectional view along the X-axis direction for forming the semi-buried bit line structure is shown in FIG. 4E.

[0130] In the embodiments of the present application, the formed buried bit line structure is partially located inside the storage region A of the semiconductor substrate, and the other part is located in the insulating layer on the surface of the semiconductor substrate in the storage region, so that the semi-buried bit line structure can be formed.

[0131] Step S1043, etching the first metal layer through the etched second metal layer to form an etched first metal layer; wherein the etched first metal layer and the etched second metal layer located in the peripheral region jointly constitute the peripheral gate.

[0132] Figure 2t A cross-sectional view along the X-axis direction for forming the semi-buried bit line structure is shown in FIG. 4E.Figure 2t As shown, the first metal layer 104 is etched through the etched second metal layer 112a to form the etched first metal layer 104b; wherein the etched first metal layer 104b and the etched second metal layer 112a located in the peripheral region C together constitute the peripheral gate 115.

[0133] It should be noted that, in this embodiment of the application, due to the etching load effect caused by the different pattern densities of the array region A and the peripheral region C, the etched second metal layer 112a located in the bit line trench will not be etched during the process of etching the first metal layer through the etched second metal layer to form the etched first metal layer.

[0134] In some embodiments, after forming the semi-buried bit line structure and the peripheral gate, the method for forming the semiconductor structure further includes forming a second isolation layer on the surface of the peripheral region, the memory region and the peripheral gate.

[0135] Figure 2u To form a cross-sectional view of the second isolation layer along the X-axis, as shown... Figure 2u As shown, a second isolation layer 116 is formed on the surfaces of the peripheral region C, the storage region A, the semi-buried bit line structure 114, and the peripheral gate 115. In this embodiment, the second isolation layer 116 is used to isolate the buried bit line structure 114 from other components of the semiconductor structure, and the second isolation layer 116 is also used to isolate the peripheral gate 115 from other components of the semiconductor structure.

[0136] The semiconductor structure formed by the semiconductor structure formation method provided in this application embodiment can simultaneously prepare and form semi-buried bit lines and peripheral gates, and the structure of the semi-buried bit lines is stable. Thus, it not only greatly simplifies the semiconductor structure preparation process and reduces the semiconductor structure preparation cost, but also improves the electrical performance of the semiconductor structure.

[0137] In addition, this application also provides a semiconductor structure, which is formed by the semiconductor structure forming method provided in the above embodiments. Figure 3 A cross-sectional view along the X-axis of the semiconductor structure provided in the embodiments of this application, as shown below. Figure 3 As shown, the semiconductor structure 30 includes: a semiconductor substrate 100, an etched insulating layer 111, a semi-buried bit line structure 114, and a peripheral gate 115.

[0138] The semiconductor substrate 100 includes a storage region A and a peripheral region C. The storage region is used to form a storage device of the semiconductor device, such as a storage capacitor; the peripheral region is used to form a peripheral control circuit of the semiconductor device.

[0139] The insulating layer 111 after etching is located on the surface of the storage region A; and the semi-buried bit line structure 114 is partially located in the storage region A of the semiconductor substrate, and the other part of the semi-buried bit line structure 114 is located in the insulating layer 111 after etching.

[0140] The peripheral gate 115 is located on the surface of the peripheral region C, and the peripheral gate 115 is a functional device in the peripheral circuit.

[0141] In the embodiment of the present application, the insulating layer 111 after etching at least includes the first word line insulating layer after etching; and the semiconductor structure 30 further includes a buried word line structure (not shown in the figure). The buried word line structure is located in the storage region A, and the buried word line structure at least includes the first word line insulating layer after etching, and the first word line insulating layer after etching exceeds the top surface 70-90 nm of the peripheral region C.

[0142] In some embodiments, the semiconductor structure further includes a second isolation layer (not shown in the figure) located on the surfaces of the peripheral region C, the storage region A, the semi-buried bit line structure 114 and the peripheral gate 115, and the second isolation layer is used to isolate the peripheral gate and other devices of the semiconductor structure, and is also used to isolate the semi-buried bit line structure and other devices of the semiconductor structure.

[0143] It should be noted that, in the embodiment of the present application, the buried bit line structure and the peripheral gate can be simultaneously prepared by the forming method of the semiconductor structure provided in the above embodiment, so that the preparation process of the semiconductor structure is greatly simplified.

[0144] The semiconductor structure in the embodiment of the present application is similar to the forming method of the semiconductor structure in the above embodiment. For technical features not disclosed in detail in the embodiment of the present application, please refer to the above embodiment for understanding, which will not be described here.

[0145] The semiconductor structure provided in the embodiment of the present application can make the bit line structure have a larger area, and thus make the control ability of the bit line stronger, because the bit line is partially buried in the semiconductor substrate and the other part is buried in the insulating layer on the surface of the semiconductor substrate.

[0146] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be realized in a non-targeted manner. The device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling between the displayed or discussed components.

[0147] The units described as separate parts above can or can not be physically separate, and the parts displayed as units can or can not be physical units, that is, can be located in one place or distributed on multiple network units; part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0148] The features disclosed in several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0149] The above is only some embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, the method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a memory region and a peripheral region; a surface of the memory region being formed with an insulating layer, and a surface of the peripheral region being formed with a first metal layer; etching the insulating layer and the memory region of the semiconductor substrate to form a plurality of bit line trenches spaced apart along a first direction and an etched insulating layer, wherein the bit line trenches are partially located in the memory region of the semiconductor substrate and the other part of the bit line trenches are located in the etched insulating layer; the insulating layer comprising first word line insulating layers and bit line insulating layers located between and covering the first word line insulating layers; forming a second metal layer on surfaces of the bit line trenches, the memory region and the first metal layer; etching the first metal layer and the second metal layer to form a semi-buried bit line structure and a peripheral gate; and the method further comprising: forming a buried word line structure in the memory region; wherein the forming the buried word line structure in the memory region comprises: forming a first isolation layer on surfaces of the memory region and the peripheral region; etching the first isolation layer on the surface of the memory region and the memory region to form a plurality of word line trenches spaced apart along a second direction; the second direction being perpendicular to the first direction; and forming the buried word line structure in the word line trenches. 2.The method of claim 1, wherein the buried word line structure comprises at least the first word line insulating layers, and the first word line insulating layers protrude beyond a top surface of the peripheral region. 3.The method of claim 2, wherein the first word line insulating layers protrude beyond the top surface of the peripheral region by 70-90 nanometers. 4.The method of claim 1, wherein the forming the buried word line structure in the word line trenches comprises: forming a gate oxide layer on inner walls of the word line trenches; forming a word line metal layer in the word line trenches with the gate oxide layer; and forming a word line insulating layer on a surface of the word line metal layer, wherein the word line insulating layer comprises second word line insulating layers and the first word line insulating layers on surfaces of the second word line insulating layers; the first word line insulating layers being located in the first isolation layer. 5.The method of claim 1, wherein the method further comprises: removing the remaining first isolation layer on the surface of the peripheral region to expose a surface of the peripheral region after the first word line insulating layers are exposed. 6.The method of any one of claims 2-5, wherein the first metal layer is formed by: ​ ​ ​ ​ ​ ​ ​ ​ wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ forming a first initial metal layer, a first mask layer and a first photoresist layer on the surface of the peripheral region, the storage region and the first word line insulation layer in sequence; wherein the first photoresist layer has a first preset pattern, and the first preset pattern exposes the storage region; etching the first mask layer through the first photoresist layer to realize transferring the first preset pattern to the first mask layer, and obtaining a patterned first mask layer; forming the first metal layer by etching the first initial metal layer through the patterned first mask layer.

7. The method of claim 6, wherein, the method further comprises: after forming the first metal layer, removing the first photoresist layer and the patterned first mask layer.

8. The method of claim 7, wherein, the etching the insulation layer and the storage region to form a plurality of bit line trenches arranged along a first direction comprises: forming the bit line insulation layer, a bit line mask layer and a second photoresist layer on the surface of the first metal layer, the storage region and the first word line insulation layer in sequence; the second photoresist layer has a second preset pattern, and the second preset pattern comprises a plurality of sub-patterns arranged in parallel along the first direction; each of the sub-patterns is used to form one of the bit line trenches; etching the bit line mask layer through the second photoresist layer to realize transferring the sub-patterns to the bit line mask layer, and obtaining a patterned bit line mask layer; forming the bit line trenches by etching the bit line insulation layer, the first word line insulation layer and the storage region through the patterned bit line mask layer.

9. The method of claim 8, wherein, the method further comprises: after forming the bit line trenches, removing the second photoresist layer, the patterned bit line mask layer, and the bit line insulation layer on the surface of the peripheral region.

10. The method of claim 9, wherein, the etching the first metal layer and the second metal layer to form a semi-buried bit line structure and a peripheral gate comprises: forming a second mask layer on the surface of the second metal layer in the peripheral region; etching the second metal layer through the second mask layer to form an etched second metal layer; wherein the etched second metal layer located in the bit line trench constitutes the semi-buried bit line structure; etching the first metal layer through the etched second metal layer to form an etched first metal layer; wherein the etched first metal layer and the etched second metal layer located in the peripheral region jointly constitute the peripheral gate.

11. The method of claim 1, wherein, the method further comprises: after forming the semi-buried bit line structure and the peripheral gate, forming a second isolation layer on the surface of the peripheral region, the storage region and the peripheral gate.

12. A semiconductor structure, wherein, the semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 11, and the semiconductor structure comprises: a semiconductor substrate comprising a storage region and a peripheral region; an etched insulating layer located on a surface of the memory region; a semi-buried bit line structure, a portion of the semi-buried bit line structure located in the memory region and another portion of the semi-buried bit line structure located in the etched insulating layer; a peripheral gate located on a surface of the peripheral region.

13. The semiconductor structure of claim 12, wherein: the etched insulating layer comprises at least an etched first word line insulating layer; the semiconductor structure further comprises a buried word line structure; the buried word line structure is located in the memory region; the buried word line structure comprises at least the etched first word line insulating layer, and the etched first word line insulating layer extends beyond a top surface of the peripheral region.

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