Enhanced SPI Communication Protocol with Reliability, Security, and Fault Operability Features

Abstract

The present invention relates to a Serial Peripheral Interface (SPI) communication protocol. Specifically, the present disclosure proposes an extension of the SPI protocol. To this end, the present disclosure correspondingly proposes a device and a method for implementing the extended SPI protocol. The device is configured to transmit and / or receive extended SPI frames. The extended SPI frames include SPI frames and additionally include one or more bit sets that form the frame header and / or frame tail of the extended SPI frames. Therefore, each of the bit sets in the bit sets of the extended SPI frames corresponds to an extended SPI protocol capability.

Description

Technical Field

[0001] The present disclosure relates to a serial peripheral interface (SPI) communication protocol. Specifically, the present disclosure proposes an extension of the SPI protocol. To this end, the present disclosure correspondingly proposes devices and methods for implementing the extended SPI protocol. The extended SPI protocol is based on extended SPI frames and is backward compatible with the current SPI protocol. Background Art

[0002] The current SPI communication protocol has become the de facto standard in the industry due to its dominant position as a solution for inter-chip communication. For example, inter-chip communication between intelligent devices (such as microcontrollers, microprocessors, sensors, and actuators) that are physically distributed within the same electronic board or printed circuit board (PCB). The SPI protocol is specifically designed for high-speed short-distance serial data transmission, where any application running on top of the SPI protocol is distributed among several processing units - typically a master device (such as a processor) and one or more slave devices (such as processors) - that need to exchange data to establish a bidirectional, full-duplex, synchronous communication link.

[0003] In fact, today, the SPI protocol is built-in as a standard peripheral in many microcontroller units (MCUs) and system-on-chip (SoC) devices widely used in different industries. For example, the SPI protocol is used to interconnect a central processing unit (CPU) with external intelligent devices placed in the same electronic circuit or PCB, such as memories (such as flash memories), sensors (such as temperature sensors), and actuators (such as system basis chips, power switch devices, etc.).

[0004] Although the main functional / architectural features of the conventional SPI protocol are static, i.e., they are predefined and fixed by the standard itself, some of its features are flexible and configurable by the user. For example, the data length (i.e., the bits of the transmit (TX) / receive (RX) frames) or frequency (serial clock (SCLK)), polarity (clock polarity (CPOL)), and phase (clock phase (CPHA)) of the signals / waveforms involved in its physical interface are configurable.

[0005] The main features of the SPI protocol include:

[0006] · Master-slave model (MST-SLV)

[0007] · Four - wire interface (Master out Slave in (MOSI), Master in Slave out (MISO), SCLK, and Slave Select (SSEL)).

[0008] · Synchronous (SCLK) and time - deterministic communication

[0009] · Serial interface, full - duplex (MOSI, MISO)

[0010] · Single - host (MST) to single / multi - slave (SLV) communication options (point - to - point and daisy - chain)

[0011] · No transceiver required (TTL / CMOS logic levels)

[0012] · Designed for high - speed short - distance communication

[0013] The configurable features of the SPI protocol include:

[0014] · Variable data length (frame bits)

[0015] · Variable transmission frequency (SCLK)

[0016] · Configurable polarity (CPOL) and phase (CPHA)

[0017] Conventional SPI peripherals typically consist of a set of configurable registers (i.e., control registers, data registers, and status registers), which can be directly accessed by the system CPU (single - core) or CPU (multi - core) through the system bus and are usually mapped into the memory map of the MCU / SoC device. After configuring the SPI peripheral, data transmission can be performed.

[0018] Although the SPI protocol is widely adopted in the industry and has a wide range of applications, it also has some limitations. Specifically, it is not suitable for certain scenarios or use cases. Due to its simplicity, it is not suitable for some more restrictive or demanding use cases that require more stringent reliability and security features. For example, this is the case in safety-critical or mission-critical applications. In fact, many embedded systems must coexist in very harsh and noisy environments, and this fact may lead to potential problems related to electromagnetic interference (EMI). EMI consists of any unwanted, stray, conductive, or radiated power signal, which may cause unacceptable degradation in the performance of the system or device. When transmitting data end-to-end, EMI may have a negative impact on the signals or waveforms of the SPI interface. Therefore, EMI may cause misunderstandings of the communication data or protocol (for example, cosmic radiation in aerospace missions may cause single-event upsets - errors caused by radiation in microelectronic circuits - which may ultimately change the state of a storage unit from logic 1 to logic 0, and vice versa), and may ultimately lead to system failures.

[0019] Therefore, there is a reason to improve the current SPI protocol. Summary of the Invention

[0020] Embodiments of the present invention are also based on the following considerations made by the inventors.

[0021] In order to be able to prevent, detect, and correct some of the potential communication disturbances in the current SPI protocol, specific reliability and security countermeasures can be combined, such as data integrity checks and / or high-availability mechanisms.

[0022] Currently, the SPI protocol specifies how to transfer an SPI data frame (consisting only of the payload) from one end (the master device) to the other end (the slave device) in a synchronous (clock-based, bit-time) manner through TTL / CMOS logic levels (i.e., digital bits 1 or 0 encoded according to specific voltage level ranges), without the need for any specific protocol layering or transceivers. In addition, the master device is the device that provides the clock signal and initiates each communication.

[0023] In addition to establishing a single communication link between the master device and the slave device through a four-wire SPI interface, the conventional SPI protocol also enables a master device to address multiple slave devices simultaneously by establishing a communication bus. Effectively, the master device can be interconnected to multiple slave devices. In the case of managing multiple slave devices, such communication can be one of the following:

[0024] (i) Point-to-point, that is, by processing several select lines from the master device, each slave device in the slave devices has one select line.

[0025] (ii) A daisy chain configuration that affects slave devices in the same data transfer by forming an SPI frame as a result of appending multiple words, each word being associated with a slave device.

[0026] In addition, conventional SPI solutions are now integrated in MCU / SoC devices in the form of dedicated SPI peripherals and directly address the comprehensive issues of the SPI protocol in hardware with digitally implemented SPI master and slave controllers. The SPI protocol ensures the synchronous bi-directional transfer of data payloads from the master device to the slave device and vice versa, but does not provide any type of mechanism capable of checking the integrity of the data (payload) during data transfer. Due to this fact, in the case where an SPI slave device receives an SPI frame (payload) from an SPI master device and the SPI frame is corrupted during transmission through the physical layer (e.g., due to external noise sources such as EMI or electrostatic discharge (ESD), voltage and current peaks caused by inductive load switching, etc.), there is no error detection mechanism properly provided by the SPI protocol itself at either end.

[0027] The main drawbacks of conventional SPI protocols and related solutions are the lack of reliability, security, and / or fail-operational features and / or countermeasures, and this lack makes them unsuitable for strict or error-prone safety-critical or mission-critical applications. Conventional SPI protocol solutions simply do not support any end-to-end (E2E) communication countermeasures that are to be ported to the SPI protocol.

[0028] In view of the above problems and drawbacks, embodiments of the present invention aim to improve conventional SPI protocols and related solutions. The objective is to provide an extended SPI protocol with additional features / capabilities, aiming to make the extended SPI protocol suitable for a wider range of applications. That is to say, the goal is to extend the boundaries of the current SPI protocol. Specifically, the new features / capabilities of the extended SPI protocol should provide reliability, security, and / or fail-operational features and / or countermeasures.

[0029] In addition, embodiments of the present invention aim to provide all these new enhanced features / capabilities by incorporating them into the design and implementation of the hardware (e.g., in silicon, as part of the SPI peripheral of a device such as an MCU / SoC). The operability of the new capabilities should be flexible and configurable to provide extended functionality as an SPI backward-compatible solution. That is to say, it should be possible, for example, for the user to enable or disable all the new capabilities of the extended SPI protocol as needed during the SPI setup process. Therefore, if the user disables all the enhanced capabilities of the extended SPI peripheral, the resulting SPI protocol should behave like a conventional SPI protocol, which is currently standardized and adopted in, for example, MCU / SoC devices.

[0030] It should be noted that, just as it happens with the current SPI protocol, at both ends of the communication, the speaker and the listener, i.e., the master device and the slave device, are configured with the same set of features in order to establish a communication link, where each end can understand each other. The same concept should apply to the embodiments of the present invention, i.e., using the extended SPI protocol. In the case where one of the new capabilities is enabled, this capability should be configured the same at both ends, for example, configured the same on the master device and the slave device. In this sense, the extended SPI protocol should provide an evolution of the principles of the conventional SPI protocol, i.e., without modifying the essence of the conventional SPI communication protocol. Only the scope of application of the SPI protocol should be expanded, for example, by bringing robustness mechanisms in the form of new features / capabilities that users can configure in the extended SPI peripherals.

[0031] This object is achieved by the embodiments of the present invention described in the appended independent claims. Advantageous implementations of the embodiments of the present invention are further defined in the dependent claims.

[0032] In summary, the embodiments of the present invention propose to expand the set of capabilities of the conventional (traditional) SPI protocol in order to increase the reliability and robustness of the extended SPI protocol. The aim is to enable the resulting extended SPI protocol to be used in more demanding application scenarios / domains, where the conventional SPI protocol cannot withstand conditions of exposure to higher levels of noise, interference or perturbation. Therefore, the extended SPI protocol can be implemented to ensure backward compatibility with the conventional SPI protocol.

[0033] A first aspect of the present invention provides a device for implementing an extended SPI protocol, the device being configured to: send and / or receive extended SPI frames, wherein the extended SPI frames include SPI frames and additionally include one or more sets of bits that form the frame header and / or frame tail of the extended SPI frames; and wherein each set of bits in the set of bits of the extended SPI frames corresponds to an extended SPI protocol capability.

[0034] The extended SPI protocol is a communication protocol that is based on a function similar to the conventional SPI protocol but allows the use of extended SPI protocol capabilities. For this purpose, in the case where one or more extended SPI protocol capabilities are enabled, the extended SPI protocol is implemented by using extended SPI frames instead of SPI frames (which correspond to the conventional SPI frames of the conventional SPI protocol). Extended SPI protocol capabilities are capabilities or features that are not present in the conventional SPI protocol. They can be specified by sets of bits that form the frame tail and / or frame header of the extended SPI frames. Specifically, these capabilities implement reliability, security and / or fault operability and / or countermeasures, examples of which will be described below.

[0035] By enabling the extended SPI protocol capabilities, new functions are added compared to the conventional (traditional) SPI protocol, and these functions address the above-mentioned drawbacks of the conventional SPI protocol. Specifically, the device in the first aspect allows the extended SPI protocol (due to the extension of the conventional SPI protocol) to be used in a wider range of applications. By utilizing bit sets to extend the conventional SPI frame, that is, by forming the frame header and / or frame tail of the extended SPI frame, new SPI protocol capabilities can be specified in a simple manner. Therefore, these capabilities can be flexibly enabled and disabled to provide backward compatibility for the conventional SPI protocol.

[0036] In one implementation of the first aspect, the device includes a master device for executing the extended SPI protocol, and the master device is configured to: add the one or more bit sets to the SPI frame to form the extended SPI frame, send the extended SPI frame to one or more slave devices for executing the extended SPI protocol, and receive an extended SPI frame from the one or more slave devices; and / or the device includes a slave device for executing the extended SPI protocol, and the slave device is configured to: receive the extended SPI frame, obtain the one or more bit sets from the extended SPI frame, and perform one or more actions based on the obtained one or more bit sets, and also send an extended SPI frame to the master device.

[0037] For example, the device may include a master device and / or a slave device for inter-chip communication, for example, in a device peripheral (extended SPI peripheral). The device can be an MCU or an SoC. However, the device can also be a master device or a slave device.

[0038] In one implementation of the first aspect, the frame header and / or the frame tail of the extended SPI frame includes one or more data fields; and each bit set in the bit sets is included in a data field.

[0039] In the following of the present disclosure, the reference to a data field represents the reference to the bit sets included in the data field.

[0040] In one implementation of the first aspect, the device is further configured to: if it is determined that a specific extended SPI protocol capability is enabled, add a specific bit set corresponding to the specific extended SPI protocol capability to the extended SPI frame or obtain the specific bit set from the extended SPI frame.

[0041] Therefore, the new functions of the extended SPI protocol capabilities can be flexibly enabled or disabled.

[0042] In one implementation of the first aspect, the device is further configured to: send and / or receive the SPI frame instead of the extended SPI frame if no extended SPI protocol capabilities are enabled.

[0043] Therefore, if all extended SPI protocol capabilities are disabled, regular SPI frames of the regular SPI protocol can be exchanged. Thus, the extended SPI protocol is backward compatible with the regular SPI protocol.

[0044] Specifically, in addition to the extended SPI protocol capabilities, a beneficial aspect of the embodiments of the present invention is that the resulting extended SPI protocol is backward compatible with the currently standardized SPI protocol. This means that in the device of the first aspect, such as an MCU / SoC device, an extended SPI peripheral can be provided, where, for example, by software, all extended SPI protocol capabilities can be disabled to return to the regular SPI protocol.

[0045] In one implementation of the first aspect, the one or more extended SPI protocol capabilities include one or more of the following: data integrity check and / or error detection of the SPI frame; error correction of the SPI frame; activity indicator of the master device executing the extended SPI protocol; timestamp indicator of the SPI frame; watchdog timer of the master device; frame redundancy and / or replication of multiple master devices executing the extended SPI protocol redundantly; frame redundancy and / or replication detection and elimination of multiple slave devices executing the extended SPI protocol redundantly; automatic failover mechanism for multiple master and slave devices executing the extended SPI protocol.

[0046] The above implementation provides examples of the new functions provided by the extended SPI protocol capabilities. The extended SPI protocol capabilities mainly provide reliability, security, and / or fault operability and / or countermeasures.

[0047] In one implementation of the first aspect, the data integrity check and / or error detection is based on parity bits, checksum, cyclic redundancy check (CRC), or hash calculation; and the set of bits corresponding to the data integrity check and / or error detection includes the parity bits or includes multiple bits for the checksum or the CRC or the hash calculation and is included in the frame tail of the extended SPI frame.

[0048] In one implementation of the first aspect, the error correction is based on an error correction code; and the set of bits corresponding to the error correction includes multiple bits indicating the error correction code and / or one or more check bits and is included in the frame tail of the extended SPI frame.

[0049] In one implementation of the first aspect, the activity indicator is based on a counter; and the set of bits corresponding to the activity indicator includes a plurality of bits incremented for each extended SPI frame sent from the master device to the slave device executing the extended SPI protocol, and is included in the frame header of the extended SPI frame.

[0050] In one implementation of the first aspect, the set of bits corresponding to the timestamp indicator includes a plurality of bits indicating the time when the extended SPI frame is released by the master device executing the extended SPI protocol, and is included in the frame header of the extended SPI frame.

[0051] In one implementation of the first aspect, the watchdog timer is used to trigger the slave device executing the extended SPI protocol to monitor whether the master device executes the extended SPI protocol at an expected rhythm and / or within an expected time window.

[0052] In one implementation of the first aspect, the frame redundancy and / or duplicate detection and elimination is based on a sequence number or counter associated with the extended SPI frame; and the set of bits corresponding to the frame redundancy and / or duplicate detection and elimination includes a plurality of bits indicating the sequence number or counter, and is included in the frame header of the extended SPI frame.

[0053] In one implementation of the first aspect, the automatic failover mechanism is adapted to transfer control of the SPI protocol to another device or a second SPI physical channel when an error or failure in the performance of the extended SPI protocol is detected in a first SPI physical channel.

[0054] In one implementation of the first aspect, the device further includes: a set of extended SPI parameters configured to control and / or monitor the one or more extended SPI protocol capabilities.

[0055] The extended SPI parameters can be set / stored in an extended SPI register. Thus, a hardware implementation for enabling extended SPI capabilities is provided. With the extended SPI parameters, the extended SPI protocol capabilities can be flexibly enabled or disabled.

[0056] In one implementation of the first aspect, the set of extended SPI parameters is further configured to enable and / or disable the one or more extended SPI protocol capabilities.

[0057] Thus, the user can select the functions of the extended SPI protocol capabilities that should be activated. In addition, backward compatibility with the conventional SPI protocol can thus be enabled.

[0058] In one implementation of the first aspect, the extended SPI parameter set includes: one or more control parameters, where each control parameter is configured to enable at least one extended SPI protocol capability; and / or one or more status parameters, where each status parameter is configured to monitor the status of at least one extended SPI protocol capability.

[0059] In one implementation of the first aspect, the device further includes: an SPI parameter set, which is independent of the extended SPI parameter set, where each SPI parameter is configured to enable at least one conventional SPI protocol capability.

[0060] Thus, the conventional (traditional) SPI protocol capabilities can be controlled (enabled, disabled, monitored) independently of the (new) extended SPI protocol capabilities. This supports backward compatibility.

[0061] In one implementation of the first aspect, the device further includes: a set of extended SPI logic blocks, which are combined to support the central processing unit (CPU) of the device to execute one or more enabled extended SPI protocol capabilities.

[0062] Thus, a hardware implementation is provided to enable / implement the new features / capabilities of the extended SPI protocol.

[0063] In one implementation of the first aspect, the set of extended SPI logic blocks includes: one or more first extended SPI logic blocks, where each first extended SPI logic block can be configured by the CPU to execute at least one extended SPI peripheral capability.

[0064] Thus, a hardware implementation is provided for the device to flexibly enable and disable the new features / capabilities of the extended SPI protocol.

[0065] In one implementation of the first aspect, the set of extended SPI logic blocks further includes: one or more second extended SPI logic blocks, where each second extended SPI logic block is configured to interconnect two extended SPI peripherals, such that the two SPI peripherals work redundantly to send and receive the same extended SPI frame through two independent SPI physical channels by performing frame replication and cancellation for reliability policies, or if the first SPI physical channel is detected as defective at any point in time during operation, the two SPI peripherals work to transfer the sending and receiving of the extended SPI frame from the first SPI physical channel to the second SPI physical channel at runtime, as an automatic failover mechanism.

[0066] A second aspect of the present invention provides a method for implementing an extended SPI protocol, the method comprising: transmitting and / or receiving an extended SPI frame, wherein the extended SPI frame includes an SPI frame and further includes one or more bit sets constituting a frame header and / or a frame tail of the extended SPI frame; and wherein each bit set in the bit sets of the extended SPI frame corresponds to an extended SPI protocol capability.

[0067] In one implementation of the second aspect, the method is executed by a master device for implementing the extended SPI protocol, wherein the master device adds the one or more bit sets to the SPI frame to form the extended SPI frame, transmits the extended SPI frame to one or more slave devices for implementing the extended SPI protocol, and may further receive an extended SPI frame from the one or more slave devices; and / or the method is executed by a slave device for implementing the extended SPI protocol, wherein the slave device receives the extended SPI frame, obtains the one or more bit sets from the extended SPI frame, and performs one or more actions based on the obtained one or more bit sets, and may further transmit an extended SPI frame to the master device.

[0068] In one implementation of the second aspect, the frame header and / or the frame tail of the extended SPI frame includes one or more data fields; and each bit set in the bit sets is included in a data field.

[0069] In one implementation of the second aspect, the method further comprises: adding a specific bit set corresponding to the specific extended SPI protocol capability to the extended SPI frame or obtaining the specific bit set from the extended SPI frame if it is determined that the specific extended SPI protocol capability is enabled.

[0070] In one implementation of the second aspect, the method further comprises: transmitting and / or receiving the SPI frame instead of the extended SPI frame if no extended SPI protocol capability is enabled.

[0071] In one implementation of the second aspect, the one or more extended SPI protocol capabilities include one or more of the following: data integrity check and / or error detection of the SPI frame; error correction of the SPI frame; an activity indicator of the master device for implementing the extended SPI protocol; a timestamp indicator of the SPI frame; a watchdog timer of the master device; frame redundancy and / or replication of multiple master devices redundantly implementing the extended SPI protocol; frame redundancy and / or replication detection and elimination of multiple slave devices redundantly implementing the extended SPI protocol; an automatic failover mechanism for multiple master devices and slave devices implementing the extended SPI protocol.

[0072] In one implementation of the second aspect, the data integrity check and / or error detection is based on a parity bit, a checksum, a cyclic redundancy check (CRC), or a hash calculation; and the set of bits corresponding to the data integrity check and / or error detection includes the parity bit or includes a plurality of bits for the checksum or the CRC or the hash calculation, and is included in the frame tail of the extended SPI frame.

[0073] In one implementation of the second aspect, the error correction is based on an error correction code; and the set of bits corresponding to the error correction includes a plurality of bits indicating the error correction code and / or one or more check bits, and is included in the frame tail of the extended SPI frame.

[0074] In one implementation of the second aspect, the activity indicator is based on a counter; and the set of bits corresponding to the activity indicator includes a plurality of bits that are incremented for each extended SPI frame sent from the master device to the slave device that executes the extended SPI protocol, and is included in the frame header of the extended SPI frame.

[0075] In one implementation of the second aspect, the set of bits corresponding to the timestamp indicator includes a plurality of bits indicating the time when the extended SPI frame is released by the master device that executes the extended SPI protocol, and is included in the frame header of the extended SPI frame.

[0076] In one implementation of the second aspect, the watchdog timer is used to trigger the slave device that executes the extended SPI protocol to monitor whether the master device executes the extended SPI protocol at an expected rhythm and / or within an expected time window.

[0077] In one implementation of the second aspect, the frame redundancy and / or duplicate detection and elimination is based on a sequence number or a counter associated with the extended SPI frame; and the set of bits corresponding to the frame redundancy and / or duplicate detection and elimination includes a plurality of bits indicating the sequence number or the counter, and is included in the frame header of the extended SPI frame.

[0078] In one implementation of the second aspect, the automatic failover mechanism is adapted to transfer control of the SPI protocol to another device or a second SPI physical channel when an error or a fault in the performance of the extended SPI protocol is detected in a first SPI physical channel.

[0079] In one implementation of the second aspect, the method further includes: using an extended SPI parameter set to control and / or monitor the one or more extended SPI protocol capabilities.

[0080] In one implementation of the second aspect, the extended SPI parameter set is further configured to enable and / or disable the one or more extended SPI protocol capabilities.

[0081] In one implementation of the second aspect, the extended SPI parameter set includes: one or more control parameters, where each control parameter is configured to enable at least one extended SPI protocol capability; and / or one or more status parameters, where each status parameter is configured to monitor the status of at least one extended SPI protocol capability.

[0082] In one implementation of the second aspect, the method further includes: using an SPI parameter set that is independent of the extended SPI parameter set, where each SPI parameter is configured to enable at least one traditional SPI protocol capability.

[0083] In one implementation of the second aspect, the method further includes: using a set of extended SPI logic blocks that are combined to support the central processing unit (CPU) of the device to execute one or more enabled extended SPI protocol capabilities.

[0084] In one implementation of the second aspect, the set of extended SPI logic blocks includes: one or more first extended SPI logic blocks, where each first extended SPI logic block can be configured by the CPU to execute at least one extended SPI peripheral capability.

[0085] In one implementation of the second aspect, the set of extended SPI logic blocks further includes: one or more second extended SPI logic blocks, where each second extended SPI logic block is configured to interconnect two extended SPI peripherals such that the two SPI peripherals work redundantly to send and receive the same extended SPI frame through two independent SPI physical channels by performing frame replication and cancellation for a reliability policy, or if the first SPI physical channel is detected as defective at any point in time during operation, the two SPI peripherals work to transfer the sending and receiving of the extended SPI frame from the first SPI physical channel to the second SPI physical channel at runtime as an automatic failover mechanism.

[0086] The method of the second aspect enjoys all the advantages of the device of the first aspect.

[0087] A third aspect of the present invention provides a computer program, the computer program including program code which, when executed on a computer, is used to execute the method according to any one of the second aspect or its implementation manners.

[0088] A fourth aspect of the present invention provides a non-transitory storage medium storing executable program code which, when executed by a processor, causes the method according to any one of the second aspect or its implementation manners to be executed.

[0089] In summary, the above aspects and implementation manners propose to fill the above communication reliability gap of the conventional SPI protocol by extending the conventional SPI protocol with new functions / capabilities, and these new functions / capabilities are aimed at improving the reliability and security aspects of the extended SPI protocol itself. These new SPI protocol capabilities incorporated into the extended SPI protocol are specifically designed to target their correct operation in more stringent scenarios (such as mission-critical and / or safety-critical applications). To some extent, the extended SPI protocol can be equipped with a consistent set of data protection mechanisms, which can be carefully designed to detect and / or protect the extended SPI protocol communication from many possible sources of failure, such as electromagnetic interference, electrostatic discharge, noise or signal timing problems. Some of these new features can be found in packet-based network protocols and standards (such as ISO 26262 (functional safety)), strategies (such as Frame Replication and Elimination for Reliability (FRER)), or other communication algorithms (such as error detection codes and error correction codes).

[0090] It should be noted that all devices, elements, units and devices described in this application can be implemented in software or hardware elements or any combination thereof. All steps performed by the various entities described in this application and the functions to be performed by the various entities described are intended to mean that the corresponding entities are adapted or configured to perform the corresponding steps and functions. Although in the description of the following specific implementation manners, the specific functions or steps performed by external entities are not reflected in the description of the specific detailed elements of the entities performing the specific steps or functions, those skilled in the art should be clear that these methods and functions can be implemented in the corresponding hardware or software elements or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0091] The above aspects and implementation manners will be explained in the following description of the specific implementation manners with reference to the drawings, in which

[0092] Figure 1Shows a device for implementing an extended SPI protocol according to an embodiment of the present invention.

[0093] Figure 2 Shows a conventional SPI frame compared to the extended SPI frame used in an embodiment of the present invention.

[0094] Figure 3 Shows an exemplary parameter / register set of an SPI peripheral compared to the parameter / register set of an extended SPI peripheral used in an embodiment of the present invention.

[0095] Figure 4 Shows an exemplary system architecture of an SPI protocol compared to the system architecture of an extended SPI protocol implemented in an embodiment of the present invention.

[0096] Figure 5 Shows an example of frame redundancy implementation through two extended SPI protocol channels used in an embodiment of the present invention.

[0097] Figure 6 Shows the decomposition of the data field of an extended SPI frame used in an embodiment of the present invention.

[0098] Figure 7 Shows an extended SPI (protocol) peripheral that can be embedded in a device such as an MCU or SoC.

[0099] Figure 8 Shows a method for implementing an extended SPI protocol according to an embodiment of the present invention. Detailed Description

[0100] Figure 1 Shows a device 100 according to an embodiment of the present invention. The device 100 is configured to implement an extended SPI protocol, which includes new (extended) features / capabilities compared to the conventional SPI protocol. The device 100 may include a master device and / or a slave device that can implement the extended SPI protocol.

[0101] Specifically, the device 100 is configured to send and / or receive an extended SPI frame 101. Specifically, if the device 100 includes a master device, the device 100 can send an extended SPI frame. If the device 100 includes a slave device, the device 100 can receive the extended SPI frame 101. If the device 100 includes both a master device and a slave device, and SPI protocol communication can occur between the master device and the slave device, the device 100 can send and receive the extended SPI frame 101. SPI protocol communication, specifically SPI protocol communication between the master device and the slave device, can occur in the SPI peripheral of the device 100.

[0102] For example, device 100 may include a master device for implementing an extended SPI protocol. The master device is configured to add one or more bit sets to SPI frame 102 to form extended SPI frame 101, and further send extended SPI frame 101 to one or more slave devices for implementing the extended SPI protocol. The master device may also receive extended SPI frame 101 from one or more slave devices (e.g., one form for each slave device). Additionally or alternatively, device 100 may include a slave device for implementing the extended SPI protocol. The slave device is configured to receive extended SPI frame 101 and obtain one or more bit sets from extended SPI frame 101. The slave device may also perform one or more actions based on the obtained one or more bit sets. Further, the slave device may also be configured to send extended SPI frame 101 to the master device.

[0103] Extended SPI frame 101 includes SPI frame 102, i.e., SPI frame 102 (specifically the payload) used in the conventional SPI protocol, and additionally includes one or more bit sets. These one or more bit sets constitute the header 103 and / or the footer 104 of extended SPI frame 101. That is, extended SPI frame 101 may include one or more bit sets that only constitute header 103 (without footer 104), or may include one or more bit sets that only constitute footer 104 (without header 103), or may include multiple bit sets that constitute both header 103 and footer 104. For example, header 103 and / or footer 104 may include one or more data fields, and each bit set in the one or more bit sets may be included in one or more of the data fields in the data fields.

[0104] In addition, each bit set in the bit sets of extended SPI frame 101 corresponds to an extended SPI protocol capability. That is, each bit set added to header 103 and / or footer may specify or enable an extended SPI protocol capability. Thus, different combinations of bit sets may be included in extended SPI frame 101 to specify or enable various combinations of extended SPI protocol capabilities. The extended SPI protocol capabilities may also not be enabled at all. In this case, device 100 may send (e.g., the master device) and / or receive (e.g., the slave device) SPI frame 102 (of the conventional / traditional SPI protocol) instead of extended SPI frame 101. In other words, in this case, the transmitted / received SPI frame 102 includes neither header 103 nor footer 104.

[0105] Device 100 may include a processor or processing circuitry (not shown) configured to perform, conduct, or initiate the various operations of device 100 described herein. The processing circuitry may include hardware and / or the processing circuitry may be controlled by software. The hardware may include analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may include components such as an application-specific integrated circuit (ASIC), a field-programmable array (FPGA), a digital signal processor (DSP), or a general-purpose processor.

[0106] Device 100 may further include a memory circuit that stores one or more instructions that may be executed by the processor or by the processing circuitry (specifically, executed under the control of software). For example, the memory circuit may include a non-transitory storage medium that stores executable software code that, when executed by the processor or the processing circuitry, causes the various operations of device 100 to be performed.

[0107] In one embodiment, the processing circuitry includes one or more processors and a non-transitory memory connected to the one or more processors. The non-transitory memory may carry executable program code that, when executed by the one or more processors, causes device 100 to perform, conduct, or initiate the operations or methods described herein.

[0108] Embodiments of the present invention, such as device 100, may be provided with extended SPI protocol capabilities (new features relative to the original SPI protocol) based on the following three aspects.

[0109] The first aspect relates to extending the SPI frame 101 (or frame format). In this regard, Figure 2 A conventional SPI frame (top) is shown compared to an extended SPI frame 101 (bottom). To extend the SPI protocol, the extended SPI protocol capabilities contemplated in this disclosure may be added in a manner that affects the format of the SPI frame. Specifically, to incorporate the new functions of the extended SPI protocol, embodiments of the present invention contemplate the extended SPI frame 101.

[0110] Currently, the SPI frame consists of only one data block that corresponds to the payload (see Figure 2, at the top), i.e., based on the raw data of a certain amount of bits transmitted in both directions (e.g., from the master device to the slave device via the MOSI line and from the slave device to the master device via the MISO line) between, for example, the master device and the slave device. Now, in the extended SPI frame 101, this data payload can be extended by using some new data fields (including one or more bit sets) allocated in the frame header 103 and / or the frame tail 104 of the extended SPI frame 101 (also as Figure 2 shown at the bottom).

[0111] This means that a regular SPI frame of n bits can be extended with an additional h bits (i.e., one or more bit sets from the above-mentioned bit sets), which can be placed before the payload and / or an additional t bits (i.e., one or more bit sets from the above-mentioned bit sets), which can be placed after the payload. The number, position, and meaning of bits h and t can be specific to each of the implemented extended SPI protocol capabilities. In other words, each of the new features in the extended SPI protocol capabilities may require adding a specific number of bits, i.e., constituting the frame header 103 and / or the frame tail 104 of the extended SPI frame 101. However, although some new capabilities can be deployed without affecting the SPI frame (i.e., without additional bits in both the frame header 103 and the frame tail 104 of the extended SPI frame 101), as will be explained later when detailing each extended SPI protocol capability.

[0112] Regarding the backward compatibility of the extended SPI frame 101, the frame header 103 and the frame tail 104 (their data fields) can be architected in such a way that they are optional (as Figure 2 shown), which can depend on the set of configurable extended SPI protocol capabilities enabled or disabled. For example, by the user in software, e.g., by writing to one or more configuration registers of the device 100 (e.g., in the extended SPI peripheral). More specifically, each of these extended SPI protocol capabilities can be enabled or disabled independently of each other. Thus, if all capabilities are disabled simultaneously, the resulting SPI frame will be the original SPI frame (SPI frame 102) corresponding to the traditional SPI protocol, which consists only of the Figure 2 payload depicted in. By this strategy, backward compatibility of the extended SPI frame 101 with respect to the regular SPI frame 102 can be guaranteed.

[0113] The second aspect relates to SPI parameters and SPI registers. Specifically, a set of extended SPI parameters 301, 302 (e.g., set / stored in the SPI register) can be configured to control and / or monitor one or more extended SPI protocol capabilities. In this regard, Figure 3Shows an exemplary set of SPI parameters / registers of a conventional SPI peripheral (left; i.e., for the conventional SPI protocol) compared to a set of SPI parameters / registers of an extended SPI peripheral (right; i.e., for the extended SPI protocol).

[0114] From a logical or functional perspective, due to the aforementioned desired backward compatibility, the management of all extended SPI protocol capabilities can be implemented in a flexible and scalable manner. Thus, the set of SPI parameters / registers and / or the memory map can be extended to enhance the SPI peripheral into an extended SPI peripheral. This means that if the conventional SPI protocol is handled by a set of control, data, and status parameters / registers 311, 312, then this set of parameters / registers can be extended with some other control and status parameters / registers 301, 302 in order to include the controllability and observability aspects of all these new functions, as Figure 3 shown. These additional SPI parameters / registers 301, 302 can be accessed by the system CPU of device 100, for example, following exactly the same write and read procedures as the original SPI registers / parameters 311, 312, thus only changing their physical addresses to access the correct SPI parameters / registers.

[0115] As Figure 3 shown, the extended SPI parameters / registers 301, 302 of the extended SPI peripheral, which can be named the extended control register (eCONTROL register) 302 and the extended status register (eSTATUS register) 301, can be independent of the traditional SPI parameters / registers 311, 312 (control register 311 and status register 312), and these traditional SPI parameters / registers 311, 312 can be the same as and fully compatible with the SPI parameters / registers of the conventional SPI peripheral.

[0116] By configuring the eCONTROL parameter / register 302, the user can define which extended SPI protocol capabilities are enabled and, thus, which data fields (bit sets) are used for Figure 2 shown in the header 103 and / or the footer 104 of the extended SPI frame 101, i.e., which data fields are activated. This correspondingly extends the length of the extended SPI frame 101. In the case where the user disables all enhanced SPI protocol capabilities via the eCONTROL parameter / register 302, the resulting SPI frame will match the conventional SPI frame, i.e., without the header 103 and the footer 104 and only having the payload, as Figure 2As shown. By enabling / configuring each extended SPI protocol capability, the frame header 103 and / or the frame tail 104 can consist of specific data fields including one or more bit sets necessary for encoding-related functions. Therefore, the lengths of the frame header 103 and / or the frame tail 104 can depend on the set of capabilities enabled by the user in each application use case.

[0117] Still regarding the SPI frame backward compatibility, in the case of handling an extended version of the SPI peripheral, it is necessary to configure an additional set of SPI parameters / register groups 301, 302, while if the extended SPI protocol capability is disabled, the SPI peripheral can continue to be managed through the conventional set of SPI parameters / register groups 311, 312. That is to say, the set of SPI parameters / registers 311, 312 is independent of the set of extended SPI parameters / registers 301, 302, where each SPI parameter / register 311, 312 is configured to enable at least one traditional SPI protocol capability.

[0118] The third aspect is related to the SPI logic and the hardware circuit. That is to say, the device 100 can include a set of extended SPI logic blocks 401, 402, where these blocks 401, 402 can be combined to support the CPU 403 of the device 100 to execute one or more of the enabled extended SPI protocol capabilities. In this regard, Figure 4 An exemplary system architecture of the conventional SPI protocol (left) is shown compared with the system architecture of the extended SPI protocol (right).

[0119] From the perspective of the system architecture, the hardware circuit can be modified to deploy the SPI protocol communication based on the extended SPI frame 101 and the extended SPI register set or the extended memory map for setting the extended SPI parameters 301, 302.

[0120] In addition to the register set for implementing the extended SPI protocol capabilities and the extended SPI frame 101, where the extended SPI frame 101 can include data fields collected in the frame header 103 and / or the frame tail 104 of the extended SPI frame 101 - while the SPI frame 102 (payload) located between the frame header 103 and the frame tail 104 maintains the same structure as a regular standardized SPI frame - the system architecture of the extended SPI protocol can combine new functions in hardware through one or more logic blocks 401, 402. These logic blocks 401, 402 can be responsible for implementing new algorithms and can interact with the traditional logic blocks of conventional SPI peripherals in one way or another to ensure backward compatibility. Specifically, this can be ensured by integrating the new logic blocks 401, 402 into the hardware design in a non-invasive manner - in this sense, these logic blocks 401, 402 do not modify the expected behavior of the conventional SPI protocol capabilities. For this purpose, the architecture design can be as described below (and as Figure 4 shown).

[0121] Currently, the system CPU (see Figure 4 , left side) can access any conventional SPI peripheral of the MCU / SoC device by means of read and write commands ( Figure 3 shown, left side), and the read and write commands address different SPI parameters / registers for each instance of the SPI peripheral that exists in the MCU / SoC device and is mapped in the full memory layout of the MCU / SoC device. Now, for the extended SPI peripheral of device 100 (see Figure 4 , right side), these accesses can remain the same, with the only difference being that due to the increased (extended) SPI protocol capabilities that can be configured, the set of SPI parameters / registers present in the extended SPI peripheral consists of some additional SPI parameters / registers 301, 302 (see Figure 3 , right side).

[0122] Regarding the hardware implementation of these extended SPI protocol capabilities, the size of the extended SPI peripherals can increase with some additional logic blocks 401, 402, which can be organized into two different types of modules: the first extended logic block 401 (eX), which is used for each extended SPI #X peripheral (corresponding to the extended SPI capabilities), and the second extended logic block 402 (eXY), which is used to interconnect two extended SPI peripherals #X and #Y (corresponding to two different SPI protocol capabilities) in the case of activating the redundancy function as one of the possible extended SPI protocol capabilities described later in this document. That is, each first extended SPI logic block 401 can be configured by the CPU 403 to perform at least one extended SPI protocol capability. In addition, each second extended SPI logic block 402 can be configured to interconnect two extended SPI peripherals. Figure 4 This concept is shown in a graphical view.

[0123] It is worth noting that in the case of disabling the redundancy function of the two extended SPI peripherals #X and #Y, from a functional perspective, access to the second logic block 402 (eXY) can be bypassed, and the two extended SPI peripherals will remain independent of each other.

[0124] All of these features can be implemented by functional blocks within the device 100 (such as an MCU / SoC device), which correspond to controllers or engines responsible for handling each of the capabilities provided in the new extended SPI protocol.

[0125] In summary, by combining the above three aspects, an extended SPI peripheral / protocol can be implemented, which ensures backward compatibility with the conventional SPI peripheral / protocol.

[0126] The following presents examples of extended SPI capabilities that enhance the SPI protocol to an extended SPI protocol so that it can be used in mission-critical and high-availability scenarios where the conventional SPI protocol is not suitable.

[0127] Generally, embodiments of the present invention may include adding the following enhancements (extended SPI protocol capabilities) to the conventional SPI protocol capabilities:

[0128] 1. Data integrity check and / or error detection of the SPI frame 102.

[0129] 2. Error correction of the SPI frame 102.

[0130] 3. Activity indicator for the master device executing the extended SPI protocol.

[0131] 4. Timestamp indicator for the SPI frame 102.

[0132] 5. Watchdog timer for the master device.

[0133] 6. Frame redundancy and / or replication of multiple master devices that redundantly execute the extended SPI protocol.

[0134] 7. Detection and elimination of frame redundancy and / or replication of multiple slave devices that redundantly execute the extended SPI protocol.

[0135] 8. Automatic failover mechanism for multiple master and slave devices that execute the extended SPI protocol.

[0136] Now, all of these features are not considered in the conventional SPI protocol. Embodiments of the present invention are based on integrating these features into an extended SPI protocol in order to provide an enhanced version that can withstand harsh environments or mission-critical applications. The technical details of the relevant extended SPI protocol capabilities are introduced one by one below.

[0137] 1. Data integrity check as an error detection mechanism: This feature includes integrating a mechanism in the extended SPI communication protocol that can detect errors in the case where the SPI frame 102 (payload) transmitted by the transmitter (SPI master device) does not match the SPI frame 102 received by the receiver (SPI slave device). Some examples of algorithms that can be combined as error detection codes in the enhanced SPI protocol are: parity bits, checksums, cyclic redundancy check (CRC), or any other hash calculation. The size of this data field in the enhanced frame can be extended from 1 single bit in the case of parity bits to 8 or 16 bits for, for example, CRC or hash. Due to functional reasons (i.e., this data field cannot be calculated unless the complete data frame is received), this data field can be allocated in the frame tail 104 of the extended SPI frame 101.

[0138] 2. Error correction mechanism (detecting and correcting certain types of errors): In addition to an error detection mechanism such as CRC, another protection mechanism can be integrated in the enhanced SPI protocol that can not only detect errors but also correct errors. That is, an error correction code (ECC) for controlling errors in data on an unreliable or noisy communication channel. The basic principle of ECC is to add redundant bits to the data message to be transmitted (here the SPI frame 102) to help the receiver (such as the SPI slave device) find the true message encoded by the transmitter (such as the SPI master device). Redundancy allows the receiver to detect a limited number of errors that may occur anywhere in the message and usually correct these errors without retransmission. For example, Hamming codes are a series of linear error correction codes that can detect up to 2-bit errors or correct 1-bit errors without detecting uncorrected errors.

[0139] Unlike error detection codes, error correction codes (ECC) not only allow the detection of certain types of errors but also allow the correction of these errors in some cases. This feature can also be deployed in the extended SPI protocol, specifically in use cases for high-availability or fail-operational applications.

[0140] For example, Hamming (7,4) is a linear error correction code that encodes four bits of data into seven bits by adding three parity bits. That is, this Hamming code adds three additional check bits for every four data bits of the message, and the algorithm can correct any single-bit error or detect all single-bit errors and two-bit errors. In other words, the minimum Hamming distance between any two correct codewords is 3, and if the received word is at a distance of at most 1 from the codeword sent by the transmitter, then the received word can be correctly decoded. This means that for transmission media cases where burst errors do not occur, the Hamming (7,4) code is effective (because for two of the seven bits to be flipped, the media would have to be extremely noisy). Typically, the size of the ECC data field in the extended SPI frame 101 can be 8 bits or 16 bits, and due to functional reasons (i.e., the data field cannot be calculated unless the entire extended SPI frame 101 is received), this data field can be allocated in the frame tail 104 of the extended frame.

[0141] 3. Activity indicator: An activity indicator is a mechanism used in applications where the receiver (e.g., here the SPI slave) needs to know the availability and correct operation of the transmitter (e.g., here the SPI master) by scheduling the periodic reception of certain frames, where it is necessary to check that the received frame is fresh (new, different from the previous frame) just to prove that the transmitter has not failed / shut down / broken, but remains active during normal execution. This feature is particularly useful in functional safety applications where a slave processor monitors the correct operation of a host or master processor.

[0142] An example of algorithm implementation is simply to add an activity counter field including a cyclic n-bit counter to the extended SPI frame 101, which can be incremented on each transmission request from the transmitter and checked at the receiver side. The size of this counter can typically be 4 bits or more, and due to functional reasons (i.e., in the case where the activity counter is found to be defective, the processing of the SPI frame 102 (payload) can be skipped and the SPI frame can be discarded, and the receiver will react to this situation by triggering / activating certain fail-safe or safety operation responses), this field can be allocated in the frame header 103 of the extended SPI frame 101.

[0143] 4. Timestamp Indicator: In certain applications, especially time-sensitive ones, it may be beneficial to know the exact system time that is typically running in the master device so that the slave device can perform certain operations in a synchronized manner. In such cases, a data field with a corresponding timestamp related to the moment when the transmitter releases the SPI frame 102 can be appended to the extended SPI frame 101. To implement this feature in the logic, access to the system timer of, for example, an MCU / SoC can be provided to the SPI peripheral.

[0144] The size of this data field in the extended SPI frame 101 can depend on the time precision of the application and the granularity of the system clock of the transmitter. This data field can typically be placed in the frame header 103 of the extended SPI frame 101.

[0145] 5. Watchdog Timer: In safety-critical applications driven by time-sensitive conditions, an external watchdog mechanism is typically used in the slave device to monitor that the tasks of the master device are being executed correctly. In such cases, with the help of the synchronized extended SPI frame 101 sent by the master device, the slave device can check whether the master device is working at the expected rhythm of receiving the extended SPI frame 101, either within the expected time window in the case of the watchdog window mode or before the timeout expires in the case of the watchdog timeout mode. If the extended SPI frame 101 is not received within the correct time slot, the slave device will trigger a safety response.

[0146] It is worth noting that this extended SPI protocol capability can be achieved without affecting the extended SPI frame length, and can only be achieved by adding logic and configuration parameters / registers in the enhanced SPI hardware peripheral.

[0147] In addition to the use of individual SPI peripherals, the extended SPI protocol allows two of these extended SPI peripherals in the extended SPI peripherals to be interconnected to work together in redundant communication. For this purpose, two independent extended SPI peripherals of the device 100 (such as an MCU / SoC) can be selected and configured in a dual-mode by linking them via some specific logic combined in the hardware, as Figure 4 shown. The next two features 6 and 7 relate to this dual-SPI configuration.

[0148] 6. Frame Redundancy and Duplication: The application scope of the conventional SPI protocol does not cover any type of data transmission redundancy strategy - a feature particularly needed in high-availability time-sensitive systems, where backward retransmission of data frames is not an option in case of a first attempt failure. If the channel is corrupted and the transmitted data sent by the transmitter does not reach the receiver, or if the data is received but corrupted, in time-critical or fail-operational applications, it is required to either have redundant channels that do not fail simultaneously, thus skipping a single failure that would cause system failure, or trigger a fail-safe reaction mechanism in real time and ensure a time-deterministic response or failover reaction within a timeout (e.g., activating certain degraded operating modes or fail-safe modes). This aspect can be considered in the extended SPI protocol proposed in the present disclosure.

[0149] Some applications require the implementation of redundant communication channels to send the same data frame through two independent channels to become reliable against a single source of failure. For example, to ensure that the data frame sent from the master device to the slave device reaches the slave device even when one of the E2E channels is defective, thus aiming at a fail-operational solution. In the present disclosure, this process can affect the extended SPI frame 101 format. Specifically, a sequence counter or sequence number 501 (data field) can be added to the extended SPI frame 101 so that the slave device can identify duplicate (e.g., replicated) frames and eliminate one or more of the duplicate frames when two or more redundant SPI channels are not defective. The size of the sequence number or counter 501 can generally be 4 bits or more bits, and this data field can be allocated in the frame header 103 of the extended SPI frame. Figure 5 This sequence counter or sequence number 501 is shown in the extended SPI frame 1 in

[0150] In addition to the extended SPI frame 101, with regard to the hardware implementation, it is beneficial to deploy a logic block 402 (e.g., see Figure 4 ), and this logic block 402 is responsible for interconnecting two independent extended SPI peripherals to work in a redundant manner when this feature is enabled. When configured for this purpose, this additional logic block 402 can establish a bridge between two extended SPI peripherals #X and #Y (e.g., see the logic block 402 (eXY) in Figure 5 ). For example, if this feature is disabled by configuring relevant parameters / registers, the two SPI channels may be disconnected again and may work independently of each other without any kind of physical relationship. A topological example of this scheme is shown in Figure 5 as shown in

[0151] In Figure 5Specifically, two devices 100, a master device 100_a and a slave device 100_b, are shown according to an embodiment of the present invention. Both devices 100_a and 100_b are configured to send and receive extended SPI frames 101 to and from each other. The extended SPI frame 101 may include a sequence counter or sequence number 501. In addition, both devices 100_a and 100_b are provided with a CPU 403 and logic blocks 401, 402 (as shown in Figure 4 ), and may be provided with / maintain registers / parameters 301, 302 (as shown in Figure 3 ).

[0152] 7. Automatic failover mechanism: This feature, which is seamlessly linked to the previous features, may include a process by which, when the master SPI subsystem detects an error or failure, the master SPI subsystem can automatically transfer control to the secondary SPI subsystem in order to minimize the failover time. This extended SPI protocol capability can be implemented without affecting the format or length of the extended SPI frame 101, but can be achieved by adding some logic blocks 402 (e.g., see block 402(eXY) in Figure 4 ) and configuration parameters / registers only in the enhanced SPI hardware peripherals.

[0153] As a summary of the above seven extended SPI protocol capabilities (features), Figure 6 shows a possible decomposition of the data fields (i.e., bit sets) included in the extended SPI frame 101 previously introduced in Figure 2 . Figure 6 The extended SPI frame 101 shown in includes all the bit sets required to implement the entire set of features simultaneously. These are the bit sets for the activity indicator 601 (or counter), the timestamp 602, the watchdog timer 603 (watchdog command), and the bit sets for data integrity checking and / or error detection 604 (CRC here) and / or for error correction 604 (ECC here).

[0154] Finally, for all of these seven extended SPI protocol capabilities, according to the expected backward compatibility, there may be at least one control bit called "enable / disable" in each feature in the eCONTROL register 302 (see Figure 3 ), and these control bits can be used to activate or deactivate their associated SPI protocol capabilities. For example, the enhanced function can only start and run when this bit is set to "1". Therefore, if the user disables some of the extended SPI protocol capabilities, the affected data fields (bit sets) linked to that feature can automatically disappear from the extended SPI frame 101, or from the frame header 103 or frame tail 104.

[0155] Figure 7Shows a specific implementation example according to an embodiment of the present invention. Specifically, it can be considered to allocate a new IP core or peripheral called "Enhanced SPI or Extended SPI" within any next-generation chip planned to be built. The extended SPI core may include Figure 3 The extended SPI registers 301, 302 of the extended SPI peripheral shown, that is, it may include one or more eCONTROL registers 302 and one or more eSTATUS registers 301. In addition, the extended SPI core may include a conventional SPI control register 311 and a status register 312, which may be the same as and fully compatible with the control register and status register of a conventional SPI peripheral. For example, for a chip in the automotive market. This new extended SPI peripheral can be interconnected to the system bus of an MCU or SoC device so as to be accessible by the multi-core processors instantiated there.

[0156] Figure 8 Shows a method 800 according to an embodiment of the present invention. The method 800 may be executed by a device 100. The method 800 includes step 801 of transmitting and / or receiving an extended SPI frame 101. The extended SPI frame 101 includes an SPI frame 102 and additionally includes one or more bit sets that constitute a frame header 103 and / or a frame tail 104 of the extended SPI frame 101. Therefore, each bit set in the bit sets of the extended SPI frame 101 corresponds to (802) the extended SPI protocol capabilities.

[0157] The present invention has been described in connection with various embodiments and implementations by way of example. However, upon study of the drawings, the present disclosure, and the independent claims, those skilled in the art will be able to understand and implement other variations when practicing the claimed invention. In the claims as well as in the specification, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items described in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage in an implementation.

Claims

1. A device (100) for performing an extended Serial Peripheral Interface (SPI) protocol, the device (100) being configured to: Transmit and / or receive extended SPI frames (101), Wherein, The extended SPI frame (101) includes an SPI frame (102) and additionally includes one or more bit sets that constitute a frame header (103) and / or a frame tail (104) of the extended SPI frame (101); and Wherein each of the bit sets in the extended SPI frame (101) corresponds to an extended SPI protocol capability; The device is further configured to: Determine whether a specific extended SPI protocol capability is enabled; If it is determined that the specific extended SPI protocol capability is enabled, add a specific bit set corresponding to the specific extended SPI protocol capability to the extended SPI frame (101) or obtain the specific bit set from the extended SPI frame (101).

2. The device (100) according to claim 1, Wherein: The device (100) includes a master device for performing the extended SPI protocol, the master device being configured to: add the one or more bit sets to the SPI frame (102) to form the extended SPI frame (101), transmit the extended SPI frame (101) to one or more slave devices for performing the extended SPI protocol, and receive extended SPI frames (101) from the one or more slave devices; and / or The device (100) includes a slave device for performing the extended SPI protocol, the slave device being configured to: receive the extended SPI frame (102), obtain the one or more bit sets from the extended SPI frame (101), perform one or more actions based on the obtained one or more bit sets, and further transmit an extended SPI frame (101) to the master device.

3. The device (100) according to claim 1, Wherein: The frame header (103) and / or the frame tail (104) of the extended SPI frame (101) includes one or more data fields; and Each of the bit sets is included in a data field.

4. The device (100) according to claim 1, being configured to: If no extended SPI protocol capability is enabled, transmit and / or receive the SPI frame (102) instead of the extended SPI frame (101).

5. The device (100) according to any one of claims 1 to 4, Wherein, The one or more extended SPI protocol capabilities include one or more of the following: - Data integrity check and / or error detection (604) of the SPI frame (102); - Error correction (604) of the SPI frame (102); - Activity indicator (601) of the master device performing the extended SPI protocol; - Timestamp indicator (602) of the SPI frame (102); - Watchdog timer (603) of the master device; - Redundantly execute frame redundancy and / or replication for multiple master devices implementing the extended SPI protocol; - Redundantly execute frame redundancy and / or replication detection and elimination for multiple slave devices implementing the extended SPI protocol; - Implement an automatic failover mechanism for multiple master and slave devices implementing the extended SPI protocol.

6. The apparatus (100) according to claim 5, wherein: the data integrity check and / or error detection (604) is based on parity bits, checksum, cyclic redundancy check CRC, or hash calculation; and the set of bits corresponding to the data integrity check and / or error detection (604) includes the parity bits or includes multiple bits for the checksum or the CRC or the hash calculation and is included in the frame tail (104) of the extended SPI frame (101).

7. The apparatus (100) according to claim 5, wherein: the error correction (604) is based on error correction codes; and the set of bits corresponding to the error correction (604) includes multiple bits indicating the error correction code and / or one or more check bits and is included in the frame tail (104) of the extended SPI frame (101).

8. The apparatus (100) according to claim 5, wherein: the activity indicator is based on a counter; and the set of bits corresponding to the activity indicator (601) includes multiple bits that are incremented for each extended SPI frame (101) sent from the master device to the slave device implementing the extended SPI protocol and is included in the frame header (103) of the extended SPI frame (101).

9. The apparatus (100) according to claim 5, wherein: the set of bits corresponding to the timestamp indicator (602) includes multiple bits indicating the time when the extended SPI frame (101) was released by the master device implementing the extended SPI protocol and is included in the frame header of the extended SPI frame (101).

10. The apparatus (100) according to claim 5, wherein: the watchdog timer (603) is used to trigger the slave device implementing the extended SPI protocol to monitor whether the master device executes the extended SPI protocol at an expected rhythm and / or within an expected time window.

11. The apparatus (100) according to claim 5, wherein: the frame redundancy and / or replication detection and elimination is based on a sequence number or counter (501) associated with the extended SPI frame (101); and the set of bits corresponding to the frame redundancy and / or replication detection and elimination includes multiple bits indicating the sequence number or counter (501) and is included in the frame header (103) of the extended SPI frame (101).

12. The apparatus (100) according to claim 5, wherein: the automatic failover mechanism is adapted to transfer control of the SPI protocol to another device or a second SPI physical channel when an error or failure in the performance of the extended SPI protocol is detected in a first SPI physical channel.

13. The device (100) according to any one of claims 1 to 4, further comprises: a set of extended SPI parameters (301, 302) configured to control and / or monitor the one or more extended SPI protocol capabilities.

14. The device (100) according to claim 13, wherein: the set of extended SPI parameters (301, 302) is further configured to enable and / or disable the one or more extended SPI protocol capabilities.

15. The device (100) according to claim 13, wherein, the set of extended SPI parameters comprises: one or more control parameters (302), wherein each control parameter (302) is configured to enable at least one extended SPI protocol capability; and / or one or more status parameters (301), wherein each status parameter (301) is configured to monitor the status of at least one extended SPI protocol capability.

16. The device (100) according to claim 13, further comprises: a set of SPI parameters (311, 312) independent of the set of extended SPI parameters (301, 302), wherein each SPI parameter (311, 312) is configured to enable at least one traditional SPI protocol capability.

17. The device (100) according to any one of claims 1 to 4, further comprises: a set of extended SPI logic blocks (401, 402) combined to support the central processing unit CPU (403) of the device (100) to execute one or more enabled extended SPI protocol capabilities.

18. The device (100) according to claim 17, wherein the set of extended SPI logic blocks (401, 402) comprises: one or more first extended SPI logic blocks (401), wherein each first extended SPI logic block (401) can be configured by the CPU to execute at least one extended SPI peripheral capability.

19. The device (100) according to claim 18, wherein, the set of extended SPI logic blocks (401, 402) further comprises: one or more second extended SPI logic blocks (402), wherein each second extended SPI logic block (402) is configured to interconnect two extended SPI peripherals such that the two SPI peripherals work redundantly to send and receive the same extended SPI frame (101) through two independent SPI physical channels for performing frame replication and cancellation for a reliability policy, or, if the first SPI physical channel is detected as defective at any point in time during operation, the two SPI peripherals work to transfer the sending and receiving of the extended SPI frame (101) from the first SPI physical channel to the second SPI physical channel at runtime as an automatic failover mechanism.

20. A method (800) for performing an extended serial peripheral interface SPI protocol, the method (800) comprises: Transmit and / or receive (801) an extended SPI frame (101), wherein the extended SPI frame (101) includes an SPI frame (102) and additionally includes one or more bit sets that constitute a frame header (103) and / or a frame tail (104) of the extended SPI frame (101); and wherein each of the bit sets in the bit sets of the extended SPI frame (101) corresponds to (802) an extended SPI protocol capability The method further includes: Determine whether a specific extended SPI protocol capability is enabled; If it is determined that the specific extended SPI protocol capability is enabled, add a specific bit set corresponding to the specific extended SPI protocol capability to the extended SPI frame (101) or obtain the specific bit set from the extended SPI frame (101).

21. A computer program comprising program code for performing the method (800) according to claim 20 when executed on a computer.

Images