Three-dimensional memory devices and methods for forming the same

Abstract

A three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed over the first semiconductor structure, and the second semiconductor structure includes a second substrate and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to memory devices and methods for forming memory devices, and more particularly to three-dimensional (3D) memory devices and methods for forming 3D memory devices. BACKGROUND

[0002] Planar semiconductor devices, such as memory cells, have been scaled down to smaller and smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature sizes of semiconductor devices approach lower limits, planar processes and fabrication technology become more difficult and more costly. 3D semiconductor device architectures can address some of the density limitations in planar semiconductor devices (e.g., flash memory devices).

[0003] 3D semiconductor devices can be formed by stacking semiconductor wafers or dies and vertically interconnecting them so that the resulting structure functions as a single device, thereby achieving performance improvements at reduced power and smaller footprint relative to conventional planar processes. Among various techniques for stacking semiconductor substrates, bonding such as hybrid bonding is considered a promising technique because it can form high-density interconnections. SUMMARY

[0004] In one aspect, a 3D memory device is disclosed. The 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed above the first semiconductor structure, and the second semiconductor structure includes a second substrate and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.

[0005] In another aspect, a system is disclosed. The system includes a 3D memory device configured to store data and a memory controller. The 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed above the first semiconductor structure, and the second semiconductor structure includes a second substrate and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure. The memory controller is coupled to the 3D memory device and configured to control operations of the 3D memory device.

[0006] In yet another aspect, a method for forming a 3D memory device is disclosed. A memory array structure is formed over a first substrate. A second substrate is formed over the memory array structure. A peripheral device is formed in contact with the second substrate. An interconnect layer is formed over the peripheral device. The second substrate is disposed between the peripheral device and the memory array structure.

[0007] In yet another aspect, a method for forming a 3D memory device is disclosed. A first dielectric layer is formed over a first substrate. A memory array structure is formed within the first dielectric layer. A second substrate is bonded to the first dielectric layer. The second substrate includes a second dielectric layer, and the second dielectric layer is bonded to the first dielectric layer. A hetero-interface is formed within the second substrate. Portions of the second substrate are removed along the hetero-interface, thereby forming a third substrate over the memory array structure. A peripheral device is formed within the third substrate. An interconnect layer is formed over the peripheral device. The third substrate is disposed between the peripheral device and the memory array structure.

[0008] In yet another aspect, a method for forming a 3D memory device is disclosed. A first dielectric layer is formed over a first substrate. A memory array structure is formed within the first dielectric layer. A composite substrate is bonded to the first dielectric layer. The composite substrate includes a second dielectric layer, and the second dielectric layer is bonded to the first dielectric layer. Portions of the composite substrate are removed, thereby forming a second substrate over the memory array structure. A peripheral device is formed within the second substrate. An interconnect layer is formed over the peripheral device. The second substrate is disposed between the peripheral device and the memory array structure. BRIEF DESCRIPTION OF DRAWINGS

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0010] Figure 1 Cross-sectional views of exemplary 3D memory devices in accordance with some aspects of the present disclosure are shown.

[0011] Figures 2-13 Cross-sectional views of exemplary 3D memory devices in different stages of fabrication in accordance with some aspects of the present disclosure are shown.

[0012] Figure 14 Flowcharts of exemplary methods for forming 3D memory devices in accordance with some aspects of the present disclosure are shown.

[0013] Figure 15 Flowcharts of another exemplary method for forming 3D memory devices in accordance with some aspects of the present disclosure are shown.

[0014] Figure 16 A flow diagram illustrating another example method for forming a 3D memory device in accordance with some aspects of the present disclosure is shown.

[0015] Figure 17 A block diagram illustrating an example system having a memory device in accordance with some aspects of the present disclosure is shown.

[0016] Figure 18A A diagram illustrating an example memory card having a memory device in accordance with some aspects of the present disclosure is shown.

[0017] Figure 18B A diagram illustrating an example solid state drive (SSD) having a memory device in accordance with some aspects of the present disclosure is shown.

[0018] Figure 19 A cross-sectional view of another example 3D memory device in accordance with some aspects of the present disclosure is shown.

[0019] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Moreover, the present disclosure can also be employed in a variety of other applications. The described features and structural or methodological aspects can be combined in various ways to produce other embodiments, all of which are within the scope of the present disclosure.

[0021] In general, terminology can be understood at least in part from usage and context. For example, terms, such as "one or more" as used herein, can be taken to mean that at least one, or there is equivalent to at least one, and that at least one but not only one. Similarly, as used herein, the terminology "one" or "the" can be taken to signify both singular and plural, at the discretion of the context. Further, such as "based on" can be taken to mean "based, at least in part, on," that is, "based on" can be taken to allow that there are other factors as well which can affect a

[0022] It should be readily understood that the terms "on," "above," and "over" are meant to encompass both the meanings of directly on as well as on with intervening features or layers between the stated "on," "above," or "over" and the stated item, and that "above" or "over" is meant to encompass both the meanings of above or over as well as above or over with no intervening features or layers (i.e., directly on).

[0023] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0024] As used herein, the term "layer" can refer to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have a shape that is smaller than the underlying or overlying structure. Further, a layer can be a region of a continuous structure that is homogeneous or inhomogeneous in composition, and that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any pair of horizontal planes between a top surface and a bottom surface of the continuous structure, or at the top surface and the bottom surface. Layers can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can contain one or more layers therein, and / or can have one or more layers thereon and / or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (within which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0025] As used herein, the term "substrate" refers to a material on which a subsequent material layer is added. The substrate itself can be patterned. Material added on top of the substrate can be patterned or can remain unpatterned. Further, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be composed of a non-conductive material such as glass, plastic, or sapphire wafer, etc.

[0026] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND memory strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically" refers to nominally perpendicular to a lateral surface of the substrate.

[0027] In some 3D memory devices (e.g., 3D NAND memory devices), the stack of the device includes both a memory array device and a peripheral device, e.g., a complementary metal-oxide-semiconductor (CMOS) chip. As the number of layers in the array memory device continues to increase, the size of the memory array device or the peripheral device continues to decrease. As such, there is a need to scale down the area of the CMOS chip to ensure that the array efficiency does not significantly decrease.

[0028] Figure 1 A cross-sectional view of an exemplary 3D memory device 100 is shown in accordance with some aspects of the present disclosure. The 3D memory device 100 includes a first semiconductor structure 102 and a second semiconductor structure 104. A bonding interface 106 is formed between the first semiconductor structure 102 and the second semiconductor structure 104. The first semiconductor structure 102 includes a substrate 108. The substrate 108 can be a doped semiconductor layer and can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In some embodiments, the first semiconductor structure 102 includes the substrate 108 and the substrate 108 includes a doped single crystalline silicon layer.

[0029] In some embodiments, the substrate 108 is a thick substrate, as shown in Figure 1 In some embodiments, where pad-out from the substrate 108 is desired for the 3D memory device 100, the substrate 108 can be a thinned substrate (e.g., a semiconductor layer) that has been thinned by polishing, etching, chemical mechanical polishing (CMP), or any combination thereof. It should be noted that in Figure 1The inclusion of the x-axis and y-axis is to further illustrate the spatial relationship of components in the 3D memory device 100. The substrate 108 of the 3D memory device 100 includes two lateral surfaces (e.g., top and bottom surfaces) that extend laterally along the x-direction (i.e., lateral direction). As used herein, when a substrate (e.g., substrate 108) of a 3D memory device (e.g., 3D memory device 100) is in the lowest plane of the 3D memory device in the y-direction, whether a component (e.g., layer or device) of the 3D memory device is "on," "above," or "below" another component (e.g., layer or device) is determined relative to the substrate in the y-direction (i.e., vertical direction). The same concept is employed throughout the disclosure to describe spatial relationships.

[0030] In some embodiments, the 3D memory device 100 can be part of a non-monolithic 3D memory device in which components (e.g., peripheral devices and memory array devices) can be formed separately onto different substrates before being bonded. In some embodiments, the memory array structure 110 can be formed onto the substrate 108 to form a first semiconductor structure 102. The substrate 112 is then bonded onto the first semiconductor structure 102, and the peripheral device layer 114 is formed in the substrate 112, thereby forming a second semiconductor structure 104. In some embodiments, the second semiconductor structure 104 can include the substrate 112, and the substrate 112 can include a doped single crystalline silicon layer.

[0031] The bonding interface 106 is formed on a bonding surface between the first semiconductor structure 102 and the second semiconductor structure 104. In some embodiments, the second semiconductor structure 104 can further include an interconnect layer 116 formed on and electrically connected to the peripheral device layer 114. The 3D memory device 100 can further include a contact pad 118 disposed on top of the second semiconductor structure 104. The contact pad 118 can be electrically coupled to the peripheral device layer 114 through the interconnect layer 116.

[0032] In some embodiments, the first semiconductor structure 102 including the memory array structure 110 is formed first, and then the substrate 112 is formed on the memory array structure 110. In some embodiments, to form the substrate 112 on the memory array structure 110, a dielectric layer 120, e.g., silicon oxide, is formed on the memory array structure 110, and another dielectric layer 122, e.g., silicon oxide, is further formed under the substrate 112. The dielectric layer 120 and the dielectric layer 122 are then bonded, and the bonding interface 106 is formed on a bonding surface between the dielectric layer 120 and the dielectric layer 122.

[0033] In some embodiments, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings, each NAND memory string extending vertically above the substrate 108. As shown in FIG. 1A, the substrate 108 includes a semiconductor well 102 and a plurality of charge storage regions 104. The semiconductor well 102 can be a P-well or an N-well. The charge storage regions 104 can be charge trapping dielectric regions of a charge trapping layer. The charge storage regions 104 can be formed of silicon nitride or any other suitable material. The charge storage regions 104 can be formed in a single crystalline semiconductor region of the substrate 108. The charge storage regions 104 can be formed in a semiconductor-on-insulator (SOI) substrate. The charge storage regions 104 can be formed in an amorphous semiconductor region of the substrate 108. The charge storage regions 104 can be formed in a polycrystalline semiconductor region of the substrate 108. The charge storage regions 104 can be formed in a combination of a single crystalline semiconductor region, an amorphous semiconductor region, a polycrystalline semiconductor region, and a semiconductor-on-insulator (SOI) substrate. Figure 1 The memory array structure 110 can include a memory stack 124 and a channel structure 126, as shown in FIG. 1B. The memory stack 124 includes alternating conductive layers and dielectric layers, and the conductive layers can include at least one source select gate line, a plurality of word lines, and at least one drain select gate line.

[0034] The channel structure 126 extends vertically through the memory stack 124 along the y-direction. The channel structure 126 can include a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some embodiments, the memory film is a composite layer including a tunnel layer, a memory layer (also referred to as a “charge trapping layer”), and a blocking layer. In some embodiments, the remaining space of the channel structure can be partially or fully filled with a fill layer including a dielectric material (e.g., silicon oxide). The channel structure 126 can have a cylindrical shape (e.g., a columnar shape). According to some implementations, the fill layer, the semiconductor channel, the tunnel layer, the memory layer, and the blocking layer are radially arranged from the middle of the column to the outer surface of the column in this order. The tunnel layer can include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film can include a silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide (ONO) composite layer.

[0035] In some embodiments, the peripheral device layer 114 can include one or more peripheral devices formed within the substrate 112 and configured to control and sense the 3D memory device 100. The peripheral devices can include any suitable digital, analog, and / or mixed-signal control and sensing circuitry for facilitating the operation of the 3D memory device 100, including but not limited to a page buffer, decoders (e.g., a row decoder and a column decoder), sense amplifiers, drivers (e.g., a word line driver), charge pumps, current or voltage references, or any active or passive components (e.g., transistors, diodes, resistors, or capacitors) of the circuitry.

[0036] In some embodiments, the peripheral device layer 114 includes transistors having a first source / drain terminal 128, a second source / drain terminal 130, and a gate terminal 132. The first source / drain terminal 128 can be electrically connected to the substrate 108 through a through-silicon contact (TSC) structure 134. In some embodiments, the first source / drain terminal 128 can be electrically connected to the substrate 108 through the TSC structure 134 and an interconnect structure 136. The TSC structure 134 can be disposed between the first semiconductor structure 102 and the second semiconductor structure 104, penetrating the substrate 112. The interconnect structure 136 can be formed within the first semiconductor structure 102, connecting source terminals of the memory array as an array common source (ACS). In other words, the ACS of the first semiconductor structure 102 is electrically connected to the first source / drain terminal 128 of the peripheral device layer 114 in the second semiconductor structure 104.

[0037] In some embodiments, the contact pad 118 can be electrically connected to the second source / drain terminal 130. In some embodiments, another TSC structure 138 can be further formed through the substrate 112 between the first semiconductor structure 102 and the second semiconductor structure 104, and the TSC structure 138 is electrically connected to at least one word line of the memory stack 124.

[0038] The peripheral device layer 114 can include transistors formed on the substrate 112, where the entirety or a portion of the transistors are formed within the substrate 112, e.g., all or a portion below a top surface of the substrate 112. According to some embodiments, the transistors are high speed by virtue of being fabricated with an advanced logic process, e.g., a 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc. technology node. It should be appreciated that in some embodiments, the peripheral device layer 114 can further include any other circuitry compatible with the advanced logic process, including logic circuitry such as processors and programmable logic devices (PLDs) or memory circuitry such as static random access memory (SRAM) and dynamic RAM (DRAM).

[0039] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer 116 above the peripheral device layer 114 to transfer signals to and from the peripheral device layer 114. The interconnect layer 116 can include a plurality of interconnects (also referred to herein as “contacts”), including lateral interconnect lines and vertical interconnect via (VIA) contacts. As used herein, the term interconnect can broadly include any suitable type of interconnect, such as, for example, mid-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also referred to as intermetal dielectric (IMD) layers) within which the interconnect lines and VIA contacts can be formed. That is, the interconnect layer can include interconnect lines and VIA contacts within a plurality of ILD layers. The interconnect lines and VIA contacts within the interconnect layer can be of an electrically conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers in the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0040] In some embodiments, the peripheral device layer 114 is disposed between the memory array structure 110 and the contact pad 118, and BEOL interconnects of the non-monolithic 3D memory device can be formed on the contact pad 118. It should be appreciated that in some embodiments, the 3D memory device 100 (including the first semiconductor structure 102 and the second semiconductor structure 104) can be flipped over, and the peripheral device layer 114 can be disposed underneath the memory array structure 110. In this case, BEOL interconnects of the non-monolithic 3D memory device can be formed underneath the contact pad 118 below the peripheral device layer 114.

[0041] Figures 2-13 Cross-sectional views of the 3D memory device 100 at different stages of a fabrication process are shown in accordance with some aspects of the present disclosure. Figure 14 A flowchart of an exemplary method 200 for forming the 3D memory device 100 in accordance with some aspects of the present disclosure is shown. For a better understanding of the present disclosure, the cross-sectional views of the 3D memory device 100 in Figures 2-13 are discussed in conjunction with the method 200. Figure 14 It should be appreciated that the operations shown in the method 200 are not exclusive and other operations can be performed either before, after, or between any of the illustrated operations. Moreover, some of the operations can be performed simultaneously or in a different order than shown in the method 200. Figures 2-13 and Figure 14 are shown.

[0042] As Figure 2and Figure 14 As shown in operation 202, a memory array structure 110 is formed on a first doped semiconductor layer (e.g., substrate 108), which includes single crystalline silicon.

[0043] To form the memory array structure 110 on the substrate 108, in some embodiments, a dielectric stack extending in the x-direction is formed, which includes a plurality of dielectric layers and a plurality of sacrificial layers alternating on the substrate 108. A channel structure 126 extending vertically through the dielectric stack and in contact with the substrate 108 is formed. Thereafter, the plurality of sacrificial layers is replaced with a plurality of conductive layers to form word lines. In some embodiments, each dielectric layer can include a layer of silicon oxide, and each sacrificial layer can include a layer of silicon nitride. The dielectric stack can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, a pad oxide layer (not shown) is formed between the substrate 108 and the dielectric stack by depositing a dielectric material (e.g., silicon oxide) on the substrate 108.

[0044] The channel structure 126 extending vertically through the dielectric stack in the y-direction is formed. In some embodiments, an etching process can be performed to form channel holes extending vertically through the alternating dielectric layers / sacrificial layers within the dielectric stack. In some embodiments, the fabrication process for forming the channel holes includes wet etching and / or dry etching, e.g., deep ion reactive etching (DRIE). In some embodiments, the channel holes can further extend into a top portion of the substrate 108. The etching process through the dielectric stack can not stop at the top surface of the substrate 108 and can continue to etch away portions of the substrate 108. After the channel holes are formed, an epitaxy operation (e.g., a selective epitaxial growth operation) can be performed to form channel contacts on the bottom of the channel holes. Thereafter, a semiconductor channel and a memory film including a tunnel layer, a memory layer, and a blocking layer can be formed on the channel contacts. In some embodiments, the channel structure 126 can not include channel contacts.

[0045] In some other embodiments, to form the memory array structure 110 on the substrate 108, a stack structure including a plurality of word lines is formed on the substrate 108. Thereafter, a channel structure 126 extending vertically through the stack structure and in contact with the substrate 108 is formed.

[0046] As Figure 3 and Figure 14As shown in operation 204, a second doped semiconductor layer, such as substrate 112, is formed on the memory array structure 110. The second doped semiconductor layer comprises single-crystal silicon. The first semiconductor structure 102 includes a dielectric layer 120 formed on the memory array structure 110, and the dielectric layer 120 is bonded to the dielectric layer 122. Figure 3 As shown, a bonding interface 106 is formed on the bonding surface between dielectric layer 120 and dielectric layer 122.

[0047] In some embodiments, bonding the substrate 112 to the dielectric layer 120 may include Figures 4-7 The series of operations shown. In Figures 4-7 In this process, a single-crystal silicon layer (substrate 112) is transferred from substrate 140 (donor substrate) onto dielectric layer 120, for example, using a de-bonding process. Figure 15 This is a flowchart of an exemplary method 300 for transferring a single-crystal silicon layer according to some aspects of this disclosure.

[0048] like Figure 4 as well as Figure 15 As shown in operation 302, a substrate 140 including a dielectric layer 122 is provided, and then the substrate 140 is bonded to the memory array structure 110, as follows: Figure 5 As shown in the figure. Substrate 140 includes a single-crystal silicon layer. A bonding interface 106 is formed on the bonding surface between dielectric layer 120 and dielectric layer 122.

[0049] like Figure 6 as well as Figure 15As shown in operation 304, a heterostructure 142 is formed within the substrate 140. In some embodiments, an ion implantation process is performed within the substrate 140 to form the heterostructure 142, which separates the doped single-crystal silicon layer (substrate 112) from the remainder of the substrate 140. In some embodiments, the dopant is hydrogen, including hydrogen ions and / or hydrogen atoms. It should be understood that any other dopant capable of forming the heterostructure 142 within the substrate 140 may also be used. For example, light ion implantation can be used to implant light ions such as protons or helium ions into the substrate 112, which can then be removed from the substrate 112. The thickness of the substrate 112, i.e., the distance along the y-direction between the heterostructure 142 and the bonding interface 106, can be controlled by various parameters of ion implantation, such as energy, dopant, dose, time, etc., and post-annealing parameters, such as the temperature and time of thermal diffusion immediately following ion implantation. In some embodiments, the thickness of substrate 112 is between approximately 1 μm and approximately 100 μm, for example, between 1 μm and 100 μm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, any range defined by the lower end and any of these values, or any range defined by any two of these values). Thickness uniformity can be controlled by fine-tuning the implanted dopant over the entire surface of substrate 140.

[0050] like Figure 6 As shown, heterojunction 142 is an interface within substrate 140 between two layers of different materials, such as hydrogen-implanted monocrystalline silicon and undoped monocrystalline silicon. The presence of heterojunction 142 within substrate 140 facilitates the separation of the two material layers (e.g., substrate 112 and the remainder of substrate 140) during subsequent debonding processes.

[0051] like Figure 7 as well as Figure 15 As shown in operation 306, the remainder of substrate 140 is removed from substrate 112 along heterojunction 142. Substrate 112 is thus formed on memory array structure 110, and substrate 112 is doped single-crystal silicon, such as... Figure 3 As shown in the diagram, the remainder of substrate 140 is peeled off from substrate 112 along heterojunction 142 within substrate 140, leaving substrate 112 intact. Substrate 112 remains bonded to memory array structure 110.

[0052] likeFigures 8-10 As shown in FIG. 1 14, the substrate 140 is peeled off from the substrate 1 12 along the hetero-interface 142 by applying a mechanical force to the substrate 140, for example, because the bonding strength at the bonding interface 106 is greater than the splitting force at the hetero-interface 142. In other words, the substrate 140 can be broken and peeled off from the substrate 1 12 along the hetero-interface 142. Thus, the substrate 1 12 is transferred from its donor substrate (i.e., the substrate 140) onto the memory array structure 1 10 using the debonding process as described above. In some embodiments, after the substrate 140 is peeled off from the substrate 1 12, a planarization operation, such as a CMP process, can be further performed on the surface of the substrate 1 12 to smooth the surface of the substrate 1 12.

[0053] In some embodiments, bonding the substrate 1 12 onto the dielectric layer 120 can include Figures 8-10 In some embodiments, the substrate 1 12 is transferred from the composite substrate 144 onto the dielectric layer 120. Figure 16 In some embodiments, the substrate 1 12 is transferred from the composite substrate 144 onto the dielectric layer 120. Figure 8 is a flowchart of an exemplary method 400 for transferring a single crystal silicon layer according to some aspects of the present disclosure.

[0054] As shown in operation 402 of FIG. 4, a composite substrate 144 is provided, and then the composite substrate 144 is bonded onto the memory array structure 1 10 as shown in FIG. 1 14. Figure 16 In some embodiments, the composite substrate 144 can be fabricated independently from a semiconductor substrate that is a silicon wafer (e.g., a silicon-on-insulator (SOI) wafer). For example, a wafer composed of single crystal silicon can be first provided by cutting from a large cylindrical ingot of silicon. A high-energy ion implantation can be performed on the wafer to form an oxygen-rich layer within the wafer, which is then oxidized to form the insulating layer 148 (e.g., a silicon oxide layer). In some embodiments, oxygen is implanted into the single crystal silicon wafer and converted into a buried layer of silicon dioxide (the insulating layer 148). The dielectric layer 122 (e.g., a silicon oxide layer) can be further formed on the single crystal silicon layer 146. Thus, the composite substrate 144 including heterogeneous materials (e.g., single crystal silicon, silicon oxide, etc.) is obtained. Figure 9 Figure 10 The composite substrate 144 is bonded to the first semiconductor structure 102 in a face-to-face manner, in which the dielectric layer 120 and the dielectric layer 122 are bonded together, and the bonding interface 106 is formed on the bonding surface between the dielectric layer 120 and the dielectric layer 122.

[0055] As shown in operation 402 of FIG. 4, a composite substrate 144 is provided, and then the composite substrate 144 is bonded onto the memory array structure 1 10 as shown in FIG. 1 14.

[0056] As shown in operation 402 of FIG. 4, a composite substrate 144 is provided, and then the composite substrate 144 is bonded onto the memory array structure 1 10 as shown in FIG. 1 14. Figure 16 and​Figure 3 As shown in operation 404 of FIG. 4, portions of the composite substrate 144 are removed to form the doped semiconductor layer (substrate 112). In some embodiments, portions of the composite substrate 144 including the sacrificial layer 150 and the insulating layer 148 can be broken and peeled off from the rest of the composite substrate 144 during a debonding process along a hetero-interface separating the layers with heterogeneous materials (e.g., the interface between the insulating layer 148 and the single-crystalline silicon layer 146). Thus, only the single-crystalline silicon layer 146 is left on top of the dielectric layers 122 and 120. The remaining portions of the single-crystalline silicon layer 146 form the substrate 112, and the substrate 112 is a doped single-crystalline silicon, as shown in FIG. 1. Figure 11

[0057] As shown in operation 206 of FIG. 2, the peripheral device layer 114 is formed within the substrate 112. The peripheral device layer 114 can include a plurality of peripheral circuits electrically connected to the memory array structure 110 through the later-formed interconnect layer 116. In some embodiments, the peripheral device layer 114 can include a plurality of transistors, as shown in FIG. 3. Each transistor can include a first source / drain terminal 128, a second source / drain terminal 130, and a gate terminal 132 formed within the substrate 112 as doped regions. In some embodiments, isolation regions (e.g., STI) are also formed within the substrate 112 by wet etching and / or dry etching and thin film deposition. These transistors can form the peripheral circuits within the peripheral device layer 114. In some embodiments, two transistors with different doping types can form a CMOS structure, as shown in FIG. 4. Figure 14 Figure 11 Figure 11 Figure 12

[0058] In some embodiments, TSC structures 134 and 138 can also be formed within the substrate 112 and pass through the substrate 112 to the first semiconductor structure 102. The TSC structures 134 and 138 can provide electrical connections between components made of heterogeneous materials, for example, to combine the peripheral circuits with the memory cells. In some embodiments, the TSC structures 134 and 138 can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof.

[0059] Figure 14 Figure 13 ​​​​​​​As shown in operation 208, an interconnect layer 116 is formed on the peripheral device layer 114. The interconnect layer 116 may be above and electrically connected to the second source / drain terminal 130 to enable pad take-off, for example, to transmit electrical signals between the 3D memory device 100 and external circuitry. The interconnect layer 116 may further electrically connect the first source / drain terminal 128 and the TSC structure 134. In some embodiments, the interconnect layer 116 may further connect multiple peripheral devices within the 3D memory device 100. In some embodiments, the interconnect layer 116 may include one or more interlayer dielectric (ILD) layers and one or more redistribution layers disposed within the ILD layers for electrically connecting devices. The ILD layers may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The redistribution layers may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof.

[0060] like Figure 14 as well as Figure 19 As shown in operation 210, contact pads 118 are formed on the peripheral device layer 114. The contact pads 118 are electrically contacted with the second source / drain terminals 130 via interconnect layer 116. The peripheral device layer 114, including one or more peripheral devices, is disposed between the contact pads 118 and the memory array structure 110. In other words, the 3D memory device 100 is a core-under-periphery (CUP) structure, and the pads of this structure are led out from the top of the peripheral devices. Furthermore, the active layers of the peripheral devices (e.g., the substrate 112 of the peripheral device layer 114) are bonded to the first semiconductor structure 102 via transfer bonding methods 300 or 400, and the peripheral devices can be electrically connected to the memory array structure 110 via TSC structures 134 or 138. Since the peripheral device layer 114 is bonded to the memory array structure 110 after the fabrication process of the memory array structure 110 is completed, the peripheral devices in the peripheral device layer 114 can avoid being subjected to the high temperatures typically used during the fabrication process of the memory array structure 110. Therefore, the reliability of peripheral devices can be improved, and more options are available for the conductive materials used in the peripheral devices. For example, since the peripheral devices will not be processed at high temperatures, the conductive lines or layers in the peripheral device 114 or the interconnect layer 116 can be formed of Cu to improve the reliability and performance of the 3D memory device 100.

[0061] Figure 19 A cross-sectional view of another exemplary 3D memory device 700 according to some aspects of this disclosure is shown. Figure 13 The 3D memory device 700 shown is Figure 19The difference between the 3D memory devices 100 shown in FIGS. 1A-1C is in the pad-out structure. As shown in FIG. 1A, the contact pads 106 are electrically coupled to the first source / drain terminal 128 through the TSC structure 134 and the interconnect structure 136. Figure 19 As shown in FIG. 1C, the contact pads 706 and the contact pads 708 are disposed underneath the first semiconductor structure 102. To form the contact pads 706 and the contact pads 708, the substrate 108 can be thinned to expose the contact pads 706 and the contact pads 708. Figure 17 As shown in FIG. 1C, the contact pads 706 and the contact pads 708 are disposed underneath the first semiconductor structure 102. To form the contact pads 706 and the contact pads 708, the substrate 108 can be thinned to expose the contact pads 706 and the contact pads 708.

[0062] Thereafter, the interconnect layer 704 can be formed over the substrate 108. The interconnect layer 704 can include the contact pads 706 electrically coupled to the substrate 108 through the interconnect layer 704. The interconnect layer 704 can further include the contact pads 708 electrically coupled to the first source / drain terminal 128 through the TSC structure 134, the interconnect structure 136, and the interconnect layer 704.

[0063] Figure 17 A block diagram illustrating an exemplary system 500 having a memory device in accordance with some aspects of the present disclosure is shown. The system 500 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device located therein. As shown in FIG. 5, the system 500 can include a host 508 and a memory system 502 having one or more memory devices 504 and a memory controller 506. The host 508 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system on a chip (SoC), such as an application processor (AP). The host 508 can be configured to send or receive data to or from the memory device 504. Figure 18A As shown in FIG. 1C, the contact pads 706 and the contact pads 708 are disposed underneath the first semiconductor structure 102. To form the contact pads 706 and the contact pads 708, the substrate 108 can be thinned to expose the contact pads 706 and the contact pads 708.

[0064] The memory device 504 can be any memory device disclosed in the present disclosure. As disclosed in detail above, the memory device 504 (e.g., a NAND flash memory device) can have a controlled predefined discharge current in a discharge operation to discharge a bit line. According to some embodiments, a memory controller 506 is coupled to the memory device 504 and the host 508, and is configured to control the memory device 504. The memory controller 506 can manage data stored in the memory device 504, and communicate with the host 508. For example, the memory controller 506 can be coupled to the memory device 504 (e.g., the 3D memory device 100 described above), and the memory controller 506 can be configured to control the operation of the memory array structure 110 through the peripheral device layer 114, the interconnect layer 116, and the contact pad 118. By forming the structure according to the present disclosure, the pad-out of signals to the 3D memory device 100 from the upper side of the peripheral device is enabled. In addition, the reliability of the peripheral device can be improved, and the conductive material used in the peripheral device can also have more options.

[0065] In some embodiments, the memory controller 506 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 506 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc. as well as enterprise storage arrays. The memory controller 506 can be configured to control operations of the memory device 504, such as read, erase, and program operations. The memory controller 506 can also be configured to manage various functions related to data stored in or to be stored in the memory device 504, including but not limited to bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 506 is further configured to process error-correcting codes (ECC) related to data read from or written to the memory device 504. Any other suitable functions can also be performed by the memory controller 506, for example, formatting the memory device 504. The memory controller 506 can communicate with external devices (e.g., the host 508) according to a particular communication protocol. For example, the memory controller 506 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0066] The memory controller 506 and one or more memory devices 504 can be integrated into various types of memory devices, for example, contained within the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 502 can be implemented and packaged into different types of final electronic products. In one example as shown, the memory controller 506 and a single memory device 504 can be integrated into a memory card 602. The memory card 602 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), a SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 602 can further include a connector to connect the memory card 602 with a host (e.g., a memory card reader), a card controller, a buffer, etc. The memory card 602 can be used in various electronic devices, such as a digital still camera, a digital video camera, a personal computer, a mobile phone, a tablet, etc. Figure 17 The memory controller 506 and one or more memory devices 504 can be integrated into various types of memory devices, for example, contained within the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 502 can be implemented and packaged into different types of final electronic products. In one example as shown, the memory controller 506 and a single memory device 504 can be integrated into a memory card 602. The memory card 602 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), a SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 602 can further include a connector to connect the memory card 602 with a host (e.g., a memory card reader), a card controller, a buffer, etc. The memory card 602 can be used in various electronic devices, such as a digital still camera, a digital video camera, a personal computer, a mobile phone, a tablet, etc.Figure 18B The memory card connector 604 is coupled to the memory card 602. In some embodiments, the memory card 602 is a removable memory card (e.g., a removable memory card that is removable from the host 508). In some embodiments, the memory card 602 is a non-removable memory card (e.g., a non-removable memory card that is not removable from the host 508). Figure 17 In another example as shown, the memory controller 506 and the plurality of memory devices 504 can be integrated into an SSD 606. The SSD 606 can further include an SSD connector 608 that couples the SSD 606 to a host (e.g., the host 508). In some embodiments, the storage capacity and / or operating speed of the SSD 606 is higher than the storage capacity and / or operating speed of the memory card 602. ​ In another example as shown, the memory controller 506 and the plurality of memory devices 504 can be integrated into an SSD 606. The SSD 606 can further include an SSD connector 608 that couples the SSD 606 to a host (e.g., the host 508). In some embodiments, the storage capacity and / or operating speed of the SSD 606 is higher than the storage capacity and / or operating speed of the memory card 602.

[0067] According to one aspect of the present disclosure, a 3D memory device is disclosed. The 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed over the first semiconductor structure, and the second semiconductor structure includes a second substrate and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.

[0068] In some embodiments, an interconnect layer is disposed over the second semiconductor structure. The memory array structure is disposed between the interconnect layer and the first substrate. A contact pad of the interconnect layer is electrically coupled to the peripheral device. In some embodiments, an interconnect layer is disposed over the first semiconductor structure. The second substrate is disposed between the interconnect layer and the peripheral device. A contact pad of the interconnect layer is electrically coupled to the peripheral device.

[0069] In some embodiments, the memory array structure further includes a memory stack having a plurality of alternating conductive layers and dielectric layers, and a channel structure extending through the memory stack. The channel structure includes a memory film and a semiconductor channel, and the semiconductor channel is in contact with the first substrate.

[0070] In some embodiments, a first through-silicon contact structure passes through the second substrate, and the first substrate is electrically coupled to the peripheral device through the first through-silicon contact structure. In some embodiments, the peripheral device further includes a transistor, and the first substrate is electrically coupled to a first source / drain terminal of the transistor through the first through-silicon contact structure.

[0071] In some embodiments, the contact pad is electrically coupled to a second source / drain terminal of the transistor. In some embodiments, a second through-silicon contact structure passes through the second substrate. The memory array structure is electrically coupled to the peripheral device through the second through-silicon contact structure.

[0072] In some embodiments, the first through-si contact structure, the second through-si contact structure, and the interconnect layer are formed of copper (Cu). In some embodiments, a bonding interface is formed between the first semiconductor structure and the second semiconductor structure. In some embodiments, the first substrate comprises a single crystalline silicon layer. In some embodiments, the second substrate comprises a single crystalline silicon layer.

[0073] According to another aspect of the present disclosure, a system is disclosed. The system includes a 3D memory device configured to store data and a memory controller. The 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed above the first semiconductor structure, and the second semiconductor structure includes a second substrate and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure. The memory controller is coupled to the 3D memory device and configured to control operations of the 3D memory device.

[0074] According to yet another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A memory array structure is formed over a first substrate. A second substrate is formed over the memory array structure. A peripheral device is formed in contact with the second substrate. An interconnect layer is formed over the peripheral device. The second substrate is disposed between the peripheral device and the memory array structure.

[0075] In some embodiments, a contact pad is embedded within the interconnect layer. The contact pad is in contact with the peripheral device. In some embodiments, the contact pad is formed over the first substrate. The first substrate is disposed between the contact pad and the memory array structure.

[0076] In some embodiments, a dielectric stack comprising a plurality of dielectric layers and a plurality of sacrificial layers alternating on the first substrate is formed, a channel structure extending vertically through the dielectric stack and in contact with the first substrate is formed, and a plurality of conductive layers is employed in place of the plurality of sacrificial layers.

[0077] In some embodiments, a stack structure comprising a plurality of word lines is formed on the first substrate, and a channel structure extending vertically through the stack structure and in contact with the first substrate is formed.

[0078] In some embodiments, a third substrate comprising a dielectric layer is provided, the third substrate is bonded to the memory array structure in a face-to-face manner via the dielectric layer, a hetero-interface is formed within the third substrate, and portions of the third substrate are removed along the hetero-interface to form the second substrate. In some embodiments, forming the hetero-interface within the third substrate comprises implanting dopants into the substrate. In some embodiments, the dopants comprise hydrogen.

[0079] In some embodiments, a composite substrate is bonded to the memory array structure, and portions of the composite substrate are removed to form the second substrate. In some embodiments, the composite substrate comprises a silicon-on-insulator (SOI) substrate including a single crystalline silicon layer, an insulating layer, and a single crystalline silicon substrate. In some embodiments, the single crystalline silicon substrate and the insulating layer above the single crystalline silicon layer are removed from the composite substrate to form the second substrate.

[0080] In some embodiments, a transistor is formed within the second substrate, the transistor including a gate structure, a first source / drain terminal, and a second source / drain terminal. In some embodiments, a first through-silicon contact structure is formed through the second substrate. The peripheral device is electrically coupled to the first substrate through the first through-silicon contact structure. In some embodiments, the first source / drain terminal and the first substrate are electrically connected through the first through-silicon contact structure.

[0081] In some embodiments, a second through-silicon contact structure is formed through the second substrate. The peripheral device is electrically coupled to a word line of the memory array structure through the second through-silicon contact structure. In some embodiments, a contact pad is formed over the transistor and is electrically connected to the second source / drain terminal.

[0082] According to yet another aspect of the disclosure, a method for forming a 3D memory device is disclosed. A first dielectric layer is formed over a first substrate. A memory array structure is formed within the first dielectric layer. A second substrate is bonded to the first dielectric layer. The second substrate includes a second dielectric layer, and the second dielectric layer is bonded to the first dielectric layer. A hetero-interface is formed within the second substrate. Portions of the second substrate are removed along the hetero-interface, thereby forming a third substrate over the memory array structure. A peripheral device is formed within the third substrate. An interconnect layer is formed over the peripheral device. The third substrate is disposed between the peripheral device and the memory array structure.

[0083] In some embodiments, a dielectric stack including a plurality of dielectric layers and a plurality of sacrificial layers alternating on the first substrate is formed, a channel structure extending vertically through the dielectric stack and in contact with the first substrate is formed, and a plurality of conductive layers is employed in place of the plurality of sacrificial layers.

[0084] In some embodiments, a stack structure including a plurality of word lines is formed on the first substrate, and a channel structure extending vertically through the stack structure and in contact with the first substrate is formed.

[0085] In some embodiments, forming a hetero-interface within the second substrate includes implanting dopants into the second substrate. In some embodiments, the dopants include hydrogen.

[0086] In some embodiments, a transistor is formed within a third substrate. The transistor includes a gate structure, a first source / drain terminal, and a second source / drain terminal. In some embodiments, a first through-silicon via structure is formed through the third substrate. A peripheral device is electrically coupled to the first substrate through the first through-silicon via structure. In some embodiments, the first source / drain terminal and the first substrate are electrically connected by the first through-silicon via structure.

[0087] In some embodiments, a second through-silicon via structure is formed through the third substrate. A peripheral device is electrically coupled to a word line of the memory array structure through the second through-silicon via structure. In some embodiments, a contact pad is embedded within the interconnect layer. The contact pad is in contact with the peripheral device. In some embodiments, the contact pad is formed over the transistor, and the contact pad electrically connects the second source / drain terminal.

[0088] According to yet another aspect of the disclosure, a method for forming a 3D memory device is disclosed. A first dielectric layer is formed over a first substrate. A memory array structure is formed within the first dielectric layer. A composite substrate is bonded to the first dielectric layer. The composite substrate includes a second dielectric layer, and the second dielectric layer is bonded to the first dielectric layer. Portions of the composite substrate are removed, thereby forming a second substrate over the memory array structure. A peripheral device is formed within the second substrate. An interconnect layer is formed over the peripheral device. The second substrate is disposed between the peripheral device and the memory array structure.

[0089] In some embodiments, a dielectric stack including a plurality of dielectric layers and a plurality of sacrificial layers alternating on the first substrate is formed, a channel structure extending vertically through the dielectric stack and in contact with the first substrate is formed, and a plurality of electrically conductive layers is employed in place of the plurality of sacrificial layers.

[0090] In some embodiments, a stack structure including a plurality of word lines is formed on the first substrate, and a channel structure extending vertically through the stack structure and in contact with the first substrate is formed.

[0091] In some embodiments, the composite substrate further includes a silicon-on-insulator (SOI) substrate including a single-crystal silicon layer, an insulating layer, and a single-crystal silicon substrate. In some embodiments, the single-crystal silicon substrate and the insulating layer above the single-crystal silicon layer are removed from the composite substrate to form the second substrate.

[0092] In some embodiments, a transistor is formed within the second substrate. The transistor includes a gate structure, a first source / drain terminal, and a second source / drain terminal. In some embodiments, a first through-silicon contact structure is formed through the second substrate. The peripheral device is electrically coupled to the first substrate through the first through-silicon contact structure. In some embodiments, the first source / drain terminal and the first substrate are electrically connected through the first through-silicon contact structure.

[0093] In some embodiments, a second through-silicon contact structure is formed through the second substrate. The peripheral device is electrically coupled to a word line of the memory array structure through the second through-silicon contact structure. In some embodiments, a contact pad is embedded within the interconnect layer. The contact pad is in contact with the peripheral device. In some embodiments, the contact pad is formed over the transistor, and the contact pad electrically connects the second source / drain terminal.

[0094] The foregoing description of specific embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed, and various modifications and / or adjustments as described herein can be suggested to practitioners in the art, based on the teaching and guidance presented herein.

[0095] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: A first semiconductor structure includes a first substrate and a memory array structure disposed on the first substrate, wherein the first substrate includes a source terminal serving as a common source of the array; A second semiconductor structure disposed on the first semiconductor structure, the second semiconductor structure including a second substrate and peripheral devices in contact with the second substrate; and The first through-silicon contact structure passes through the second substrate, and the source terminal in the first substrate is electrically coupled to the peripheral device through the first through-silicon contact structure. The second substrate is formed between the peripheral device and the first semiconductor structure.

2. The 3D memory device according to claim 1, further comprising: An interconnect layer disposed on the second semiconductor structure, The memory array structure is disposed between the interconnect layer and the first substrate; and The contact pads of the interconnect layer are electrically coupled to the peripheral device.

3. The 3D memory device according to claim 1, further comprising: The interconnect layer disposed on the first semiconductor structure, The second substrate is disposed between the interconnect layer and the peripheral device; and The contact pads of the interconnect layer are electrically coupled to the peripheral device.

4. The 3D memory device according to any one of claims 1-3, wherein, The memory array structure further includes: A memory stack having multiple alternating conductive and dielectric layers; and A channel structure extending through the memory stack, the channel structure including a memory film and a semiconductor channel; The semiconductor channel is in contact with the first substrate.

5. The 3D memory device according to claim 3, wherein, The peripheral device further includes a transistor, and the first substrate is electrically coupled to the first source / drain terminal of the transistor through the first through-silicon contact structure.

6. The 3D memory device according to claim 5, wherein, The contact pads are electrically coupled to the second source / drain terminals of the transistor.

7. The 3D memory device of claim 6, further comprising a second through-silicon contact structure passing through the second substrate, and the memory array structure being electrically coupled to the peripheral device via the second through-silicon contact structure.

8. The 3D memory device according to claim 7, wherein, The first through-silicon contact structure, the second through-silicon contact structure, and the interconnect layer are formed of copper (Cu).

9. The 3D memory device of claim 1, further comprising a bonding interface between the first semiconductor structure and the second semiconductor structure.

10. The 3D memory device according to any one of claims 1-3, wherein, The first substrate comprises a single-crystal silicon layer.

11. The 3D memory device according to claim 10, wherein, The second substrate comprises a single-crystal silicon layer.

12. A system comprising: A three-dimensional (3D) memory device configured to store data, the 3D memory device comprising: A first semiconductor structure includes a first substrate and a memory array structure disposed on the first substrate, wherein the first substrate includes a source terminal serving as a common source of the array; A second semiconductor structure disposed on the first semiconductor structure, the second semiconductor structure including a second substrate and peripheral devices in contact with the second substrate; and The first through-silicon contact structure passes through the second substrate, and the source terminal in the first substrate is electrically coupled to the peripheral device through the first through-silicon contact structure. Wherein, the second substrate is formed between the peripheral device and the first semiconductor structure; and A memory controller coupled to the 3D memory device and configured to control the operation of the 3D memory device.

13. A method for forming a three-dimensional (3D) memory device, comprising: A memory array structure is formed on the first substrate; A second substrate is formed on the memory array structure; Forming peripheral devices that are in contact with the second substrate; A first through-silicon contact structure is formed through the second substrate; as well as An interconnect layer is formed on the peripheral device, wherein the first substrate includes a source terminal as a common source of the array, wherein the peripheral device is electrically coupled to the source terminal in the first substrate through a first through-silicon contact structure, and wherein the second substrate is disposed between the peripheral device and the memory array structure.

14. The method of claim 13, further comprising: Contact pads are formed embedded in the interconnect layer, wherein the contact pads are in contact with the peripheral devices.

15. The method of claim 13, further comprising: Contact pads are formed on the first substrate, wherein the first substrate is disposed between the contact pads and the memory array structure.

16. The method according to any one of claims 13-15, wherein, Forming the memory array structure on the first substrate further includes: A dielectric stack comprising alternating dielectric layers and sacrificial layers on the first substrate is formed; Forming a channel structure that extends vertically through the dielectric stack and contacts the first substrate; and Multiple conductive layers are used instead of the multiple sacrificial layers.

17. The method according to any one of claims 13-15, wherein, Forming the memory array structure on the first substrate further includes: A multilayer structure including multiple word lines is formed on the first substrate; and A channel structure is formed that extends vertically through the stacked structure and contacts the first substrate.

18. The method according to any one of claims 13-15, wherein, Forming the second substrate on the memory array structure further includes: Provide a third substrate including a dielectric layer; The third substrate is bonded to the memory array structure via the dielectric layer in a face-to-face manner; A heterogeneous interface is formed within the third substrate; and A portion of the third substrate is removed along the heterogeneous interface to form the second substrate.

19. The method according to claim 18, wherein, Forming the heterostructure within the third substrate includes implanting a dopant into the third substrate.

20. The method according to claim 19, wherein, The dopant includes hydrogen.

21. The method according to any one of claims 13-15, wherein, Forming the second substrate on the memory array structure further includes: Bonding the composite substrate to the memory array structure; and A portion of the composite substrate is removed to form the second substrate.

22. The method according to claim 21, wherein, The composite substrate includes a silicon-on-insulator (SOI) substrate, which includes a single-crystal silicon layer, an insulating layer, and a single-crystal silicon substrate.

23. The method according to claim 22, wherein, Removing a portion of the composite substrate to form the second substrate further includes: The monocrystalline silicon substrate and the insulating layer above the monocrystalline silicon layer are removed from the composite substrate to form the second substrate.

24. The method according to any one of claims 14, wherein, The peripheral device forming contact with the second substrate further includes: A transistor is formed within the second substrate, the transistor including a gate structure, a first source / drain terminal, and a second source / drain terminal.

25. The method according to claim 24, wherein, Forming the interconnect layer over the peripheral device further includes: The first source / drain terminals and the first substrate are electrically connected through the first through-silicon contact structure.

26. The method of claim 13, further comprising: Forming a second through-silicon contact structure that penetrates the second substrate. The peripheral devices are electrically coupled to the word lines of the memory array structure through the second through-silicon contact structure.

27. The method according to claim 24, wherein, Forming the contact pads on the interconnect layer further includes: The contact pads are formed on the transistor and electrically connected to the second source / drain terminals.

28. A method for forming a three-dimensional (3D) memory device, comprising: A first dielectric layer is formed on a first substrate; A memory array structure is formed within the first dielectric layer; A second substrate is bonded to the first dielectric layer, wherein the second substrate includes a second dielectric layer, and the second dielectric layer is bonded to the first dielectric layer; A heterogeneous interface is formed within the second substrate; A portion of the second substrate is removed along the heterogeneous interface to form a third substrate on the memory array structure; Peripheral devices are formed within the third substrate; Forming a first through-silicon contact structure through the second substrate; and An interconnect layer is formed on top of the peripheral devices. The first substrate includes a source terminal serving as a common source of the array, wherein the peripheral device is electrically coupled to the source terminal in the first substrate through the first through-silicon contact structure, and wherein the third substrate is disposed between the peripheral device and the memory array structure.

29. The method according to claim 28, wherein, Forming the memory array structure within the first dielectric layer further includes: A dielectric stack comprising alternating dielectric layers and sacrificial layers on the first substrate is formed; Forming a channel structure that extends vertically through the dielectric stack and contacts the first substrate; and Multiple conductive layers are used instead of the multiple sacrificial layers.

30. The method according to claim 28, wherein, Forming the memory array structure within the first dielectric layer further includes: A multilayer structure including multiple word lines is formed on the first substrate; and A channel structure is formed that extends vertically through the stacked structure and contacts the first substrate.

31. The method according to any one of claims 28-30, wherein, Forming the heterostructure within the second substrate includes implanting a dopant into the second substrate.

32. The method according to claim 31, wherein, The dopant includes hydrogen.

33. The method according to any one of claims 28-30, wherein, Forming the peripheral device within the third substrate further includes: A transistor is formed within the third substrate, the transistor including a gate structure, a first source / drain terminal, and a second source / drain terminal.

34. The method of claim 33, further comprising: The first source / drain terminals and the first substrate are electrically connected through the first through-silicon contact structure.

35. The method of claim 28, further comprising: A second through-silicon contact structure is formed through the third substrate. The peripheral devices are electrically coupled to the word lines of the memory array structure through the second through-silicon contact structure.

36. The method of claim 33, further comprising: Contact pads are formed embedded in the interconnect layer, wherein the contact pads are in contact with the peripheral devices.

37. The method of claim 36, wherein, Forming the contact pads on the interconnect layer further includes: Contact pads are formed on the transistor and electrically connected to the second source / drain terminals.

38. A method for forming a three-dimensional (3D) memory device, comprising: A first dielectric layer is formed on a first substrate; A memory array structure is formed within the first dielectric layer; A composite substrate is bonded to the first dielectric layer, wherein the composite substrate includes a second dielectric layer, and the second dielectric layer is bonded to the first dielectric layer; A portion of the composite substrate is removed, thereby forming a second substrate on the memory array structure; Peripheral devices are formed within the second substrate; Forming a first through-silicon contact structure through the second substrate; and An interconnect layer is formed on top of the peripheral devices. The first substrate includes a source terminal serving as a common source of the array, wherein the peripheral device is electrically coupled to the source terminal in the first substrate through the first through-silicon contact structure, and wherein the second substrate is disposed between the peripheral device and the memory array structure.

39. The method according to claim 38, wherein, Forming the memory array structure within the first dielectric layer further includes: A dielectric stack comprising alternating dielectric layers and sacrificial layers on the first substrate is formed; Forming a channel structure that extends vertically through the dielectric stack and contacts the first substrate; and Multiple conductive layers are used instead of the multiple sacrificial layers.

40. The method of claim 38, wherein, Forming the memory array structure within the first dielectric layer further includes: A multilayer structure including multiple word lines is formed on the first substrate; and A channel structure is formed that extends vertically through the stacked structure and contacts the first substrate.

41. The method according to any one of claims 38-40, wherein, The composite substrate further includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a single-crystal silicon layer, an insulating layer, and a single-crystal silicon substrate.

42. The method according to claim 41, wherein, Removing a portion of the composite substrate to form the second substrate over the memory array structure further includes: The monocrystalline silicon substrate and the insulating layer above the monocrystalline silicon layer are removed from the composite substrate to form the second substrate.

43. The method according to any one of claims 38-40, wherein, Forming the peripheral device within the second substrate further includes: A transistor is formed within the second substrate, the transistor including a gate structure, a first source / drain terminal, and a second source / drain terminal.

44. The method of claim 43, further comprising: The first source / drain terminals and the first substrate are electrically connected through the first through-silicon contact structure.

45. The method of claim 38, further comprising: Forming a second through-silicon contact structure that penetrates the second substrate. The peripheral devices are electrically coupled to the word lines of the memory array structure through the second through-silicon contact structure.

46. ​​The method of claim 43, further comprising: Contact pads are formed embedded in the interconnect layer, wherein the contact pads are in contact with the peripheral devices.

47. The method according to claim 46, wherein, Forming the contact pads on the interconnect layer further includes: The contact pads are formed on the transistor and electrically connected to the second source / drain terminals.

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