Tunable Voltage Sensing Device Based on TDC and Its Calibration Tuning Method

Abstract

This invention provides a tunable voltage sensing device based on a phase-shifted clock (TDC) and its calibration and tuning method, comprising a TDC module, a clock module, and a register module. The clock module generates a pulse clock and a sampling clock. The TDC module generates a multi-edge pulse signal based on the pulse clock, which is transmitted on a delay chain and sampled by the sampling clock to obtain the measurement result. The register module configures and adjusts various parameters in the TDC module and the clock module. The voltage sensing device provided by this invention has high sensitivity and good deployability. Compared with common TDC voltage sensing devices, it adopts a multi-chain, multi-edge, and dual-sampling design, which greatly improves sensitivity, and utilizes a phase-shifted clock to enhance deployability.

Description

Technical Field

[0001] This invention relates to the technical field of information security for cloud FPGAs, specifically to a tunable voltage sensing device based on TDC and its calibration tuning method, and more particularly, preferably to a high-sensitivity tunable TDC voltage sensing device for remote power analysis attacks. Background Technology

[0002] With the rapid development of the global internet, cloud data centers are emerging. Due to the reconfigurable nature of FPGAs (Field-Programmable Gate Arrays), they are widely used in various embedded and cloud computing environments. Cloud FPGAs are typically multi-tenant, meaning that the FPGA's hardware resources can be shared by multiple users. By deploying voltage sensing devices on FPGAs, it is possible to eavesdrop on power leakage caused by surrounding computing and steal information through side-channel attacks using power analysis, posing security risks to data and even machine learning models in cloud services. In this type of Remote Power Analysis (RPA) attack, designing efficient and easily implemented on-chip voltage sensing devices is a core issue.

[0003] A Time-to-Digital Converter (TDC) is a circuit that converts analog time information into digital information. The dedicated carry-addition chain on an FPGA has a very small delay (approximately 4 ps per stage on a Xilinx 16nm FPGA), making it relatively easy to build high-resolution delay chains. TDC circuits designed using this method can effectively perform time measurement-related applications. Its basic principle is to record the number of stages of the rising (or falling) edge propagation of the input signal by sampling the tap value of each stage of the delay chain using the system clock. When the TDC and the attacked module share the power distribution network on the FPGA, the operations of the attacked module cause voltage fluctuations, affecting the carry-addition chain delay time and the number of stages of the input signal propagation in the delay chain, thus causing changes in the otherwise relatively stable TDC measurement value. Therefore, the TDC's time measurement can also reflect voltage changes, converting analog voltage information into digital information.

[0004] Chinese invention patent document CN109342807A discloses a voltage sensing device and detection method combining elastic-optical modulation and electro-optical modulation. Based on elastic-optical modulation technology, it achieves rapid and highly sensitive detection of the phase difference introduced by the voltage to be measured onto an electro-optical crystal, realizing real-time and fast voltage sensing. The electro-optical sensing element uses a uniaxial electro-optical crystal with light passing along the optical axis, improving the temperature stability of the voltage sensing device. Signal processing is implemented based on digital lock-in amplification technology. Signal acquisition and digital lock-in are both controlled by the same FPGA, and the input signal of the LC resonant high-voltage drive circuit of the elastic-optical modulator is also provided by the FPGA, ensuring that the reference signal and the modulation fundamental frequency signal are in sync and from the same source, thus improving the accuracy of signal processing.

[0005] Regarding the aforementioned technologies, the inventors believe that current FPGA on-chip voltage sensing devices mainly employ TDC circuits, often using only a single delay chain. This delay chain propagates only a rising (or falling) edge, resulting in insufficient sensitivity to voltage fluctuations. More power consumption traces need to be collected to complete an attack, a point more pronounced on advanced process FPGAs. Furthermore, since the voltage fluctuation time and clock period are in the nanosecond range, the clock phase between the sensing device and the attacked module also affects the signal-to-noise ratio of the sampled power consumption trace. This factor is typically not fixed during actual attacks. Under certain phases, the voltage sensing device collects less effective information. This factor is almost entirely ignored in existing designs. Additionally, in typical TDC voltage sensing devices, the signal propagating in the delay chain is a clock signal. Adjusting the clock phase and delay chain length is necessary to sample the clock signal edge on the delay chain to measure its propagation order. However, when FPGA process, temperature, voltage, or even the layout of the sensing device or PLL changes, repeated experiments are required for adjustment, resulting in poor deployability. Summary of the Invention

[0006] In view of the deficiencies in the prior art, the purpose of this invention is to provide a tunable voltage sensing device based on TDC and its calibration and tuning method.

[0007] A tunable voltage sensing device based on TDC according to the present invention includes a TDC module, a clock module and a register module;

[0008] The clock module generates a pulse clock and a sampling clock;

[0009] The TDC module generates multi-edge pulse signals based on the pulse clock, which are transmitted on the delay chain and sampled by the sampling clock to obtain the measurement results.

[0010] The register module configures and debugs the TDC module and the clock module.

[0011] Preferably, the TDC module includes a pulse generation circuit, a delay chain, a sampling circuit, and an encoding module;

[0012] The pulse generation circuit receives a pulse clock and generates a pulse signal that propagates on the delay chain.

[0013] The sampling circuit receives a sampling clock and samples the output on the delay chain in each cycle according to the sampling clock to obtain a sampled value;

[0014] The encoder module encodes the sampled values ​​to obtain the measurement results.

[0015] Preferably, the clock module includes cascaded clock generation units; the output clock of the preceding clock generation unit serves as the input clock of the following clock generation unit, and the clock phase of the voltage sensing device is dynamically adjusted by phase shift.

[0016] The subsequent clock generation unit generates a pulse clock and a sampling clock, dynamically shifting the phase of the pulse clock from the input pulse generation circuit to adjust the pulse phase.

[0017] Preferably, the pulse generation circuit includes a delay chain unit and an XOR gate;

[0018] The delay chain unit of the pulse generation circuit adjusts the number of stages of clock propagation in the delay chain unit by selecting a signal; when the clock reaches the XOR gate after different delays, pulse signals of different widths are generated at the clock edge.

[0019] Preferably, there are multiple delay chains, and the pulse generated by the XOR gate is input into each delay chain for propagation.

[0020] Preferably, the sampling circuit is a flip-flop array;

[0021] The delay unit taps at each stage of the delay chain are connected to triggers and sampled;

[0022] When the delay chain is implemented by the FPGA's add-carry chain, both the add output and carry output of the carry chain are connected to flip-flops and sampled.

[0023] Preferably, the encoding module encodes the sampled value for each cycle of the sampling circuit, finds the propagation order of the rising and falling edges of the pulse signal and sums them to obtain the voltage measurement result of the voltage sensing device.

[0024] During encoding, sub-chains are divided according to tap type and number, and then each sub-chain is encoded and summed.

[0025] Preferably, the register module includes a chain sampling register, a clock phase shift register, and a pulse width register;

[0026] The chain sampling register corresponds to the sampling value of the delay chain at a preset distance from the pulse generation circuit; when the pulse reaches the delay chain at the preset distance, it determines whether the phase of the current pulse is appropriate based on the sampling value, and determines whether both sides of the pulse can be sampled.

[0027] The clock phase shift register controls the clock phase shift port of the clock generation unit to adjust the pulse and the clock phase of the voltage sensing device;

[0028] The pulse width register corresponds to the selection signal of the pulse generation circuit of the TDC module; the pulse width register adjusts the number of stages of clock propagation on the delay chain unit of the pulse generation circuit, so that the XOR gate generates pulses and adjusts the pulse width.

[0029] According to the present invention, a calibration and tuning method for a tunable voltage sensing device based on TDC is provided, which applies a TDC-based tunable voltage sensing device and includes the following steps:

[0030] Step S1: Adjust the pulse width of the pulse generation circuit of the TDC module: Configure the pulse width register to make one delay chain unit in the pulse generation circuit have a short delay and another delay chain unit have a long delay.

[0031] Step S2: Calibration, enabling simultaneous sampling of both edges: Configure the clock phase shift register to gradually phase shift the clock of the pulse generation circuit; read the chain sampling register after each phase shift until both edges of the pulse are sampled, completing the calibration;

[0032] Step S3: Phase shift the output clock of the clock generation unit in front of the clock module, and collect the power consumption trajectory of the attacked module in the working and non-working states: gradually phase shift the output clock of the clock generation unit in front of the clock module, and collect several voltage values ​​of the attacked module in the working and non-working states at each phase.

[0033] Step S4: Tuning, determining the clock phase of the voltage sensing device: Calculate the standard deviation of the voltage values ​​collected in each phase within the period in step S3, and determine the phase with the largest difference in standard deviation as the phase used to complete the remote power consumption analysis attack.

[0034] Preferably, in step S2, if the pulse width is found to be insufficient during the phase shift process, the process from step S1 to step S2 is repeated to adjust the value of the pulse width register and generate a pulse of the preset width.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. The voltage sensing device provided by this invention has high sensitivity. Compared with common TDC voltage sensing devices, it adopts a multi-chain, multi-edge, and dual-sampling design, which greatly improves sensitivity;

[0037] 2. The voltage sensing device provided by this invention is easy to implement and has good deployability, which is enhanced by the use of a phase-shifted clock. The clock phase shift is used to complete the calibration of the sensing device before measurement, and an adjustable-length delay chain is used to implement a pulse generation circuit with adjustable width, avoiding repeated design modifications at the hardware level, while debugging is completed at the software level through register configuration.

[0038] 3. The voltage sensing device provided by this invention is tunable and has a high signal-to-noise ratio. The design of cascaded dual-clock generation units and clock phase shifting can adjust the phase relationship between the clocks of the sensing device and the attacked module, increasing the amount of effective information that can be collected. Attached Figure Description

[0039] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0040] Figure 1 This is a structural diagram of the voltage sensing device of the present invention;

[0041] Figure 2 This is a structural diagram of the clock module;

[0042] Figure 3 This is a structural diagram of the TDC module;

[0043] Figure 4 This is a diagram of the pulse generation circuit structure.

[0044] Figure 5 Schematic diagram of carry chain delay adjustment for pulse generation circuit;

[0045] Figure 6 This is a schematic diagram of the encoding module;

[0046] Figure 7 This is a schematic diagram of a test system architecture for attacking AES on an FPGA.

[0047] Figure 8 Flowchart for using this invention to complete a remote power consumption analysis attack;

[0048] Figure 9 A graph showing the standard deviation of voltage data collected with and without AES encryption at each clock phase;

[0049] Figure 10 A graph representing 10,000 AES-encrypted power consumption traces collected under two different clock phases;

[0050] Figure 11 This is a structural diagram of the voltage sensing device calibration and tuning of the present invention. Detailed Implementation

[0051] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0052] This invention discloses a high-sensitivity tunable TDC voltage sensing device for remote power analysis attacks, such as... Figure 1 As shown, the voltage sensing device of the present invention mainly comprises three parts: a clock module, a TDC module, and a register module. The present invention also provides a calibration and tuning method for the voltage sensing device, which can improve the deployability of the voltage sensing device and the signal-to-noise ratio of the acquired data.

[0053] The clock module includes two cascaded clock generation units. The output clock of the first-stage unit serves as the input clock of the second-stage unit, and can dynamically adjust the clock phase of the entire sensing device through phase shifting. The second-stage unit generates two clocks: the clock for the input TDC module pulse generation circuit and the main clock for the entire voltage sensing device. It can dynamically shift the phase of the input pulse generation circuit clock to adjust the pulse phase.

[0054] The TDC module includes a pulse generation circuit, a delay chain, a sampling circuit, and an encoding module.

[0055] The pulse generation circuit includes two sets of delay chain units and an XOR gate.

[0056] The delay chain unit of the pulse generation circuit adjusts the number of stages through which the clock propagates by a selection signal. When the clock reaches the XOR gate after passing through two different delays, pulse signals of different widths are generated at the clock edges.

[0057] The delay chain comprises multiple adjacent chains, and the pulses generated by the XOR gate are input into each chain for propagation.

[0058] The sampling circuit is a flip-flop array. Each stage of the delay chain has its delay unit taps connected to the flip-flops for sampling. When the delay chain is implemented using an FPGA's add-carry chain, both the add output and carry output of the carry chain are connected to flip-flops for sampling; the number of sampling taps is twice the number of stages in the carry chain, i.e., double sampling.

[0059] The encoding module encodes the sampled values ​​for each cycle of the sampling circuit, finds the propagation levels of the rising and falling edges of the pulse signal, and sums them to obtain the voltage measurement result of the sensing device. During encoding, sub-chains are divided according to tap type and number, encoded separately, and then summed to solve the problem of bubble interference encoding in the sampled values ​​caused by metastability.

[0060] The register module includes a chain sampling register, a clock phase shift register, and a pulse width register.

[0061] The chain sampling register corresponds to the sampled value of the delay chain closest to the pulse generation circuit. The pulse arrives at this chain the fastest, and the sampling value is used to determine whether the phase of the current pulse is appropriate, ensuring that both edges of the pulse are sampled.

[0062] The clock phase shift register controls the clock phase shift port of the clock generation unit, which is used to adjust the clock phase of the pulse and the entire sensing device.

[0063] The pulse width register corresponds to the selection signal of the pulse generation circuit in the TDC module. This register is used to adjust the number of stages of clock propagation on the two delay chains of the pulse generation circuit, causing the XOR gate to generate pulses and adjust the pulse width.

[0064] For example, to efficiently perform remote power consumption analysis attacks and collect as few power consumption trajectories as possible, this invention proposes a high-sensitivity tunable voltage sensing device based on TDC, implemented using an FPGA. The overall structure is as follows: Figure 1 As shown, the sensing device mainly includes a clock module, a TDC module, and a register module. The clock module uses a dual cascaded MMCM to generate the two clock signals required by the TDC module. The TDC module uses the propagation order of both edges of the carry chain measurement pulse signal as the measurement value. The register module is used to perform calibration and tuning operations related to the sensing device. This invention improves sensitivity through multi-chain, multi-edge, dual-sampling of the TDC module, and completes calibration and tuning through clock phase shifting, improving the deployability of the sensing device and the signal-to-noise ratio of the sampled power consumption trajectory, which is beneficial for remote power analysis attacks on FPGAs.

[0065] 1. Clock module:

[0066] The clock module uses two cascaded Mixed-Mode Clock Managers (MMCMs) on an FPGA, such as... Figure 2 As shown, the preamplifier stage is called the tuning MMCM, and the post-amplifier stage is called the working MMCM. The working MMCM outputs two clocks: one is a dynamically phase-shiftable pulse clock used to control the pulse generation circuit, adjusting the pulse phase through phase shifting; the other is a non-dynamically phase-shiftable sampling clock used for delay chain sampling and the operation of other modules. The dynamically phase-shiftable tuning clock output from the tuning MMCM serves as the input to the working MMCM, thus determining the overall clock phase of the sensing device. Dynamic phase shifting is achieved through the control of the phase shift control port via the register module. Relevant signals include the phase shift clock signal psclk, the phase shift enable signal psen, the phase shift increment / decrement control signal psincdec, and the phase shift completion signal psdone.

[0067] 2. TDC module:

[0068] The TDC module consists of a pulse generation circuit, a delay chain and sampling circuit, and an encoding module. The structure of the TDC module is as follows: Figure 3 As shown.

[0069] The pulse generation circuit includes two sets of carry chain units and an XOR gate composed of a lookup table, such as... Figure 4 As shown, it implements the function of a Digital-to-Time Converter (DTC). On the UltraScale+ series FPGA, the carry chain unit is CARRY8, which contains 8 cascaded carry selectors. The pulse clock is connected to the data input signals DI[7:0] of the carry chain. Therefore, by adjusting the carry selection signals S[7:0] of CARRY8, the number of stages of the input pulse clock propagation in each of the two carry chains can be adjusted. Then, after passing through an XOR gate, pulse signals of different widths are generated, such as... Figure 5 As shown, the two sets of CARRY8 units are constrained to adjacent positions when laid out on the FPGA, so that the delays of their outputs reaching the XOR gate are similar, which facilitates the generation of pulses with smaller widths. One set of carry chains contains multiple cascaded CARRY8 units; otherwise, in some cases, the delay adjustment space is too small to allow the two signals arriving at the XOR gate to be staggered for a sufficient time, thus failing to generate a pulse.

[0070] The delay chain and sampling circuit consist of multiple CARRY8 carry chains and flip-flop arrays. Each chain is placed adjacent to each other on the FPGA layout to reduce the skew of pulse arrival at each chain. Double sampling is performed on the delay chains, meaning the number of taps in the delay chain is twice the number of stages. All eight carry outputs CO[7:0] and eight adder outputs O[7:0] of each CARRY8 unit can be sampled, utilizing all 16 D flip-flops within its slice. The delay chain length should be long enough to ensure that the rising edge (0-1 transition) and falling edge (1-0 transition) of the pulse occur simultaneously on each chain, i.e., sampled as a set of data similar to "000011110000". Compared to ordinary single-chain TDCs, this invention uses a multi-chain, multi-edge, double-sampling method to improve the sensitivity of the TDC sensing device.

[0071] The encoding module implements edge lookup, encoding the sampled values ​​of the delay chain as the sum of the rising and falling edge positions. Then, the encoded values ​​of all delay chains are summed to obtain the final measured value. Considering that metastability and clock skew can cause bubbles in the sampled values ​​(i.e., 0s appearing in what should be consecutive 1s, such as "000101110000"), direct encoding makes it difficult to determine the edge positions. Therefore, the sampled values ​​of each chain are divided into two groups of 8 sub-chains each (bubble width not exceeding 8) according to the carry output CO[7:0] and the addition output O[7:0], as shown below. Figure 6 As shown, each subchain is encoded separately and then summed to eliminate the influence of bubbles in the sampled values. The encoding process is completed in multiple clock cycles using pipelined technology.

[0072] 3. Register module:

[0073] The register module uses the AXI-lite bus interface for the ARM processor on the FPGA PS side to configure and debug the TDC voltage sensing device. The designed registers include a read-only chain sampling register, a read-write clock phase shift register, and a read-write pulse width register.

[0074] The chain sampling register corresponds to the sampled value of the delay chain and is used to perform calibration, that is, to determine whether the phase of the current pulse clock can be sampled on both sides. Since the delay of the XOR gate of the pulse generation circuit to the delay chain of its same column slice is the smallest, and the delay of the carry output is smaller than the delay of the addition output, only the carry output of this chain can be sampled to reduce resource consumption. The clock phase shift register is used to control the clock phase shift ports of the two MMCMs, including: the enable signal psen and the phase shift increment / decrement control signal psincdec, which completes one phase shift to the left or right each time it is enabled; and the phase shift status signal psdone, which determines whether a phase shift is completed. The pulse width register corresponds to the configuration signal of the input pulse generation module, that is, the value of the carry selection signal S[7:0] of the two carry chain units.

[0075] Figure 7This is a test system for performing remote power analysis attacks using this invention on an FPGA. The main modules of the system are the TDC voltage sensing device of this invention and the open-source AES-128 encryption module to be attacked. Each time the AES module (Advanced Encryption Standard) is controlled from the PS to start encryption, the AES module sends a pulse trigger signal "start" to the sensing device, causing the sensing device to start recording voltage data and writing it into the FIFO (First Input First Output). In actual attacks, this trigger signal is not necessary, mainly for testing convenience and to avoid additional power consumption trajectory alignment operations. When the clock frequency of the AES module is 10MHz and the sampling clock frequency of the TDC sensing device is 200MHz, since AES-128 is a ten-round encryption, it requires 10 cycles to complete the encryption of one plaintext. Therefore, in one encryption, the sensing device needs to continuously collect voltage data for at least 200 cycles. After one data acquisition cycle, DMA (Direct Memory Access) reads the FIFO data and converts it into an AXI write operation, writing the data to DDR (Double Data Rate Synchronous Dynamic Random Access) memory controlled by the PS terminal of the FPGA. Once all data acquisitions are complete, the data is exported from DDR using the Xilinx XSCT tool.

[0076] This invention also discloses a calibration and tuning method for a tunable voltage sensing device based on TDC, such as... Figure 8 and 11 As shown, the calibration and tuning method of the voltage sensing device is accomplished through phase shifting of the clock signal, and the steps are as follows:

[0077] Step S1: Adjust the pulse width of the pulse generation circuit of the TDC module: Configure the pulse width register to make one delay chain in the pulse generation circuit have a short delay and another delay chain have a long delay.

[0078] Step S2: Calibration, ensuring simultaneous sampling of both edges: Configure the clock phase shift register to gradually phase shift the clock of the pulse generation circuit. After each phase shift, read the chain sampling register until both edges of the pulse are sampled, thus completing the calibration. If the pulse width is found to be too large or no pulse is generated during the phase shift process, repeat step S1-S2 to adjust the value of the pulse width register to generate a pulse of appropriate width.

[0079] Step S3: Phase shift the output clock of the front-end unit of the clock module and collect the power consumption trajectory of the attacked module in the working and non-working states: Phase shift the output clock of the front-end unit step by step using the same method as in S2, and collect several voltage values ​​of the attacked module in the working and non-working states at each phase.

[0080] Step S4: Tuning, determining the clock phase of the entire sensing device: Calculate the standard deviation of the two sets of voltage values ​​collected under each phase in one cycle in S3, and determine the phase with the largest difference between the two standard deviations as the phase used to complete the remote power consumption analysis attack, where the power consumption information leakage is the greatest.

[0081] Specific examples are as follows: Figure 8 This is a flowchart illustrating the process of using this invention to perform a remote power consumption analysis attack on AES in a test system. The first step is to configure the pulse width register to generate a pulse signal. The second step is to configure the clock phase shift register, gradually shifting the clock of the pulse generation circuit to complete the scan. After each phase shift, the chain sampling register is read to check whether a pulse is generated and whether the pulse width is small enough (both double edges can be sampled on the delay chain). If not, the value of the pulse width register is modified to adjust the length of the two carry chains of the pulse generation circuit. The third step is still to configure the clock phase shift register, gradually shifting and tuning the clock to adjust the clock phase relationship between the sensing device and AES, and collecting the power consumption of the AES module under each phase within one cycle, both encrypted and unencrypted. Each of the three steps involves 100 tracks, each containing 256 voltage data points. The fourth step involves exporting the data collected in the third step, calculating the standard deviation of the two sets of voltage data for each phase, and finding the phase position where the standard deviations differ the most. The fifth step involves first completing the tuning, that is, moving the tuning clock phase to the position calculated in the fourth step, and then starting the attack, that is, inputting a sufficient number of random plaintexts into the AES module, while using a sensor to collect the power consumption trajectory during encryption. The sixth step is the final step of the attack, using the collected power consumption trajectory data, selecting the last round of AES encryption as the attack point, and recovering the 16-byte key of the AES module through Correlation Power Analysis (CPA).

[0082] Figure 9 This refers to the standard deviation of 25,600 voltage data points collected in one cycle (AES encrypted and unencrypted) across 448 phases within a period when the tuning clock frequency of this invention is 200MHz. The standard deviation of the two sets of data differs most significantly at position 69, i.e., when the tuning clock phase shifts 69 times, indicating the greatest leakage of power consumption information. Subsequently, when attacking the AES module by collecting power consumption traces, the tuning clock phase is shifted to this position to complete the tuning of the sensing device.

[0083] Figure 10 These are 10,000 AES-encrypted power consumption traces collected by this invention at 69 and 400 phase shifts of the tuning clock, respectively. Where 69 corresponds to... Figure 9 The position with the largest difference in standard deviation, corresponding to 400. Figure 9The position with the smallest difference in standard deviation. The impact of the phase relationship between the sensor and the AES module on the signal-to-noise ratio of the acquired power consumption trajectory can be seen from the power consumption trajectory. In the power consumption trajectory acquired at the tuned phase on the left, the voltage troughs corresponding to each clock edge can be clearly distinguished. The tuning completed by phase-shifting the clock significantly improves the signal-to-noise ratio of the acquired data. The instantaneous voltage drop is caused by the register inversion of the AES module at each rising edge of the clock. When the voltage decreases, the delay chain, including the delay of the pulse generation circuit, becomes smaller, and the number of stages of pulse propagation on the delay chain decreases, thereby reducing the measured value of the TDC sensor.

[0084] This invention provides an on-chip voltage sensing device based on a delay chain (TDC). It achieves high sensitivity and good deployability through multi-chain, multi-edge, dual-sampling measurement and dynamic phase shift of the clock signal, and also provides calibration and tuning functions.

[0085] This invention relates to the design and calibration / tuning method of a voltage sensing device based on a time-to-digital converter (TDC). The high-sensitivity tunable voltage sensing device based on TDC of this invention can be used to acquire power consumption trajectories and perform remote power consumption analysis attacks. The sensing device comprises three parts: a TDC module, a clock module, and a register module. The core TDC module includes a pulse generation circuit, a delay chain, a sampling circuit, and an encoding module. The pulse generation circuit generates pulse signals that propagate along the delay chain. The sampling circuit is a flip-flop array that samples the output of the delay chain each cycle. The encoding module encodes the sampled values ​​to obtain the measurement results. The clock module contains two cascaded clock generation units to provide the pulse clock and sampling clock required by the TDC module, and completes the calibration and tuning of the sensing device through clock phase shifting. The register module is used to configure and debug various parameters of the sensing device. The TDC voltage sensing device design and corresponding calibration / tuning method provided by this invention can reduce the implementation difficulty of the voltage sensing device and improve the sensitivity of the sensing device and the signal-to-noise ratio of the acquired power consumption trajectory.

[0086] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0087] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A tunable voltage sensing device based on TDC, characterized in that, Includes a TDC module, a clock module, and a register module; The clock module generates a pulse clock and a sampling clock; The TDC module generates multi-edge pulse signals based on the pulse clock, which are transmitted on the delay chain and sampled by the sampling clock to obtain the measurement results. The register module configures and debugs the TDC module and the clock module; The TDC module includes a pulse generation circuit, a delay chain, a sampling circuit, and an encoding module; The pulse generation circuit receives a pulse clock and generates a pulse signal that propagates on the delay chain. The sampling circuit receives a sampling clock and samples the output on the delay chain in each cycle according to the sampling clock to obtain a sampled value; The encoder module encodes the sampled values ​​to obtain the measurement results; The clock module includes cascaded clock generation units; The output clock of the preceding clock generation unit serves as the input clock of the subsequent clock generation unit, and the clock phase of the voltage sensing device is dynamically adjusted by phase shift. The subsequent clock generation unit generates a pulse clock and a sampling clock, dynamically shifting the phase of the pulse clock from the input pulse generation circuit to adjust the pulse phase.

2. The tunable voltage sensing device based on TDC according to claim 1, characterized in that, The pulse generation circuit includes a delay chain unit and an XOR gate; The delay chain unit of the pulse generation circuit adjusts the number of stages of clock propagation in the delay chain unit by selecting a signal; when the clock reaches the XOR gate after different delays, pulse signals of different widths are generated at the clock edge.

3. The tunable voltage sensing device based on TDC according to claim 2, characterized in that, The delay chain consists of multiple chains, and the pulse generated by the XOR gate is input into each delay chain for propagation.

4. The tunable voltage sensing device based on TDC according to claim 1, characterized in that, The sampling circuit is a flip-flop array; The delay unit taps at each stage of the delay chain are connected to triggers and sampled; When the delay chain is implemented by the FPGA's add-carry chain, both the add output and carry output of the carry chain are connected to flip-flops and sampled.

5. The tunable voltage sensing device based on TDC according to claim 1, characterized in that, The encoding module encodes the sampled value for each cycle of the sampling circuit, finds the propagation order of the rising and falling edges of the pulse signal and sums them to obtain the voltage measurement result of the voltage sensing device. During encoding, sub-chains are divided according to tap type and number, and then each sub-chain is encoded and summed.

6. The tunable voltage sensing device based on TDC according to claim 2, characterized in that, The register module includes a chain sampling register, a clock phase shift register, and a pulse width register; The chain sampling register corresponds to the sampling value of the delay chain at a preset distance from the pulse generation circuit; when the pulse reaches the delay chain at the preset distance, it determines whether the phase of the current pulse is appropriate based on the sampling value, and determines whether both sides of the pulse can be sampled. The clock phase shift register controls the clock phase shift port of the clock generation unit to adjust the pulse and the clock phase of the voltage sensing device; The pulse width register corresponds to the selection signal of the pulse generation circuit of the TDC module; the pulse width register adjusts the number of stages of clock propagation on the delay chain unit of the pulse generation circuit, so that the XOR gate generates pulses and adjusts the pulse width.

7. A calibration and tuning method for a tunable voltage sensing device based on TDC, characterized in that, The application of the tunable voltage sensing device based on TDC according to any one of claims 1-6 includes the following steps: Step S1: Adjust the pulse width of the pulse generation circuit of the TDC module: Configure the pulse width register to make one delay chain unit in the pulse generation circuit have a short delay and another delay chain unit have a long delay. Step S2: Calibration, enabling simultaneous sampling of both edges: Configure the clock phase shift register to gradually phase shift the clock of the pulse generation circuit; read the chain sampling register after each phase shift until both edges of the pulse are sampled, completing the calibration; Step S3: Phase shift the output clock of the clock generation unit in front of the clock module, and collect the power consumption trajectory of the attacked module in the working and non-working states: gradually phase shift the output clock of the clock generation unit in front of the clock module, and collect several voltage values ​​of the attacked module in the working and non-working states at each phase. Step S4: Tuning, determining the clock phase of the voltage sensing device: Calculate the standard deviation of the voltage values ​​collected in each phase within the period in step S3, and determine the phase with the largest difference in standard deviation as the phase used to complete the remote power consumption analysis attack.

8. The calibration and tuning method for a tunable voltage sensing device based on TDC according to claim 7, characterized in that, In step S2, if the pulse width is found to be insufficient during the phase shift process, the process from step S1 to step S2 is repeated to adjust the value of the pulse width register and generate a pulse of the preset width.

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