Low power system based on clockless wake-up

Abstract

The application discloses a low-power-consumption system with clockless wake-up, which comprises an external signal detection module, a gated clock, and a low-power-consumption timer. The external signal detection module is located in a normal power area of the low-power-consumption system and is used for detecting whether an external signal exists. If the external signal exists, an enable signal for starting a low-power-consumption timer working clock is output. The gated clock is used for receiving the enable signal for starting the low-power-consumption timer working clock and starting the low-power-consumption timer working clock. The low-power-consumption timer is used for starting the low-power-consumption timer working clock, and a counter starts counting. After the counter overflows, a wake-up signal and an interrupt signal are generated. The wake-up signal is used for waking up a power management unit, the power management unit controls a clock reset module to generate a system clock signal, the interrupt signal and the system clock signal are used for waking up a CPU, and the low-power-consumption system can start working again. The low-power-consumption system can wake up the system in time and reduce system power consumption.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and in particular relates to a low-power system based on clock-free wake-up. Background Technology

[0002] Power consumption is a crucial parameter for microcontroller chips (MCUs). Different chips performing the same function can have varying power densities, leading to higher chip temperatures, reduced circuit reliability, and shorter device lifespans. Higher power consumption also means more battery consumption and higher operating costs. Current chips face increasingly stringent power consumption requirements due to market demands. The primary method for reducing power consumption is to power off the chip or disable its clock when the CPU is idle, putting the CPU in a power-off or sleep mode while still maintaining real-time responsiveness.

[0003] In existing technologies, the external signal detection module is located inside the low-power timer. The low-power timer's operating clock needs to be continuously on, which increases system power consumption. When an external signal is detected, the counter starts counting, which in turn generates a wake-up signal. The low-power timer needs the wake-up signal to wake up the PMU (power management unit) to enable the clock reset module (RCC), and at the same time wake up the CPU. The CPU configures the low-power timer to restart. Ordinary designs may cause the timer to malfunction when it is restarted. Summary of the Invention

[0004] Purpose of the invention: The technical problem to be solved by the present invention is to provide a low-power system based on clock-free wake-up, which addresses the shortcomings of the prior art.

[0005] To solve the above-mentioned technical problems, the present invention discloses a low-power system based on clock-free wake-up, including an external signal detection module, a gated clock, a low-power timer, a power management unit, a clock reset module and a CPU. When in low-power mode, all clocks, including the system clock and the low-power timer working clock, are turned off.

[0006] The external signal detection module is located in the constant power area of ​​the low-power system and is used to detect whether there is an external signal. If there is an external signal, it outputs an enable signal to turn on the working clock of the low-power timer.

[0007] The gated clock is used to receive an enable signal to turn on the low-power timer clock and turn on the low-power timer clock.

[0008] The low-power timer is used to start counting after the low-power timer clock is turned on. When the counter overflows, it generates a wake-up signal and an interrupt signal. The wake-up signal is used to wake up the power management unit, which controls the clock reset module to generate a system clock signal. The interrupt signal and the system clock signal are used to wake up the CPU, so that the low-power system can start working again.

[0009] The process of enabling the low-power system to restart includes the low-power timer feeding back the status of the counter enable signal and clear signal to the low-power system, and the low-power system reconfiguring the low-power timer to enable it to restart.

[0010] This invention implements clockless chip wake-up based on a low-power timer. The external signal detection module is placed in the constant power area of ​​the chip, which greatly reduces the power consumption of the low-power timer. When an external signal is detected, the working clock of the low-power timer is turned on. When the low-power timer overflows, it generates a wake-up signal, which can wake up the PMU and thus turn on the system clock. At the same time, the low-power timer generates an interrupt signal to wake up the CPU, and the system can start working again.

[0011] Furthermore, the low-power timer includes a counter enable unit and a counter clear unit.

[0012] The counter enable unit is used to generate a counter enable signal after the counter overflows. The counter enable signal is used to turn off the counter enable. When the system clock is turned on, the counter enable signal is fed back to the low-power system.

[0013] The counter clearing unit is used to clear the counter. After the counter is cleared, it releases the clearing signal in the system clock domain. When the system clock is turned on, it feeds back the status of the clearing signal to the low-power system, which then turns off the clearing signal.

[0014] Furthermore, both the counter enable unit and the counter clear unit include a system clock domain and a working clock domain. Feeding back the counter enable signal to the low-power system and feeding back the status of the clear signal to the low-power system both require cross-clock domain processing.

[0015] Furthermore, the counter enable signal is fed back to the low-power system for cross-clock domain processing via a feedback circuit; the status of the clear signal is fed back to the low-power system for cross-clock domain processing via a handshake circuit.

[0016] Furthermore, the system clock domain of the counter enable unit includes a first flip-flop D1, a first selector MUX1, a first inverter, a first XOR circuit NOR1, a second synchronization circuit Sync2, and a first control circuit Ctrl1, wherein the first flip-flop D1 and the second synchronization circuit Sync2 use the system clock as the control signal; the operating clock domain of the counter enable unit includes a second flip-flop D2, a second selector MUX2, a second XOR circuit NOR2, a first synchronization circuit Sync1, and a second control circuit Ctrl2, wherein the second flip-flop D2 and the first synchronization circuit Sync1 use the low-power timer operating clock as the control signal;

[0017] The value of the second flip-flop D2 reaches the system clock domain after passing through the second synchronization circuit Sync2. The first control circuit Ctrl1 controls the first selector MUX1 to select an appropriate value. The value of the first selector MUX1 is input to the first flip-flop D1. The value of the first flip-flop D1 reaches the working clock domain after passing through the first synchronization circuit Sync1. The second control circuit Ctrl2 controls the second selector MUX2 to select an appropriate value. The value of the second selector MUX2 is input to the second flip-flop D2. The value of the first flip-flop D1, after passing through the first synchronization circuit Sync1, and the value of the second flip-flop D2 are input to the second XOR circuit NOR2 to obtain the counter enable signal EN. The value of the second flip-flop D2, after passing through the second synchronization signal Sync2, and the value of the first flip-flop D1 are input to the first XOR circuit NOR1 to obtain the enable signal feedback value rdata.

[0018] For the enable signal of the low-power timer, this invention uses a feedback circuit instead of a handshake, avoiding a complex handshake mechanism and reducing circuit power consumption. When the timer operates in low-power mode, there is no system clock. This circuit can latch the timer's state and feed it back to the CPU when the system clock arrives, allowing normal operation to resume. The innovative introduction of a feedback circuit into the low-power timer simplifies the circuit structure and improves circuit reliability and practicality.

[0019] Furthermore, the first control circuit Ctrl1 controls the first selector MUX1 to select an appropriate value by: the first control circuit Ctrl1 is controlled by the counter enable register in the system clock domain; when the counter enable register is high, the counter enable is high, and the first selector MUX1 selects the inverted value; when the counter enable register is low, the counter enable is low, and the first selector MUX1 selects the non-inverted value.

[0020] The second control circuit Ctrl2 controls the second selector MUX2 to select an appropriate value, including: when the counter overflows without detecting an external signal, the second control circuit Ctrl2 controls the second selector MUX2 to select the value of the first synchronization circuit Sync1; otherwise, it selects the value of the second flip-flop D2.

[0021] Furthermore, feeding back the counter enable signal to the low-power system includes: when the system clock is not turned on, the second flip-flop D2 holds the value previously passed from the first flip-flop D1. When the wake-up signal wakes up the PMU, and the PMU controls the clock reset module to generate the system clock signal, the value of the second flip-flop D2 is input to the first XOR circuit NOR1 after passing through the second synchronization signal Sync2. The other input of the first XOR circuit NOR1 is the value of the first flip-flop D1. The two inputs are the same, and the XOR value is the same. If the enable signal feedback value rdata is low, the low-power system reads that the counter has been turned off, thus completing the process of the low-power timer feeding back the enable signal to the low-power system.

[0022] Furthermore, the system clock domain of the counter clearing unit includes the third flip-flop D3, the third selector MUX3, the third control circuit Ctrl3, and the fourth synchronization circuit Sync4, wherein the third flip-flop D3 and the fourth synchronization circuit Sync4 use the system clock as the control signal; the operating clock domain of the counter clearing unit includes the fourth flip-flop D4, the fourth selector MUX4, the fourth control circuit Ctrl4, the third synchronization circuit Sync3, the fifth synchronization circuit Sync5, and the edge detection module edge_det2, wherein the fourth flip-flop D4, the third synchronization circuit Sync3, and the fifth synchronization circuit Sync5 use the low-power timer operating clock as the control signal;

[0023] In the system clock domain, writing 1 to the counter clear register generates a pulse signal to clear the counter. The third control circuit Ctrl3 converts this pulse signal into a level signal. After the third control circuit Ctrl3 controls the third selector MUX3 to make a selection, the signal passes through the third flip-flop D3 to the third synchronization circuit Sync3 and is then input to the fourth selector MUX4. The fourth control circuit Ctrl4 controls the fourth selector MUX4 to select an appropriate value. The value of the fourth selector MUX4 is input to the fourth selector MUX4. The value of the fourth selector MUX4 is input to the edge detection module edge_det2, which outputs a clear signal clr. The value of the fourth flip-flop D4 passes through the fourth synchronization circuit Sync4 to reach the system clock domain and is input to the third selector Ctrl3. The value of the third selector Ctrl3 is synchronized to the fourth control circuit Ctrl4 through the fifth synchronization circuit Sync5.

[0024] Furthermore, the third control circuit Ctrl3 controls the third selector MUX3 to select the following: when the CPU controls the counter clear register to clear the counter, the third control circuit Ctrl3 controls the third selector MUX3 to select a high-level signal; otherwise, when the fourth synchronization circuit Snyc4 is high, the third control circuit Ctrl3 controls the third selector MUX3 to select a low-level signal; otherwise, when the fourth synchronization circuit Snyc4 is low, the third selector MUX3 selects the value of the third flip-flop D3.

[0025] The fourth control circuit Ctrl4 controls the fourth selector MUX4 to select an appropriate value, including: when the fifth synchronization circuit Sync5 is high, the fourth control circuit Ctrl4 controls the fourth selector MUX4 to select a low level; otherwise, it selects the value of the third synchronization circuit Sync3.

[0026] Furthermore, feeding back the status of the clear signal to the low-power system includes: the value of the fourth flip-flop D4 reaches the system clock domain through the fourth synchronization circuit Sync4, and after passing through the third control circuit Crtl3, when the fourth synchronization circuit Sync4 is high, the third selector MUX3 selects a low-level signal. The value of the third control circuit Crtl3 reaches the fourth control circuit Ctrl4 after passing through the fifth synchronization circuit Sync5. When the fifth synchronization circuit Sync5 is high, the fourth selector MUX4 outputs a low-level signal, and the clear signal is released. In this way, when the next clear signal arrives, the edge detection module edge_det2 can still detect the rising edge.

[0027] When the system clock domain generates a clear signal, the system clock is turned off, and the fourth flip-flop D4 remains at a high level. When the system is woken up and the system clock is generated, the output signal of the fourth flip-flop D4 is synchronized to the system clock domain, which changes the value of the third flip-flop D3 to a low level and turns off the clear signal.

[0028] This invention employs a handshake mechanism to clear the signal. The clear signal in the system clock domain is a pulse signal. It is first converted to a level signal in the system clock domain, synchronized to the working clock domain, and then edge detection is performed to generate a pulse signal in the working clock domain. This is the clear signal in the working clock domain, and this clear signal is also fed back to the system clock domain to release the clear signal status.

[0029] Beneficial effects:

[0030] This invention reduces the overall power consumption of the system. An external signal detection module is set in the normally open area. When the rising edge of an external signal is detected, the timer's operating clock is activated, thus reducing the dynamic power consumption of the timer during the period before the external signal arrives. A feedback circuit is used to control the counter enable signal, simplifying the circuit and reducing power consumption. This invention can wake up the system promptly. After detecting an external signal, the low-power timer's counter starts counting. When the count overflows, a wake-up signal and an interrupt signal are generated. The wake-up signal is sent to the PMU, and the interrupt signal is sent to the CPU. After the system clock is turned on, the low-power timer can resume normal operation, solving the problem in existing technologies where the timer cannot function properly upon restarting. Attached Figure Description

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, and the advantages of the present invention in the above and / or other aspects will become clearer.

[0032] Figure 1 This is a schematic diagram of a low-power system based on clock-free wake-up provided in an embodiment of this application.

[0033] Figure 2 This is a schematic diagram of the structure of a counter enable unit for a low-power system based on a clock-free wake-up, as provided in an embodiment of this application.

[0034] Figure 3 This is a schematic diagram of the structure of a counter clearing unit for a low-power system based on a clock-free wake-up, as provided in an embodiment of this application. Detailed Implementation

[0035] The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0036] With the application of technologies such as wireless communication and the Internet of Things in smart grids, a large number of handheld and wireless devices are powered by batteries, highlighting the need for low-power chips. There are over 500 million electricity meters in use nationwide, each with at least one built-in main control chip. Assuming a static power consumption of 100µA, the annual static power consumption of main control chips in national electricity meters reaches 780,000 kWh; assuming an average dynamic power consumption of 3mA, the annual dynamic power consumption reaches 24 million kWh. Each type of grid device uses several to dozens of chips, resulting in a very large total power consumption. Therefore, reducing power consumption has always been a key focus in smart grid chip development. Low-power chips (low-power systems) mostly require low-power timers, thus this application has broad application scenarios.

[0037] To reduce system power consumption, in low-power mode, the system clock and the low-power timer's operating clock can be turned off, and the system can be woken up to resume operation; therefore, a wake-up mechanism is still required. This application provides a low-power system based on clockless wake-up, implementing a clockless chip wake-up mechanism based on a low-power timer, such as... Figure 1 As shown, the low-power system includes an external signal detection module edge_det1, a gated clock GCLK, a low-power timer lptimer, a power management unit PMU, a clock reset module RCC, and a CPU. When in low-power mode, all clocks, including the system clock pclk and the low-power timer operating clock 32k, are turned off.

[0038] The external signal detection module edge_det1 is located in the constant power area of ​​the low-power system and is used to detect whether there is an external signal. If there is an external signal, it outputs an enable signal en to turn on the low-power timer clock.

[0039] The gated clock GCLK is used to receive the enable signal to turn on the low-power timer clock, which turns on the low-power timer clock 32kHz. In this embodiment, the frequency of the low-power timer clock is 32kHz.

[0040] The low-power timer is used to start counting after the low-power timer clock is turned on at 32k. When the counter overflows, it generates a wake-up signal and an interrupt signal. The wake-up signal is used to wake up the power management unit. The power management unit controls the clock reset module to generate the system clock signal pclk. The interrupt signal and the system clock signal pclk are used to wake up the CPU, so that the low-power system can start working again.

[0041] The process of enabling the low-power system to restart includes the low-power timer feeding back the status of the counter enable signal EN and the clear signal clr to the low-power system, and the low-power system reconfiguring the low-power timer to enable it to resume operation.

[0042] After configuring the low-power timer registers, the system clock pclk and the low-power timer's operating clock 32k can be turned off. The constant-power zone clock pclk1 is always on. When the external signal detection module edge_det1 detects the external signal ext_i, the low-power timer's operating clock 32k is turned on. The counter can start counting when triggered by an external signal. Each time an external signal is detected, the counter is cleared and restarted. The counter can be flexibly configured with a target value. When the counter reaches the target value, it stops counting and generates wake-up and interrupt signals, waking up the PMU. The RCC module generates a clock signal, and after the CPU responds to the interrupt signal, the system can resume operation. The low-power timer can be configured to restart.

[0043] In this embodiment, the low-power timer includes a counter enable unit and a counter clear unit.

[0044] The counter enable unit is used to generate a counter enable signal after the counter overflows. The counter enable signal is used to turn off the counter. When the system clock pclk is turned on, the counter enable signal is fed back to the low-power system.

[0045] The counter clearing unit is used to clear the counter. After the counter is cleared, it releases the clearing signal in the system clock domain. When the system clock pclk is turned on, it feeds back the status of the clearing signal to the low-power system, which then turns off the clearing signal.

[0046] Both the counter enable unit and the counter clear unit include a system clock domain and a working clock domain. Feeding back the counter enable signal to the low-power system and the status of the clear signal to the low-power system both require cross-clock domain processing.

[0047] The core unit of a low-power timer is a counter, which has two important control signals: the counter enable signal (EN) and the counter clear signal (CLR). In the system clock domain, writing a 1 to the counter enable register turns the counter on, and writing a 0 turns it off. In the operating clock domain, the counter enable can be turned off after overflow. In the system clock domain, writing a 1 to the counter clear register controls the clear signal to reset the counter to zero. In the operating clock domain, after the counter is reset to zero, the system clock clear signal needs to be released. When there is no system clock (pclk), the low-power timer needs to retain the states of the enable and clear signals required for operation. Once the system clock (pclk) is generated, the low-power timer feeds back the states of the enable and clear signals to the system, allowing the low-power timer to resume operation. Signal transmission across different clock domains requires cross-clock processing, typically handled by handshaking and FIFO. This embodiment requires special handling of the counter's enable and clear signals.

[0048] In this embodiment, the counter enable signal is fed back to the low-power system for cross-clock domain processing via a feedback circuit; the status of the clear signal is fed back to the low-power system for cross-clock domain processing via a handshake circuit.

[0049] For the enable signal, a feedback circuit is used to solve the clock-crossing problem. The circuit structure diagram is as follows: Figure 2 As shown, this circuit contains two clock domains: a system clock (pclk) and a working clock (32kHz). The system clock domain includes a first flip-flop D1, a first selector (MUX1), a first inverter, a first XOR circuit (NOR1), a second synchronization circuit (Sync2), and a first control circuit (Ctrl1). The first flip-flop D1 and the second synchronization circuit (Sync2) use the system clock (pclk) as their control signal. The working clock domain similarly includes a second flip-flop D2, a second selector (MUX2), a second XOR circuit (NOR2), a first synchronization circuit (Sync1), and a second control circuit (Ctrl2). The second flip-flop D2 and the first synchronization circuit (Sync1) use a low-power timer working clock (32kHz) as their control signal. Both the first synchronization circuit (Sync1) and the second synchronization circuit (Sync2) are composed of two cascaded flip-flops.

[0050] The value of the second flip-flop D2 in the operating clock domain reaches the system clock domain after passing through the second synchronization circuit Sync2. The first control circuit Ctrl1 controls the first selector MUX1 to select an appropriate value. The first control circuit Ctrl1 is controlled by the counter enable register in the system clock domain. When the counter enable register is high, the counter enable is high, and the first selector MUX1 selects the inverted value. When the counter enable register is low, the counter enable is low, and the first selector MUX1 selects the non-inverted value. The value of the first selector MUX1 is input to the first flip-flop D1. The value of the first flip-flop D1 reaches the 32kHz operating clock domain after passing through the first synchronization circuit Sync1. The second control circuit Ctrl2 controls the second selector MUX2 to select an appropriate value. When no external signal is detected, the counter overflows. The second control circuit Ctrl2 controls the second selector MUX2 to select the value of the first synchronization circuit Sync1; otherwise, it selects the value of the second flip-flop D2. The value of the second selector MUX2 is input to the second flip-flop D2. The value of the first flip-flop D1, after passing through the first synchronization circuit Sync1 and the value of the second flip-flop D2, is input to the second XOR circuit NOR2 to obtain the counter enable signal EN; the value of the second flip-flop D2, after passing through the second synchronization signal Sync2 and the value of the first flip-flop D1, is input to the first XOR circuit NOR1 to obtain the enable signal feedback value rdata.

[0051] When the counter enable register is written with a 1 to enable the counter, the first control circuit Ctrl1 controls the first selector MUX1 to select the inverted value. The value of the second flip-flop D2 is inverted by the second synchronization circuit Sync2 and then reaches the first flip-flop D1. After passing through the first synchronization circuit Sync1, the value of the second flip-flop D2 is XORed, resulting in an XOR value EN that is high, thus enabling the counter. When the counter enable register is written with a 0 to disable the counter, the value of the second flip-flop D2 is passed through the second synchronization circuit Sync2 and reaches the first flip-flop D1. After passing through the first synchronization circuit Sync1, the value of the second flip-flop D2 is XORed, resulting in an XOR value EN that is low, thus disabling the counter. When the counter overflows, the second control circuit Ctrl2 controls the second selector MUX2 to select the value of the first synchronization circuit Sync1 to reach the second flip-flop D2. The values ​​at both ends of the second XOR circuit NOR2 are equal, resulting in an XOR value EN that is low, thus disabling the counter.

[0052] When the system clock pclk is absent, the second flip-flop D2 can maintain the value previously passed from the first flip-flop D1. When the wake-up signal wakes up the PMU, and the PMU controls the clock reset module to generate the system clock signal pclk, the value of the second flip-flop D2 is input to the first XOR circuit NOR1 after passing through the second synchronization signal Sync2. The other input of the first XOR circuit NOR1 is the value of the first flip-flop D1. When the two inputs are the same, the XOR value rdata is low, and the low-power system can read that the counter has been turned off, thus completing the process of the low-power timer feeding back the enable signal to the low-power system. This feedback signal method avoids the complex synchronization circuits required by the handshake mechanism.

[0053] For the clear signal clr, this embodiment uses a handshake circuit, and the circuit structure diagram is as follows. Figure 3 As shown. The counter clearing unit contains two clock domains: a system clock domain and a counter operating clock domain. The system clock domain of the counter clearing unit includes the third flip-flop D3, the third selector MUX3, the third control circuit Ctrl3, and the fourth synchronization circuit Sync4, where the third flip-flop D3 and the fourth synchronization circuit Sync4 use the system clock pclk as the control signal; the operating clock domain of the counter clearing unit includes the fourth flip-flop D4, the fourth selector MUX4, the fourth control circuit Ctrl4, the third synchronization circuit Sync3, the fifth synchronization circuit Sync5, and the edge detection module, where the fourth flip-flop D4, the third synchronization circuit Sync3, and the fifth synchronization circuit Sync5 use the low-power timer operating clock 32k as the control signal.

[0054] In the system clock domain, writing 1 to the counter clear register generates a pulse signal to clear the counter. The third control circuit Ctrl3 converts this pulse signal into a level signal. After the third control circuit Ctrl3 controls the third selector MUX3 to make a selection, the signal passes through the third flip-flop D3 to the third synchronization circuit Sync3 and is then input to the fourth selector MUX4. The fourth control circuit Ctrl4 controls the fourth selector MUX4 to select an appropriate value. The value of the fourth selector MUX4 is input to the fourth selector MUX4. The value of the fourth selector MUX4 is input to the edge detection module edge_det2, which outputs a clear signal clr. The value of the fourth flip-flop D4 passes through the fourth synchronization circuit Sync4 to reach the system clock domain and is input to the third selector Ctrl3. The value of the third selector Ctrl3 is synchronized to the fourth control circuit Ctrl4 through the fifth synchronization circuit Sync5.

[0055] The third control circuit Ctrl3 controls the third selector MUX3 to select the following: when the CPU controls the counter clear register to clear the counter, the third control circuit Ctrl3 controls the third selector MUX3 to select a high-level signal; otherwise, when the fourth synchronization circuit Snyc4 is high, the third control circuit Ctrl3 controls the third selector MUX3 to select a low-level signal; otherwise, when the fourth synchronization circuit Snyc4 is low, the third selector MUX3 selects the value of the third flip-flop D3.

[0056] The fourth control circuit Ctrl4 controls the fourth selector MUX4 to select an appropriate value, including: when the fifth synchronization circuit Sync5 is high, the fourth control circuit Ctrl4 controls the fourth selector MUX4 to select a low level; otherwise, it selects the value of the third synchronization circuit Sync3.

[0057] The value of the fourth flip-flop D4 reaches the system clock domain through the fourth synchronization circuit Sync4. After passing through the third control circuit Crtl3, when the fourth synchronization circuit Sync4 is high, the third selector MUX3 selects a low-level signal. The value of the third control circuit Crtl3 reaches the fourth control circuit Ctrl4 after passing through the fifth synchronization circuit Sync5. When the fifth synchronization circuit Sync5 is high, the fourth selector MUX4 outputs a low-level signal, and the clear signal is released. In this way, when the next clear signal arrives, the edge detection module edge_det2 can still detect the rising edge.

[0058] When the system clock domain generates a clear signal, the system clock pclk is turned off, and the fourth flip-flop D4 in the 32k clock domain can maintain a high level. When the system is woken up and the system clock pclk arrives, the output signal of the fourth flip-flop D4 can be synchronized to the system clock domain, turning the value of the third flip-flop D3 low and turning off the clear signal.

[0059] This invention provides a low-power system based on clock-free wake-up. Many methods and approaches exist for implementing this technical solution; the above descriptions are merely specific embodiments of this invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this invention, and these improvements and modifications should also be considered within the scope of protection of this invention. All components not explicitly stated in this embodiment can be implemented using existing technologies.

Claims

1. A low-power system based on clock-free wake-up, characterized in that, It includes an external signal detection module, a gated clock, a low-power timer, a power management unit, a clock reset module, and a CPU. When in low-power mode, all clocks, including the system clock and the low-power timer's operating clock, are turned off. The external signal detection module is located in the constant power area of ​​the low-power system and is used to detect whether there is an external signal. If there is an external signal, it outputs an enable signal to turn on the working clock of the low-power timer. The gated clock is used to receive an enable signal to turn on the low-power timer clock and turn on the low-power timer clock. The low-power timer is used to start counting after the low-power timer clock is turned on. When the counter overflows, it generates a wake-up signal and an interrupt signal. The wake-up signal is used to wake up the power management unit, which controls the clock reset module to generate a system clock signal. The interrupt signal and the system clock signal are used to wake up the CPU, so that the low-power system can start working again. The process of enabling the low-power system to restart includes the low-power timer feeding back the status of the counter enable signal and clear signal to the low-power system, and the low-power system reconfiguring the low-power timer to enable it to restart. The low-power timer includes a counter enable unit, which generates a counter enable signal after the counter overflows. The counter enable signal is used to turn off the counter enable. When the system clock is turned on, the counter enable signal is fed back to the low-power system. The counter enable unit includes a system clock domain and a working clock domain, and feeds back the counter enable signal to the low-power system for cross-clock domain processing through a feedback circuit. The system clock domain of the counter enable unit includes a first flip-flop D1, a first selector MUX1, a first inverter, a first XOR circuit NOR1, a second synchronization circuit Sync2, and a first control circuit Ctrl1, wherein the first flip-flop D1 and the second synchronization circuit Sync2 use the system clock as the control signal; the operating clock domain of the counter enable unit includes a second flip-flop D2, a second selector MUX2, a second XOR circuit NOR2, a first synchronization circuit Sync1, and a second control circuit Ctrl2, wherein the second flip-flop D2 and the first synchronization circuit Sync1 use the low-power timer operating clock as the control signal.

2. The low-power system based on clock-free wake-up according to claim 1, characterized in that, The low-power timer also includes a counter clearing unit, which is used to clear the counter. After the counter is cleared, the clearing signal in the system clock domain is released. When the system clock is turned on, the status of the clearing signal is fed back to the low-power system, and the low-power system turns off the clearing signal.

3. A low-power system based on clock-free wake-up according to claim 2, characterized in that, The counter clearing unit includes a system clock domain and a working clock domain. Feeding back the status of the clearing signal to the low-power system requires cross-clock domain processing.

4. A low-power system based on clock-free wake-up according to claim 3, characterized in that, The status of the clear signal is fed back to the low-power system for cross-clock domain processing via a handshake circuit.

5. A low-power system based on clock-free wake-up according to claim 4, characterized in that, The value of the second flip-flop D2 reaches the system clock domain after passing through the second synchronization circuit Sync2. The first control circuit Ctrl1 controls the first selector MUX1 to select an appropriate value. The value of the first selector MUX1 is input to the first flip-flop D1. The value of the first flip-flop D1 reaches the working clock domain after passing through the first synchronization circuit Sync1. The second control circuit Ctrl2 controls the second selector MUX2 to select an appropriate value. The value of the second selector MUX2 is input to the second flip-flop D2. The value of the first flip-flop D1, after passing through the first synchronization circuit Sync1, and the value of the second flip-flop D2 are input to the second XOR circuit NOR2 to obtain the counter enable signal EN. The value of the second flip-flop D2, after passing through the second synchronization signal Sync2, and the value of the first flip-flop D1 are input to the first XOR circuit NOR1 to obtain the enable signal feedback value rdata. The first control circuit Ctrl1 controls the first selector MUX1 to select an appropriate value, including: the first control circuit Ctrl1 is controlled by the counter enable register in the system clock domain. When the counter enable register is high, the counter enable is high, and the first selector MUX1 selects the inverted value; when the counter enable register is low, the counter enable is low, and the first selector MUX1 selects the non-inverted value. The second control circuit Ctrl2 controls the second selector MUX2 to select an appropriate value, including: when the counter overflows without detecting an external signal, the second control circuit Ctrl2 controls the second selector MUX2 to select the value of the first synchronization circuit Sync1; otherwise, it selects the value of the second flip-flop D2.

6. A low-power system based on clock-free wake-up according to claim 5, characterized in that, Feeding the counter enable signal back to the low-power system includes the following steps: When the system clock is not turned on, the second flip-flop D2 holds the value previously passed from the first flip-flop D1. When the wake-up signal wakes up the PMU, and the PMU controls the clock reset module to generate the system clock signal, the value of the second flip-flop D2 is input to the first XOR circuit NOR1 after passing through the second synchronization signal Sync2. The other input of the first XOR circuit NOR1 is the value of the first flip-flop D1. The two inputs are the same, and the XOR value is the same. If the enable signal feedback value rdata is low, the low-power system reads that the counter has been turned off, thus completing the process of the low-power timer feeding the enable signal back to the low-power system.

7. A low-power system based on clock-free wake-up according to claim 6, characterized in that, The system clock domain of the counter clearing unit includes the third flip-flop D3, the third selector MUX3, the third control circuit Ctrl3, and the fourth synchronization circuit Sync4, wherein the third flip-flop D3 and the fourth synchronization circuit Sync4 use the system clock as the control signal; the operating clock domain of the counter clearing unit includes the fourth flip-flop D4, the fourth selector MUX4, the fourth control circuit Ctrl4, the third synchronization circuit Sync3, the fifth synchronization circuit Sync5, and the edge detection module edge_det2, wherein the fourth flip-flop D4, the third synchronization circuit Sync3, and the fifth synchronization circuit Sync5 use the low-power timer operating clock as the control signal; In the system clock domain, writing 1 to the counter clear register generates a pulse signal to clear the counter. The third control circuit Ctrl3 converts this pulse signal into a level signal. After the third control circuit Ctrl3 controls the third selector MUX3 to make a selection, the signal passes through the third flip-flop D3 to the third synchronization circuit Sync3 and is then input to the fourth selector MUX4. The fourth control circuit Ctrl4 controls the fourth selector MUX4 to select an appropriate value. The value of the fourth selector MUX4 passes through the fourth flip-flop D4 and is input to the edge detection module edge_det2. The edge detection module edge_det2 outputs a clear signal clr. The value of the fourth flip-flop D4 passes through the fourth synchronization circuit Sync4 to reach the system clock domain and is input to the third selector Ctrl3. The value of the third selector Ctrl3 is synchronized to the fourth control circuit Ctrl4 through the fifth synchronization circuit Sync5. The fourth control circuit Ctrl4 controls the fourth selector MUX4 to select an appropriate value, including: when the fifth synchronization circuit Sync5 is high, the fourth control circuit Ctrl4 controls the fourth selector MUX4 to select a low level; otherwise, it selects the value of the third synchronization circuit Sync3.

8. A low-power system based on clock-free wake-up according to claim 7, characterized in that, The third control circuit Ctrl3 controls the third selector MUX3 to select the following: when the CPU controls the counter clear register to clear the counter, the third control circuit Ctrl3 controls the third selector MUX3 to select a high-level signal; otherwise, when the fourth synchronization circuit Snyc4 is high, the third control circuit Ctrl3 controls the third selector MUX3 to select a low-level signal; otherwise, when the fourth synchronization circuit Snyc4 is low, the third selector MUX3 selects the value of the third flip-flop D3.

9. A low-power system based on clock-free wake-up according to claim 8, characterized in that, Feeding back the status of the clear signal to the low-power system includes: the value of the fourth flip-flop D4 reaches the system clock domain through the fourth synchronization circuit Sync4, and after passing through the third control circuit Crtl3, when the fourth synchronization circuit Sync4 is high, the third selector MUX3 selects a low-level signal. The value of the third control circuit Crtl3 reaches the fourth control circuit Ctrl4 after passing through the fifth synchronization circuit Sync5. When the fifth synchronization circuit Sync5 is high, the fourth selector MUX4 outputs a low-level signal, and the clear signal is released. In this way, when the next clear signal arrives, the edge detection module edge_det2 can still detect the rising edge. When the system clock domain generates a clear signal, the system clock is turned off, and the fourth flip-flop D4 remains at a high level. When the system is woken up and the system clock is generated, the output signal of the fourth flip-flop D4 is synchronized to the system clock domain, which changes the value of the third flip-flop D3 to a low level and turns off the clear signal.

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