A storage system and method for implementing a dual-module storage array

Abstract

This invention discloses a storage system and method for implementing a dual-module storage array, relating to the field of data storage and processing technology. The storage system includes a data acquisition end and a storage end; the acquisition end includes a core FPGA and a transmission interface; the storage end includes several storage modules, each comprising a main control FPGA, DDR4 memory, and an SSD; the core FPGA receives input data, performs data distribution control on the received data, and transmits it to the storage modules through the transmission interface; the storage modules receive data sent by the acquisition end and store the data according to their operating mode; the main control FPGA receives data transmitted from the acquisition end from the output end of the transmission interface and controls the data buffer to enter the DDR4 memory; when data can be received in the SSD, the main control FPGA controls the output of data from the DDR4 data buffer to the SSD. This invention enables high-speed data processing throughout the entire data storage path.

Description

Technical Field

[0001] This invention relates to the field of data storage and processing technology, and in particular to a storage system and method capable of implementing a dual-module storage array. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] High-speed, high-capacity data storage is a key technology in the field of data storage. With the continuous development of electronic information technology, reliable storage of high-speed data has become an urgent problem to be solved, and storage devices with high bandwidth and large capacity have become key equipment for scientific research, military information, and electronic warfare. To achieve high-speed data storage, the data storage device must have sufficient data processing bandwidth throughout the entire data processing path; simultaneously, as data storage time increases and data volume grows, the storage device must have sufficient data storage space; furthermore, to meet the storage needs of different modes, a flexible storage array combination control method is required to realize different combinations of storage arrays within the storage device.

[0004] The overall block diagram of the existing large-capacity storage system is as follows: Figure 1 The system is equipped with a VPX connector, a main control FPGA, multiple DDR memory modules, a PCIe switch chip, and SSDs mounted on the PCIe switch chip. The entire system uses the main control FPGA as its control core, externally configured with VPX connectors, DDR memory, and PCIe switch chips, while multiple SSDs are mounted on the PCIe switch chips. The system utilizes the high-speed bus on the VPX connector to input data to be processed; the main control FPGA buffers the received data into the DDR memory; then, the main control FPGA controls the DDR buffer to output data to the PCIe switch chip, and the PCIe switch chip transfers the data to the SSDs for storage.

[0005] The inventors discovered that existing high-capacity storage systems consist of a main control FPGA surrounded by DDR, PCIe switching chips, and SSDs, forming a storage module. When faced with the demand for large-volume data storage, the data storage expansion capability is limited; furthermore, in multi-mode data storage scenarios, it cannot flexibly control data distribution to meet the needs of dual-module storage arrays. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide a storage system and method capable of implementing a dual-module storage array. Data to be processed sequentially passes through an Aurora high-speed transmission port, a DDR4 cache, and a PCIe 3.0-based SSD device, thereby achieving high-speed data processing throughout the entire path. This invention configures N (N≥4) storage modules in the system. When operating in single-module storage mode, the total data storage capacity is the sum of the N storage modules, enabling maximum data storage capacity. This invention configures N storage modules, and any two combinations can be applied to a dual-module storage mode. Data distribution can be flexibly controlled via the FPGA at the acquisition end, thus meeting the requirements of a dual-module storage array.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0008] The first aspect of this invention provides a storage system capable of implementing a dual-module storage array, including a data acquisition end and a storage end; the data acquisition end includes a core FPGA and a transmission interface; the storage end includes several storage modules, each including a main control FPGA, DDR4, and an SSD; the core FPGA receives input data, performs data distribution control on the input data, and transmits it to the storage modules through the transmission interface; the storage modules receive data sent by the data acquisition end and store the data according to the working mode; the main control FPGA receives the data transmitted from the data acquisition end from the output end of the transmission interface and controls the data buffer to enter the DDR4; when the SSD can receive data, the main control FPGA controls the output of data from the data buffer of the DDR4 to the SSD.

[0009] Furthermore, the received data is distributed and controlled according to the system's operating mode, which includes single storage module mode and dual storage module mode.

[0010] Furthermore, when the system is operating in single storage module mode, the core FPGA control data is transmitted sequentially to the storage modules. When the current storage module reaches the total SSD storage space threshold, the core FPGA control data is switched from the current storage module to the next storage module for storage.

[0011] Furthermore, when the system operates in dual-storage module mode, the core FPGA is used to simultaneously output data to the online dual-storage module combination. The online dual-storage module combination first selects two storage modules from all storage modules, and then uses the selected two storage modules to form the online dual-storage module combination.

[0012] Furthermore, for the dual-storage module operation mode, when the two transmission interfaces corresponding to the online dual-storage module combination receive data signals of 1 at the same time, data is transmitted to the storage end. When it is necessary to stop the data storage process, the data transmission at the acquisition end is stopped first, and after a time delay, the data reception at the storage end is stopped.

[0013] A second aspect of the present invention provides a storage method for implementing a dual-module storage array, comprising the following steps:

[0014] The core FPGA at the acquisition end acquires the data to be stored and performs data distribution control.

[0015] The input data is distributed to the storage end through the transmission interface according to the data working mode;

[0016] The storage device will cache the distributed data to the DDR4 memory of the SSD front end via the main control FPGA.

[0017] When data can be received, the main control FPGA controls the output of cached data to the SSD for storage.

[0018] Furthermore, the received data is distributed and controlled according to the system's operating mode, which includes single storage module mode and dual storage module mode.

[0019] Furthermore, when the system is operating in single storage module mode, the core FPGA control data is transmitted sequentially to the storage modules. When the current storage module reaches the total SSD storage space threshold, the core FPGA control data is switched from the current storage module to the next storage module for storage.

[0020] Furthermore, when the system operates in dual-storage module mode, the core FPGA is used to simultaneously output data to the online dual-storage module combination. The online dual-storage module combination first selects two storage modules from all storage modules, and then uses the selected two storage modules to form the online dual-storage module combination.

[0021] Furthermore, for the dual-storage module operation mode, when the two transmission interfaces corresponding to the online dual-storage module combination receive data signals of 1 at the same time, data is transmitted to the storage end. When it is necessary to stop the data storage process, the data transmission at the acquisition end is stopped first, and after a time delay, the data reception at the storage end is stopped.

[0022] The above one or more technical solutions have the following beneficial effects:

[0023] This invention designs a storage system and method that can realize a dual-module storage array. In response to the need for high-speed data storage, the data processing path sequentially passes through the Aurora high-speed transmission port, DDR4, and PCIe 3.0-based SSD, which can realize high-speed data processing throughout the entire data storage path.

[0024] To address the need for large-capacity data storage, this invention integrates M (M≥4) SSDs within a single storage module. Furthermore, it extends the system with N (N≥4) additional storage modules, achieving maximum data storage capacity when operating in single-module mode.

[0025] To address the need for multi-mode data storage, this invention utilizes N parallel storage modules configured in the system. When operating in dual-storage module mode, the system can flexibly form various storage arrays.

[0026] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0027] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0028] Figure 1 This is a general block diagram of an existing high-capacity storage system;

[0029] Figure 2 This is a schematic diagram of a storage system that can realize a dual-module storage array according to Embodiment 1 of the present invention.

[0030] Figure 3(a) is a schematic diagram of the data distribution control principle in the single storage module mode of Embodiment 1 of the present invention;

[0031] Figure 3(b) is a schematic diagram of the data distribution control principle in the dual storage module mode of Embodiment 1 of the present invention. Detailed Implementation

[0032] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0033] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0034] Example 1:

[0035] Embodiment 1 of the present invention provides a storage system capable of implementing a dual-module storage array, such as... Figure 2 The system comprises two parts: a data acquisition end and a storage end. The data acquisition end includes a core FPGA and a transmission interface; the storage end includes several storage modules, each consisting of a main control FPGA, DDR4 memory, and an SSD. This embodiment uses an electronic countermeasures system as an example to acquire electromagnetic signal data from an outdoor testing environment and input it into the storage system of this invention. The core FPGA receives the acquired electromagnetic signal data, performs data distribution control on the received data, and transmits it to the storage modules through the transmission interface. The storage modules receive the data sent by the data acquisition end and store the data according to the operating mode. The main control FPGA receives the data transmitted from the data acquisition end from the transmission interface output and controls the data buffer to enter the DDR4 memory. When the SSD can receive data, the main control FPGA controls the output of data from the DDR4 data buffer to the SSD.

[0036] First, to achieve high-speed data processing, this invention uses an Aurora transmission interface to complete data transmission between each storage module on the acquisition and storage ends. The acquisition end is configured with N (N≥4) Aurora transmission interfaces connected to the storage modules on the storage end. Furthermore, to meet the needs of large-volume data storage, the storage end is equipped with N (N≥4) data storage modules. Each storage module consists of a main control FPGA, M (M≥4) sets of DDR4 memory, and M sets of SSDs. Each SSD on the storage end has a DDR4 memory front-end for data caching to match the varying data write speeds of the SSDs. To achieve high-speed data storage, a PCIe 3.0 interface is used between the main control FPGA and the SSDs on the storage end. Based on this, high-speed data processing is achieved throughout the entire data path.

[0037] In this embodiment, a single Aurora uses 8 lanes, operating in 64B / 66B mode, with a single lane transmission speed of 10Gb / s. Considering overall transmission efficiency, a data transmission speed of 72Gb / s can be guaranteed. Data caching is performed using a single DDR4 chip in a read-write mode. The DDR4 clock rate is 750ps, and the data processing bit width is 512 bits. Considering overall data processing efficiency, a single DDR4 chip can guarantee a data cache rate greater than 64Gb / s. The total data cache processing rate of M (M≥4) DDR4 groups is not less than 256Gb / s. The data processing rate of the PCIe 3.0 interface on a single SSD is not less than 20Gb / s, therefore the maximum data storage rate of M SSD groups is not less than 80Gb / s. In summary, the overall data processing rate of the system described in this embodiment is not less than 72Gb / s.

[0038] Furthermore, the acquisition terminal of this invention can flexibly control data distribution and transmit data to the storage module via the Aurora high-speed transmission interface, thereby flexibly realizing a dual-storage module storage array. Specifically, the received data is distributed and controlled according to the system operating mode, which includes single-storage module mode and dual-storage module mode.

[0039] The FPGA at the acquisition end receives external input data and then performs data distribution control. When the system operates in single-storage module mode, data distribution control is performed according to Figure 3(a), that is, the FPGA at the acquisition end controls the data to be transmitted sequentially to storage module 1, storage module 2, storage module 3, ..., storage module N. In this mode, the system can obtain the maximum data storage capacity. When the system operates in dual-storage module mode, data distribution control is performed according to Figure 3(b). The core FPGA simultaneously outputs data to the online dual-storage module combination. The online dual-storage module combination first selects two storage modules from all storage modules, and then uses the selected two storage modules to form the online dual-storage module combination. The figure shows dual-module storage array combination 1&2. Other combinations include combination 1&3, combination 1&4, ..., combination 1&N, combination 2&3, combination 2&4, ..., combination 2&N, ..., combination (N-1)&N, providing a rich variety of dual-module storage array combination methods.

[0040] When the system operates in single-storage-module mode, to maintain data continuity in the storage system, the core FPGA control data is sequentially transmitted to the storage modules. When the current storage module reaches the threshold of the total storage space of M groups of SSDs, the core FPGA control data switches from the current storage module to the next storage module. In this embodiment, the threshold is set to 95%.

[0041] In the dual-storage module operation mode, when the two Aurora transmission interfaces corresponding to the online dual-storage module combination are simultaneously at 1, data is transmitted to the storage end. When it is necessary to stop the data storage process, the data transmission at the acquisition end is stopped first, and after a time delay of ten milliseconds, the data reception at the storage end is stopped. This ensures that the amount of stored data in the two storage modules is the same.

[0042] The main FPGA on the storage side receives data transmitted from the acquisition end from the Aurora transmission interface output. The main FPGA is responsible for implementing the data interface and corresponding control, and the data is ultimately stored in the SSD. Since the data storage speed of the SSD is not stable, to adapt to the changing data storage speed of the SSD and improve the stability of the storage device, a corresponding DDR4 cache is configured in front of each SSD. The main FPGA first controls the data to enter the DDR4 cache through the write interface between the FPGA and DDR4. When data can be received in the SSD, the FPGA controls the output of data from the DDR4 data read interface cache. DDR4 operates in a read-write mode, and is configured to operate in write-priority mode. That is, as long as the main FPGA receives data, it can write data to the DDR4, and read operations can be performed during write idle cycles. This ensures that as long as the DDR4 operates at a clock rate that meets the system's data processing speed requirements, the system has sufficient data caching capacity to meet the processing speed requirements. Data output from the DDR4 cache is transmitted to the SSD through the PCIe 3.0 interface and ultimately stored. To meet the requirements of high-speed data storage, the main control FPGA controls the parallel writing of data to the SSD to achieve high-speed data storage. In this embodiment, the data is split and written to DDR4 simultaneously. When outputting from the parallel cache, it is then written to the SSD simultaneously to achieve the highest speed data storage.

[0043] Example 2:

[0044] Embodiment 2 of the present invention provides a storage method for implementing a dual-module storage array, comprising the following steps:

[0045] The core FPGA at the acquisition end acquires the data to be stored and performs data distribution control.

[0046] The input data is distributed to the storage end through the transmission interface according to the data working mode; the received data is distributed and controlled according to the system working mode, which includes single storage module mode and dual storage module mode.

[0047] The storage device will cache the distributed data to the DDR4 memory of the SSD front end via the main control FPGA.

[0048] When data can be received, the main control FPGA controls the output of cached data to the SSD for storage.

[0049] When the system is operating in single storage module mode, the core FPGA control data is transmitted to the storage modules sequentially. When the current storage module reaches the total SSD storage space threshold, the core FPGA control data is switched from the current storage module to the next storage module for storage.

[0050] When the system is operating in dual storage module mode, the core FPGA is used to simultaneously output data to the online dual storage module combination. The online dual storage module combination first selects two storage modules from all storage modules, and then uses the selected two storage modules to form the online dual storage module combination.

[0051] In the dual-storage module operation mode, when the two transmission interfaces corresponding to the online dual-storage module combination receive data signals of 1 at the same time, data is transmitted to the storage end. When it is necessary to stop the data storage process, the data transmission at the acquisition end is stopped first, and after a time delay, the data reception at the storage end is stopped.

[0052] The steps and methods involved in the above embodiment two correspond to those in embodiment one. For specific implementation details, please refer to the relevant description section of embodiment one.

[0053] Those skilled in the art will understand that the modules or steps of the present invention described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computer device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. The present invention is not limited to any particular combination of hardware and software.

[0054] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A storage system capable of implementing a dual-module storage array, characterized in that, It includes a data acquisition end and a storage end. The data acquisition end includes a core FPGA and a transmission interface. The storage end includes several storage modules, each containing a main control FPGA, DDR4 memory, and an SSD. The core FPGA receives input data, performs data distribution control on the received data, and transmits it to the storage modules through the transmission interface. The storage modules receive data sent by the data acquisition end and store the data according to the working mode. The main control FPGA receives the data transmitted from the data acquisition end from the output end of the transmission interface and controls the data buffer to enter the DDR4 memory. When the SSD can receive data, the main control FPGA controls the output of data from the DDR4 data buffer to the SSD. The system distributes and controls the received data according to the system's operating mode, which includes single storage module mode and dual storage module mode. When the system is working in single storage module mode, the core FPGA control data is transmitted to the storage module in sequence. When the current storage module reaches the total SSD storage space threshold, the core FPGA control data is switched from the current storage module to the next storage module for storage. When the system is working in dual storage module mode, the core FPGA is used to output data to the online dual storage module combination at the same time. The online dual storage module combination first selects two storage modules from all storage modules, and then uses the selected two storage modules to form the online dual storage module combination. In the dual-storage module operation mode, when the two transmission interfaces corresponding to the online dual-storage module combination receive data signals of 1 at the same time, data is transmitted to the storage end. When it is necessary to stop the data storage process, the data transmission at the acquisition end is stopped first, and after a time delay, the data reception at the storage end is stopped, ensuring that the amount of stored data in the two storage modules is the same.

2. A storage method for a storage system capable of implementing a dual-module storage array as described in claim 1, characterized in that, Includes the following steps: The core FPGA at the acquisition end acquires the data to be stored and performs data distribution control. The received data is distributed to the storage end through the transmission interface according to the data working mode; The storage device will cache the distributed data to the DDR4 memory of the SSD front end via the main control FPGA. When data can be received, the main control FPGA controls the output of cached data to the SSD for storage.

3. The storage method as described in claim 2, characterized in that, The system controls the distribution of received data according to its operating mode, which includes single storage module mode and dual storage module mode.

4. The storage method as described in claim 3, characterized in that, When the system is operating in single storage module mode, the core FPGA control data is transmitted to the storage modules sequentially. When the current storage module reaches the total SSD storage space threshold, the core FPGA control data is switched from the current storage module to the next storage module for storage.

5. The storage method as described in claim 3, characterized in that, When the system is operating in dual storage module mode, the core FPGA is used to simultaneously output data to the online dual storage module combination. The online dual storage module combination first selects two storage modules from all storage modules, and then uses the selected two storage modules to form the online dual storage module combination.

6. The storage method as described in claim 4, characterized in that, In the dual-storage module operation mode, when the two transmission interfaces corresponding to the online dual-storage module combination receive data signals of 1 at the same time, data is transmitted to the storage end. When it is necessary to stop the data storage process, the data transmission at the acquisition end is stopped first, and after a time delay, the data reception at the storage end is stopped.

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